KR101605607B1 - Magnetoresistive random access memory having folded memory array structure - Google Patents

Abstract

Disclosed is a magnetoresistance memory device that realizes a fast write time without increasing the size of the transistor. The magnetoresistive memory device includes a memory block having a plurality of arrays and a driver for controlling a writing operation of the memory block. At least one of the arrays has a folded structure.

Description

[0001] MAGNETORESISTIVE RANDOM ACCESS MEMORY HAVING FOLDED MEMORY ARRAY STRUCTURE WITH A FOLDED MEMORY ARRAY STRUCTURE [0002]

The present invention relates to a magnetoresistive memory device, for example a STT-MRAM.

Random Access Memory (RAM) may be volatile or non-volatile. Volatile RAM loses information stored in volatile RAM each time power is removed, while non-volatile RAM can retain memory contents in non-volatile RAM even when power is removed from memory.

However, a non-volatile RAM has a read / write time that is slower than a volatile RAM, although a non-volatile RAM has the advantage of being able to retain information without applying power.

Magnetoresistive random access memory (MRAM) is a non-volatile memory technology with read / write times comparable to volatile memory. Unlike conventional RAM technology, which stores data such as electrical charges or currents, the MRAM uses magnetic currents.

FIG. 1 shows a structure of a general MTJ, and FIG. 2 shows a structure of a memory cell of a general MRAM.

Referring to FIG. 2, the memory cell of the MRAM includes a magnetic tunnel junction (MTJ) and a transistor MN.

One end of the MTJ is connected to the bit line BL, the gate of the transistor MN is connected to the word line WL, and the source of the transistor MN is connected to the source line SL.

The MTJ comprises a pinned layer 100, a tunnel barrier layer 102 and a free layer 104, as shown in Figures 1 and 2.

The pinned layer 100 and the free layer 104 may be made of a ferromagnetic material, each having a magnetization direction and separated by a tunnel barrier layer 102.

The pinned layer 100 is set to a specific polarity and the polarity of the free layer 104 can freely change to match the polarity of the external field that can be applied.

The change in polarity of the free layer 104 will change the resistance of the MTJ. For example, the MTJ has a low resistance state when the polarities are aligned (A in FIG. 1) and a high resistance state when the polarities are not aligned (FIG. 1B).

As to the structure of the entire MRAM, the MRAM includes a plurality of arrays, and each array includes a plurality of memory cells. At this time, each memory cell has the structure shown in FIG.

For example, if the memory array includes 512 memory cells, the memory cells are aligned in a line.

When writing data to a memory array of such a structure, a specific current must flow through the array for a certain period of time.

As technology evolves, faster write times are required, requiring large currents to flow through the array. In particular, since the length of the array is long, the resistance of the array is inevitably large, and as a result, the size of the transistor must be increased in the structure of the conventional MRAM.

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KR2013-0031186 (Release date: March 28, 2013)

SUMMARY OF THE INVENTION It is an object of the present invention to provide a magnetoresistive memory device that realizes a fast write time without increasing the size of the transistor.

According to an aspect of the present invention, there is provided a magnetoresistive memory device including: a memory block having a plurality of arrays; And a driver for controlling a write operation of the memory block. At least one of the arrays has a folded structure.

A magnetoresistive memory device according to another embodiment of the present invention includes a memory block having an array including a plurality of memory cells; And a driver for controlling a write operation of the memory block. Here, the memory cells each have an MTJ element and a transistor connected to the MTJ element, and the transistors of the memory cells are electrically connected to one source line.

The magnetoresistive memory device according to the present invention has a memory array structure of a folded structure, so that the resistance of the array is smaller than that of the prior art during a write operation. As a result, the magnetoresistive memory device can realize a fast write time without increasing the size of the transistor of the memory cell.

1 is a general MTJ structure.
2 is a diagram showing a structure of a memory cell of a general MRAM.
3 is a diagram illustrating a magnetoresistive memory device according to an embodiment of the present invention.
FIG. 4 illustrates a circuit structure of some memory cells according to an embodiment of the present invention. Referring to FIG.
FIG. 5 is a three-dimensional diagram illustrating the structure of some memory cells according to an embodiment of the present invention. Referring to FIG.
6 is a diagram illustrating a current path in an array according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0001] The present invention relates to a magnetoresistive memory device, for example, a spin transfer torque magnetic random access memory (STT-MRAM). In a write operation, And a write time can be realized without increasing the write time.

Generally, if a fast write time is to be realized, a large current must flow through the cell, and as a result, the size of the transistor must be increased so that the transistor of the cell can withstand a large current.

The present invention proposes a method for solving such a problem of the prior art, and proposes a magnetoresistance memory device capable of realizing a fast write time without increasing the size of a transistor of a memory cell.

FIG. 3 is a diagram illustrating a magnetoresistive memory device according to an embodiment of the present invention. FIG. 4 is a diagram illustrating a circuit structure of some memory cells according to an embodiment of the present invention. FIG. 3 is a diagram showing a three-dimensional structure of some memory cells according to an embodiment. FIG. The resistance shown in FIG. 3 represents the resistance of a metal line corresponding to a bit line (BL) and a source line (SL).

Referring to FIG. 3, the magnetoresistive memory device of this embodiment includes a memory block 300 having arrays 302 and control circuitry.

The control circuitry may include a word line driver 310, a write driver 312, and a control logic 314.

Each array 302 may include, for example, 512 memory cells 304 and may operate in response to a word line drive signal and a column select signal output in response to an externally input address have.

According to one embodiment, each of the arrays 302 may be implemented with a folded structure as shown in FIG.

Each of the memory cells 304 may include one MTJ (Magnetic Tunnel Junction) element and one transistor as shown in FIGS. Here, the transistor may be an N-MOS transistor.

According to one embodiment, a plurality of memory cells 304 may be electrically connected to one source line SL. For example, the source line SL1 may be implemented in a folded structure as shown in FIGS. 4 and 5, and the sources of the transistors MN0 and MN1 of the two memory cells 304 may be one And may be connected to the source line SL1. That is, the memory cells 304 in array 302 may be aligned in two rows.

Conventionally, the source of one transistor is connected to one source line. Thus, if the array includes 512 memory cells, 512 memory cells are arranged in a single line. As a result, the length of the array is inevitably prolonged. As a result, when a current equal to or greater than the threshold value is caused to flow into the array for the write operation, the current decrease due to the resistance of the bit line BL and the source line SL is severe. Therefore, in order to realize fast write time, a large current must flow through the array. As a result, the size of the transistor must be increased to withstand the large current.

On the other hand, the array 302 of the present embodiment includes 512 memory cells 304 in which the array 302 has a folded structure, for example two memory cells 304 are connected to one source line SL, Lt; / RTI > As a result, the length of the array 302 becomes half of the length _Ltot of the conventional array, as shown in Fig. Accordingly, the resistance of the array 302 becomes smaller than that of the conventional resistor, and as a result, a fast write time can be realized without increasing the current flowing to the array 302. [ In addition, since the current flowing to the array 302 is not increased, the size of the transistor of the memory cell 304 may not increase. That is, the present invention can realize fast writing time without increasing the size of the transistor.

Hereinafter, the structure of the memory cell 304 and the operation of the magnetoresistive memory device will be described.

Referring to FIG. 4, one end of the MTJ element MTJ0 or MTJ1 is connected to the bit line BL1, and the other end is connected to the drain of the transistor MN0 or MN1.

The gate of the transistor MN0 or MN1 is connected to the corresponding word line WL0 or WL1 and the sources of the transistors MN0 and MN1 can be connected in common to one source line SL1.

The word line driver 310 selects and drives the word lines WL connected to the memory cells 304 and may be, for example, a decoder.

The write driver 312 may serve to drive the bit lines BL and the source lines SL and may be, for example, a buffer.

According to one embodiment, the write driver 312 may include a column decoder for selecting a bit line and a source line voltage generator for generating a voltage of the source line SL. For example, the column decoder decodes the input column address to generate a decoded column address, and as a result the bit line BL can be selected.

The write driver 312 may also control the voltage applied to the bit line BL and the source line SL to determine the direction of the current flowing to the array 304 for a write operation. For example, the write driver 312 writes the bit line BL and the source line SL so that the magnetization directions of the fixed layer and the free layer of the MTJ element are the same for writing the "0" data to the corresponding memory cell 304. [ Is applied to the bit line BL and the source line SL so that the fixed layer of the MTJ element and the magnetization direction of the free layer are different from each other in order to write "1" data to the corresponding memory cell 304 The voltage can be determined. That is, the write driver 312 outputs the bit line (data) so that the direction of the current flowing to the array 302 when writing the "0" data and the direction of the current flowing to the array 302 when writing the " BL and the source line SL can be determined.

Meanwhile, the MTJ element may include a fixed layer, a tunnel barrier layer and a free layer which are sequentially arranged. The pinned layer has a constant magnetization direction, and the free layer may have a different magnetization direction depending on the direction of a current flowing to the MTJ element. The tunnel barrier layer is arranged between the fixed layer and the free layer and may be an insulating layer.

The control logic unit 314 controls the operation of the word line driver 310 and the write driver 312.

In summary, the array 302 of the memory block 300 of the present embodiment has a folded structure, for example, the sources of a plurality of memory cells 304 can be connected to one source line SL. As a result, the resistance of the array 302 is lowered during a write operation, and a faster write time can be realized without increasing the size of the transistor.

Although two memory cells 304 are described above as being connected to one source line SL, three or more memory cells 304 may be connected to one source line SL.

Hereinafter, the current path in the write operation in the array 302 of the folded structure will be described.

6 is a diagram illustrating a current path in an array according to an embodiment of the present invention. FIG. 6 shows a current flow for writing data with different magnetization directions of the fixed layer and the free layer, and a current flows from the source line SL to the bit line BL. For this purpose, the source line SL is set higher than the voltage of the bit line BL.

The left side of FIG. 6 shows the current flow when the memory cell 0 closest to the source line SL is selected, and the right side of FIG. 6 shows the memory cell 511 farther away from the source line SL It is the current flow when it is selected.

Referring to Fig. 6, the array of this embodiment has a folded structure. Thus, two current paths can be formed.

For example, when memory cell 0 is selected, two paths 600 and 602 can be formed in parallel from source line SL to memory cell 0, as shown on the left side of FIG. 6 And flows from the memory cell 0 to the bit line BL through the current path 604. At this time, the resistance of the array is governed by the short current path 600. As a result, the resistance of the array becomes smaller than that of the prior art arrays, so that the reduction in current due to the resistance of the arrays can be reduced.

As another example, when the memory cell 511 is selected, two paths 610 and 612 may be formed in parallel from the source line SL to the memory cell 511, as shown on the right side of FIG. 6 , And flows from the memory cell 511 to the bit line BL through the current path 614. At this time, the resistance of the array is governed by the short current path 610.

It will be apparent to those skilled in the art that various modifications, additions and substitutions are possible, without departing from the spirit and scope of the invention as defined by the appended claims. Should be regarded as belonging to the following claims.

300: memory block 302: array
304: memory cell 310: word line driver
312 write driver 314 control logic

Claims (9)

A memory block having a plurality of arrays; And
And a driver for controlling a write operation of the memory block,
Wherein the source line of the memory block is connected to the memory cells of the array while having a folded structure, and in a write operation of writing data to a specific one of the memory cells of the array, Wherein a current applied to a specific point flows to multiple paths on the source line, currents flowing to the multiple paths flow to the specific memory cell,
Wherein the memory cells in the array are arranged in multiple lines as the source lines are folded. 2. The method of claim 1, wherein each array comprises a plurality of memory cells, each memory cell including an MTJ element and a transistor,
Wherein the MTJ element is connected to a bit line, the gate of the transistor is connected to a word line, and the sources of the transistors of the plurality of memory cells are connected to one source line. delete delete 2. The apparatus of claim 1,
A word line driver for selecting a word line according to an externally input address; And
And a writing buffer for controlling a specific voltage to be applied to the source line and the bit line according to data to be written.















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