KR101590381B1 - Liquid crystal display device and Method of fabricating the same - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention is directed to preventing the common electrode formed on the front surface of the upper substrate from being totally electric in a liquid crystal display device.

To this end, in the present invention, an electric discharge prevention pattern is formed so as to cover the common electrode exposed to the outside of the seal pattern.

In addition, since the electric discharge prevention pattern is formed by the same process as the column spacer, the electric discharge of the common electrode can be prevented without increasing the manufacturing process.

Liquid crystal display device, common electrode, electric current prevention

Description

[0001] The present invention relates to a liquid crystal display device and a manufacturing method thereof,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a method of manufacturing the same that can effectively prevent the common electrode from being electromagnetically driven.

Generally, the driving principle of a liquid crystal display device utilizes the optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal has a long structure, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal by optical anisotropy, so that image information can be expressed.

At present, an active matrix liquid crystal display (AM-LCD: hereinafter referred to as liquid crystal display) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has excellent resolution and video realization capability, It is attracting attention.

The liquid crystal display device includes a color filter substrate on which a common electrode is formed, an array substrate on which pixel electrodes are formed, and a liquid crystal interposed between the two substrates. In such a liquid crystal display device, The liquid crystal is driven to have excellent properties such as transmittance and aperture ratio.

1 is an exploded perspective view schematically showing a conventional liquid crystal display device.

As shown in the figure, a general liquid crystal display device has a structure in which the array substrate 10 and the color filter substrate 20 are bonded to each other with the liquid crystal layer 30 interposed therebetween.

The array substrate 10 includes a gate wiring 14 and a data wiring 16 which are arranged on the first substrate 12 so as to be crossed with each other to define a plurality of pixel regions P and the two wirings 14 and 16 The thin film transistor Tr is provided in a one-to-one correspondence with the pixel electrode 18 provided in each pixel region P.

The upper portion of the color filter substrate 20 facing the array substrate 10 is formed with a non-display (not shown) such as the gate wiring 14, the data wiring 16, and the thin film transistor Tr Shaped black matrix 25 for framing each pixel region P so as to cover the respective pixel regions P in the pixel region P. The red (R), green A color filter layer 26 including color filter patterns 26a, 26b and 26c of blue (G) and blue (B) colors is formed on the front surface of the color filter layer 26, A common electrode 28 is provided.

Although not shown in the drawings, these two substrates 10 and 20 are formed with a sealant such as a sealant along the edges to prevent leakage of the liquid crystal layer 30 interposed therebetween. At least one outer surface of each of the substrates 10 and 20 is provided with a polarizing plate.

A back light is provided on the outer surface of the array substrate to supply light. An on / off signal of the thin film transistor Tr is sequentially When the image signal of the data line 16 is transmitted to the pixel electrode 18 of the selected pixel region P, the liquid crystal molecules between the pixel electrode 18 and the common electrode 28 And various images can be displayed by the change of the light transmittance.

2 is a schematic cross-sectional view of a conventional liquid crystal display device.

As shown in the figure, the liquid crystal display includes a first substrate 40, a second substrate 70 facing the first substrate 40, and a second substrate 40 facing the first and second substrates 40 and 70 And a seal pattern 90 formed along the edges of the first and second substrates 40 and 70 to prevent the liquid crystal layer 80 from leaking.

The first substrate 40 defines a display area DA and a non-display area NDA around the display area DA. In the display area DA, a gate wiring (not shown) and a data wiring 52 crossing the gate wiring and defining the pixel area P in the display area DA are formed.

In the pixel region P, the gate line and the thin film transistor Tr connected to the data line 52 are positioned. The thin film transistor Tr includes a gate electrode 42 connected to the gate wiring, a gate insulating film 48 covering the gate electrode 42, A semiconductor layer 50 superimposed on the semiconductor layer 50 and source and drain electrodes 54 and 56 spaced from each other on the semiconductor layer 50. [ The semiconductor layer 50 includes an active layer 50a made of pure amorphous silicon and an ohmic contact layer 50b made of amorphous silicon. The source electrode 54 is connected to the data line 52.

In addition, a protective layer 60 is disposed to cover the thin film transistor Tr. The passivation layer 60 includes a drain contact hole 62 exposing a drain electrode 56 of the thin film transistor Tr.

A pixel electrode 68 connected to the drain electrode 56 through the drain contact hole 62 is located in each pixel region P on the passivation layer 60. The pixel electrode 68 is made of a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).

A common wiring 46 is formed in the non-display area NDA of the first substrate 40. [ The common interconnection 46 is covered with the gate insulating film 48 and the passivation layer 60 and the gate insulating film 48 and the passivation layer 60 are formed to expose the common interconnection 46 And at least one common contact hole (64).

On the other hand, on the second substrate 70, a black matrix 72 for covering the non-display area NDA including the gate line, the data line 52 and the thin film transistor Tr is located. On the black matrix 72, a color filter layer 74 is positioned corresponding to the pixel region P. The color filter layer 74 has any one of red, green, and blue.

A common electrode 76 is disposed on the color filter layer 74 to correspond to the entire surface of the second substrate 70. The common electrode 76 is connected to the common wiring 46 on the first substrate 40 and receives a voltage. The common electrode 76 forms an electric field with the pixel electrode 68, whereby the liquid crystal layer 80 is driven. The common electrode 76 is made of a transparent conductive material such as ITO or IZO.

The seal pattern 90 is positioned along the edges of the first and second substrates 40 and 70, that is, in the non-display area NDA, and the first and second substrates 40 and 70 are cemented The liquid crystal layer 80 is prevented from leaking. The seal pattern 90 is in contact with the common electrode 76 and is in contact with the common wiring 46 through the common contact hole 64 at the same time. In this case, the seal pattern 90 has a conductive property by including a conductive ball or the like, and a common voltage is applied to the common electrode 76 from the common wiring 46.

As described above, the common electrode 76 is located on the entire surface of the second substrate 70, that is, the display area DA as well as the non-display area NDA. Therefore, the common electrode 76 is exposed to the outside of the seal pattern 90.

In this case, the common electrode 76 is exposed to the atmosphere, and corrosion due to moisture is generated. Particularly, moisture is gathered at the lower end portion of the liquid crystal display device by the user, and the common electrode 76 is easily transferred to the liquid crystal display device. This causes a problem of deterioration of display quality and life span of the liquid crystal display device.

DISCLOSURE OF THE INVENTION The present invention is intended to solve the problems of degradation of display quality and shortening of life span of a liquid crystal display device as described above.

The present invention also aims at solving the above problems without adding a process.

In order to solve the above problems, the present invention provides a liquid crystal display device comprising: a first substrate on which a display region and a non-display region around the display region are defined; A gate wiring located in the display region on the first substrate; A common wiring located on the non-display area on the first substrate; A data line on the first substrate, the data line being located in the display region and defining a pixel region crossing the gate line; A thin film transistor connected to the gate wiring and the data wiring; A pixel electrode connected to the thin film transistor and located in the pixel region; A second substrate facing the first substrate; A common electrode formed on a front surface of the second substrate; A seal pattern positioned along an edge of the first and second substrates; An anti-tamper pattern on the common electrode, the anti-tamper pattern being located outside the seal pattern and having one side thereof contacting the side surface of the seal pattern; And a liquid crystal layer disposed between the first and second substrates.

According to another aspect of the present invention, there is provided a liquid crystal display comprising: a first substrate on which a display region and a non-display region around the display region are aligned; A gate wiring located in the display region on the first substrate; A common wiring located on the non-display area on the first substrate; A data line on the first substrate, the data line being located in the display region and defining a pixel region crossing the gate line; A thin film transistor connected to the gate wiring and the data wiring; A pixel electrode connected to the thin film transistor and located in the pixel region; A second substrate facing the first substrate; A common electrode formed on a front surface of the second substrate; A seal pattern positioned along an edge of the first and second substrates; An anti-tamper pattern positioned on the common electrode outside the seal pattern and in contact with the one side face and the top face seal pattern of the upper face; And a liquid crystal layer disposed between the first and second substrates.

And a column spacer positioned in the display area and maintaining a constant distance between the first and second substrates.

The column spacer is located on the same layer as the electric discharge prevention pattern and is made of the same material.

One end of the seal pattern is connected to the common wiring and the other end is connected to the common electrode.

A black matrix disposed on the second substrate corresponding to the gate wiring, the data wiring, and the thin film transistor; And a color filter layer corresponding to the pixel region and located on the second substrate, wherein the common electrode is located on the color filter layer.

And the upper surface of the common electrode located in the non-display area is completely covered by the seal pattern and the electric-discharge preventing pattern.

According to another aspect of the present invention, there is provided a method of manufacturing a display device, comprising: forming a gate wiring in a display region of a first substrate and forming a common wiring in a non-display region around the display region; Forming a data line crossing the gate line and defining a pixel region on the first substrate; Forming a thin film transistor connected to the gate line and the data line and located on the first substrate; Forming a pixel electrode connected to the thin film transistor and located in the pixel region; Forming a common electrode on the entire surface of the second substrate on which the display area and the non-display area are defined; Forming an electric discharge preventing pattern covering the column spacer corresponding to the display region and the upper surface of the common electrode located in the non-display region on the common electrode; Forming a seal pattern on an edge of the second substrate; Attaching the first and second substrates such that the inner space is defined by the seal pattern and the column spacer; And forming a liquid crystal layer in an inner space of the first and second substrates, wherein the upper surface of the common electrode of the non-display area is completely covered with the seal pattern and the electric discharge prevention pattern A method of manufacturing a device is provided.

Forming a black matrix on the second substrate corresponding to the gate wiring, the data wiring, and the thin film transistor; And forming a color filter layer corresponding to the pixel region on the second substrate, wherein the common electrode is located on the color filter layer.

The present invention can prevent the common electrode formed on the entire surface of the upper substrate of the liquid crystal display device from being turned on, thereby maintaining the display quality and preventing the life span from being shortened.

In addition, it has the advantage that the above effect can be obtained without adding a separate process.

Hereinafter, the present invention will be described in detail with reference to the drawings.

3 is a cross-sectional view of a liquid crystal display device according to a first embodiment of the present invention.

As shown in the figure, the liquid crystal display according to the first embodiment of the present invention includes a first substrate 110, a second substrate 150 facing the first substrate 110, A liquid crystal layer 170 interposed between the first and second substrates 110 and 150 and a seal 160 formed along the edges of the first and second substrates 110 and 150 to prevent leakage of the liquid crystal layer 170. [ A pattern 180 and an electric discharge prevention pattern 162 located on the second substrate 150 and outside the seal pattern 180. [

The first substrate 110 defines a display area DA and a non-display area NDA around the display area DA. A data line 130 is formed in the display area DA so as to cross the gate line 114 and the gate line 114 and define the pixel area P in the display area DA.

In the pixel region P, the gate line 114 and the thin film transistor Tr connected to the data line 130 are located. The thin film transistor Tr includes a gate electrode 112 connected to the gate wiring 114 and a gate insulating film 118 covering the gate electrode 112. The gate insulating film 118 is formed on the gate insulating film 118, A semiconductor layer 120 overlapping the gate electrode 112 and source and drain electrodes 132 and 134 spaced from each other on the semiconductor layer 120. [ The semiconductor layer 120 includes an active layer 120a made of pure amorphous silicon and an ohmic contact layer 120b made of amorphous silicon. The source electrode 132 is connected to the data line 130.

In addition, a protective layer 140 is disposed to cover the thin film transistor Tr. The passivation layer 140 includes a drain contact hole 142 exposing a drain electrode 134 of the thin film transistor Tr.

A pixel electrode 146 connected to the drain electrode 134 through the drain contact hole 142 is located in each pixel region P on the passivation layer 140. The pixel electrode 146 is made of a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). The pixel electrode 146 overlaps with a part of the gate line 114 to form a storage capacitor Cst.

When a voltage is applied through the gate line 114 to turn on the thin film transistor Tr, a signal voltage is applied to the pixel electrode 146 through the data line 130 and the thin film transistor Tr .

A common wiring 116 is formed in the non-display area NDA of the first substrate 110. The common interconnection 116 is covered with the gate insulating layer 118 and the passivation layer 140 and the gate insulating layer 118 and the passivation layer 140 are formed to expose the common interconnection 116 And includes at least one common contact hole 144.

On the other hand, a black matrix 152 for covering the non-display area NDA including the gate line 114, the data line 130, and the thin film transistor Tr is located on the second substrate 150 have. On the black matrix 152, a color filter layer 154 is positioned corresponding to the pixel region P. The color filter layer 154 includes a red color filter pattern R, a green color filter pattern G, and a blue color filter pattern (not shown).

A common electrode 156 is disposed on the color filter layer 154 to correspond to the entire surface of the second substrate 150. The common electrode 156 is connected to the common wiring 116 on the first substrate 110 to receive a voltage. The common electrode 156 forms an electric field with the pixel electrode 146, whereby the liquid crystal layer 170 is driven. The common electrode 156 is made of a transparent conductive material such as ITO or IZO.

The seal pattern 180 is positioned along the edges of the first and second substrates 110 and 150, that is, in the non-display area NDA, and the first and second substrates 110 and 150 are cemented Thereby preventing leakage of the liquid crystal layer 170. The seal pattern 180 is in contact with the common electrode 156 and is in contact with the common wiring 116 through the common contact hole 119 at the same time. In this case, the seal pattern 180 has a conductive property by including a conductive ball or the like, and a common voltage is applied to the common electrode 156 from the common wiring 116. Although not shown, a plurality of holes may be formed in the common electrode 156 corresponding to the seal pattern 180. As a result, the seal pattern 180 can be irradiated with UV to proceed the curing process.

Meanwhile, the common line 116 and the common electrode 156 may be connected by using conductive dots or the like. In this case, the seal pattern 190 does not have a conductive property.

In addition, a column spacer 160 for maintaining a cell gap is disposed between the first and second substrates 110 and 150. The column spacer 160 is located corresponding to the gate wiring 114, thereby preventing a decrease in the aperture ratio. The column spacer 160 may be positioned corresponding to the data line 130 or the transistor Tr.

The non-display area NDA of the second substrate 150 covers the common electrode 156 and the electric discharge prevention pattern 162 is positioned. That is, since the common electrode 156 is formed on the front surface of the second substrate 150, the common electrode 156 is also formed on the outer side of the seal pattern 180, And covers the upper surface of the common electrode 156. That is, the upper surface of the common electrode 156 located in the non-display area NDA is completely covered with the seal pattern 180 and the electric-discharge prevention pattern 162. One end of the electric discharge prevention pattern 162 is aligned with one end of the seal pattern 180 to completely cover the common electrode 156 of the non-display area NDR. That is, one side of the electric discharge prevention pattern 162 comes into contact with one side of the seal pattern 180. The electric discharge prevention pattern 162 is located on the same layer as the column spacer 162 and is made of the same material. This makes it possible to prevent the manufacturing and fixing of the liquid crystal display device from being complicated and the manufacturing cost to rise.

According to such a configuration, a part of the common electrode 156 formed on the entire surface of the second substrate 150 outside the seal pattern 180 is protected by the electric discharge prevention pattern 162. Therefore, problems of display quality deterioration and shortened life span due to the electric current of the common electrode 156 can be prevented.

FIGS. 4A to 4D are cross-sectional views illustrating a manufacturing process of an array substrate of a liquid crystal display device according to the present invention, and FIGS. 5A to 5D are cross-sectional views illustrating a manufacturing process of a color filter substrate of a liquid crystal display device according to the present invention. 4A to 4D, 5A to 5D and 3, a method of manufacturing a liquid crystal display device according to the present invention will be described.

As shown in FIG. 4A, the first metal layer (not shown) is formed on the first substrate 110 and patterned by a mask process to form the gate wiring 114 extending along the first direction, The gate electrode 112 extending from the gate wiring 114 and the common wiring 116 are formed. The gate wiring 114 and the gate electrode 112 are located in the display area DA and the common wiring 116 is located in the non-display area NDA. The first metal layer is made of any one of aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), copper (Cu), and copper alloy.

Next, the gate insulating film 118 is formed by depositing an inorganic insulating material such as silicon oxide or silicon nitride on the gate wiring 114, the gate electrode 112, and the common wiring 116.

Next, as shown in FIG. 4B, a pure amorphous silicon layer (not shown) and an impurity amorphous silicon layer (not shown) are continuously deposited on the gate insulating layer 118 and patterned by a mask process, The active layer 120a and the ohmic contact layer 120b are formed corresponding to the electrode 112. [ The active layer 120a and the ohmic contact layer 120b form a semiconductor layer 120. [

Next, one of aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), copper (Cu), and copper alloy is deposited on the semiconductor layer 120 and the gate insulating layer 118 to form a second metal layer And the source electrode 132 and the drain electrode 134 are formed on the semiconductor layer 120. The source electrode 132 and the drain electrode 134 are formed on the semiconductor layer 120 by a mask process. The gate electrode 112, the gate insulating layer 118, the semiconductor layer 120, the source electrode 132, and the drain electrode 134 form the thin film transistor Tr.

The data line 130 connected to the source electrode 132 is formed on the gate insulating layer 118. The data line 130 intersects the gate line 114 to define the pixel region P. [

4C, an inorganic insulating material such as silicon oxide or silicon nitride is deposited on the source electrode 132, the drain electrode 134, and the data line 130, 140 are formed. The passivation layer 140 may be formed of an organic insulating material such as benzocyclobutene (BCB) or photo acryl. Thereafter, the protective layer 140 is patterned by a mask process to form the drain contact hole 142 exposing the drain electrode 134. The common contact hole 144 exposing the common wiring 116 is formed by patterning the protection layer 140 and the gate insulating film 118 under the protection layer 140.

Next, as shown in FIG. 4D, a transparent conductive material layer (not shown) is deposited by depositing ITO or IZO on the passivation layer 140. Then, the transparent conductive material layer is patterned to form the pixel electrode 146 connected to the drain electrode 134 of the thin film transistor Tr through the drain contact hole 142, thereby obtaining an array substrate.

The black matrix 152 is formed on the second substrate 150 as shown in FIG. 5A. The black matrix 152 blocks the light leakage corresponding to the gate wiring 114 and the non-display area NDA formed on the first substrate 110. Meanwhile, the black matrix 152 may be further formed corresponding to the data line 130 and the thin film transistor Tr. That is, the black matrix 152 located in the display area DA has a lattice shape to expose the pixel area P.

Next, the color filter layer 154 is formed on the second substrate 150 on which the black matrix 152 is formed. The color filter layer 154 includes a red color filter pattern R, a green color filter pattern G, and a blue color filter pattern (not shown). The color filter layer 154 may be omitted when implementing a monochrome image.

5B, the common electrode 156 is formed on the entire surface of the second substrate 150, covering the color filter layer 154 and the black matrix 152 of the non-display area NDA, . The common electrode 156 is made of a transparent conductive material such as ITO or IZO.

Next, as shown in FIG. 5C, an organic material layer 190 having a photosensitive property is formed on the common electrode 156. Next, as shown in FIG. For example, the organic material layer 190 may have a negative photosensitive characteristic, and the organic material layer 190 may be formed of photo-acryl or benzocyclobutene (BCB). have. Since the organic material layer 190 is used as a column spacer (160 in FIG. 3), it is preferable that the organic material layer 190 has a negative photosensitive characteristic in which a light receiving portion remains.

Next, an exposure mask 192 having a transmissive portion A, a transflective portion B, and a blocking portion C is disposed on the organic material layer 190. The transmissive portion A corresponds to the column spacer 160 and the transflective portion B corresponds to the electric discharge prevention pattern 162. [ The transmissivity of the transflective portion B is smaller than that of the transmissive portion A and larger than that of the blocking portion C.

When the exposing process is performed on the organic material layer 190 using the exposure mask 192, the characteristics of the organic material layer 190 corresponding to the transmissive portion A are completely changed, The characteristic of the organic material layer 190 corresponding to the transflective portion B changes only partially and the characteristic of the organic material layer 190 corresponding to the blocking portion C does not change.

5D, the organic material layer 190 corresponding to the cut-off portion C is completely removed, and when the organic material layer 190 is exposed to light, The organic material layer 190 corresponding to the column A is left without being removed at all to form the column spacer 160. In addition, only a part of the organic material layer 190 corresponding to the transflective layer (B) is removed, and the remaining part forms the electric discharge prevention pattern 162. The color filter substrate can be obtained by the above process.

Next, although not shown, the seal pattern 180 is formed along the edges of the first and second substrates 110 and 150 to attach the first and second substrates 110 and 150 together. The column spacer 160 is in contact with the pixel electrode 146 or the passivation layer 140 which is the uppermost structure formed on the first substrate 100 so that the gap between the first and second substrates 110 and 150 Thereby maintaining a uniform cell gap. The seal pattern 180 is located in the non-display area NDR and the end of the electric discharge prevention pattern 162 coincides to completely cover the common electrode 156 of the non-display area NDR, The common electrode 156 may be turned on. Next, the liquid crystal display device according to the present invention can be obtained by injecting the liquid crystal layer 170 into a space between the first and second substrates 110 and 150.

6 is a cross-sectional view of a liquid crystal display device according to a second embodiment of the present invention.

As shown in the drawing, the liquid crystal display according to the second embodiment of the present invention includes a first substrate 210, a second substrate 250 facing the first substrate 210, A liquid crystal layer 270 interposed between the first and second substrates 210 and 250 and a liquid crystal layer 270 formed along the edges of the first and second substrates 210 and 250 to prevent the liquid crystal layer 270 from leaking A seal pattern 280 and an electric discharge prevention pattern 262 located on the second substrate 250 outside the seal pattern 280.

The first substrate 210 defines a display area DA and a non-display area NDA around the display area DA. A data line 230 is formed in the display area DA to intersect the gate line 214 and the gate line 214 and define the pixel area P in the display area DA.

In the pixel region P, the gate line 214 and the thin film transistor Tr connected to the data line 230 are positioned. The thin film transistor Tr includes a gate electrode 212 connected to the gate wiring 214, a gate insulating film 218 covering the gate electrode 212, A semiconductor layer 220 overlapping the gate electrode 212 and source and drain electrodes 232 and 234 spaced from each other on the semiconductor layer 220. The semiconductor layer 220 includes an active layer 220a made of pure amorphous silicon and an ohmic contact layer 220b made of amorphous silicon. The source electrode 232 is connected to the data line 230.

In addition, a protective layer 240 is disposed to cover the thin film transistor Tr. The passivation layer 240 includes a drain contact hole 242 exposing the drain electrode 234 of the thin film transistor Tr.

A pixel electrode 246 connected to the drain electrode 234 through the drain contact hole 242 is located in each pixel region P on the passivation layer 240. The pixel electrode 246 is made of a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). The pixel electrode 246 overlaps with a part of the gate wiring 214 to form a storage capacitor Cst.

When a voltage is applied through the gate line 214 to turn on the thin film transistor Tr, a signal voltage is applied to the pixel electrode 246 through the data line 230 and the thin film transistor Tr .

A common wiring 216 is formed in the non-display area NDA of the first substrate 210. [ The common interconnection 216 is covered with the gate insulating layer 218 and the passivation layer 240 and the gate insulating layer 218 and the passivation layer 240 are formed to expose the common interconnection 216 And at least one common contact hole 244.

On the other hand, a black matrix 252 for covering the non-display region NDA including the gate wiring 214, the data line 230, and the thin film transistor Tr is located on the second substrate 250 have. A color filter layer 254 is disposed on the black matrix 252 in correspondence with the pixel region P. The color filter layer 254 includes a red color filter pattern R, a green color filter pattern G, and a blue color filter pattern (not shown).

A common electrode 256 is disposed on the color filter layer 254 to correspond to the entire surface of the second substrate 150. The common electrode 256 is connected to the common wiring 216 on the first substrate 210 and receives a voltage. The common electrode 256 forms an electric field with the pixel electrode 246, whereby the liquid crystal layer 270 is driven. The common electrode 256 is made of a transparent conductive material such as ITO or IZO.

The seal pattern 180 is positioned along the edges of the first and second substrates 210 and 250, that is, in the non-display area NDA, and the first and second substrates 210 and 250 are bonded together The leakage of the liquid crystal layer 270 is prevented. The seal pattern 280 is in contact with the common electrode 256 and is in contact with the common wiring 216 through the common contact hole 219 at the same time. In this case, the seal pattern 280 has a conductive property by including a conductive ball or the like, and a common voltage is applied to the common electrode 256 from the common wiring 216. Although not shown, a plurality of holes may be formed in the common electrode 256 corresponding to the seal pattern 280. Thus, the seal pattern 280 can be irradiated with UV to proceed the curing process.

Meanwhile, the common line 216 and the common electrode 256 may be connected by using conductive dots or the like. In this case, the seal pattern 290 does not have a conductive property.

In addition, a column spacer 260 for maintaining a cell gap is disposed between the first and second substrates 210 and 250. The column spacer 260 is located corresponding to the gate wiring 2140, thereby preventing the aperture ratio from lowering. The column spacer 260 may be positioned corresponding to the data line 230 or the transistor Tr.

The non-display area NDA of the second substrate 250 covers the common electrode 256 and the electric discharge prevention pattern 262 is positioned. That is, the common electrode 256 is also formed outside the seal pattern 280 because the common electrode 256 is formed on the front surface of the second substrate 250. The electric contact prevention pattern 262 is formed on the outside of the seal pattern 280 And covers the upper surface of the common electrode 256. That is, the upper surface of the common electrode 156 located in the non-display area NDA is completely covered with the seal pattern 180 and the electric-discharge prevention pattern 162. The electric discharge prevention pattern 262 is disposed to partially overlap the seal pattern 280 to prevent the common electrode 256 from being exposed due to the alignment error of the seal pattern 290. That is, one side surface and the upper surface of the electric discharge prevention pattern 262 are positioned to contact the seal pattern 280. The electric discharge prevention pattern 262 is located on the same layer as the column spacer 262 and is made of the same material. This makes it possible to prevent the manufacturing and fixing of the liquid crystal display device from being complicated and the manufacturing cost to rise.

According to such a configuration, a portion of the common electrode 256 formed on the entire surface of the second substrate 250 outside the seal pattern 280 is protected by the electric discharge prevention pattern 262. Therefore, the problem of the display quality deterioration and the shortening of the life span of the common electrode 256 can be prevented.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It can be understood that

1 is an exploded perspective view schematically showing a conventional liquid crystal display device.

2 is a schematic cross-sectional view of a conventional liquid crystal display device.

3 is a cross-sectional view of a liquid crystal display device according to a first embodiment of the present invention.

4A to 4D are cross-sectional views illustrating a manufacturing process of an array substrate of a liquid crystal display device according to the present invention.

5A to 5D are cross-sectional views illustrating a manufacturing process of a color filter substrate of a liquid crystal display device according to the present invention.

6 is a cross-sectional view of a liquid crystal display device according to a second embodiment of the present invention.

Claims (10)

A first substrate on which a display region and a non-display region around the display region are defined; A gate wiring located in the display region on the first substrate; A common wiring located on the non-display area on the first substrate; A data line on the first substrate, the data line being located in the display region and defining a pixel region crossing the gate line; A thin film transistor connected to the gate wiring and the data wiring; A pixel electrode connected to the thin film transistor and located in the pixel region; A second substrate facing the first substrate; A common electrode formed on a front surface of the second substrate; A seal pattern positioned along an edge of the first and second substrates; An anti-tamper pattern on the common electrode, the anti-tamper pattern being located outside the seal pattern and having one side thereof contacting the side surface of the seal pattern; And a liquid crystal layer disposed between the first and second substrates, And the upper surface of the common electrode located in the non-display area is completely covered by the seal pattern and the electric-discharge preventing pattern. A first substrate on which a display region and a non-display region around the display region are defined; A gate wiring located in the display region on the first substrate; A common wiring located on the non-display area on the first substrate; A data line on the first substrate, the data line being located in the display region and defining a pixel region crossing the gate line; A thin film transistor connected to the gate wiring and the data wiring; A pixel electrode connected to the thin film transistor and located in the pixel region; A second substrate facing the first substrate; A common electrode formed on a front surface of the second substrate; A seal pattern positioned along an edge of the first and second substrates; An anti-tamper pattern positioned on the common electrode outside the seal pattern and in contact with the one side face and the top face seal pattern of the upper face; And a liquid crystal layer disposed between the first and second substrates And the liquid crystal display device. 3. The method according to claim 1 or 2, And a column spacer disposed in the display region and maintaining a constant distance between the first and second substrates. The method of claim 3, Wherein the column spacer is located on the same layer as the electric discharge prevention pattern and is made of the same material. 3. The method according to claim 1 or 2, Wherein one end of the seal pattern is connected to the common wiring and the other end is connected to the common electrode. 3. The method according to claim 1 or 2, A black matrix disposed on the second substrate corresponding to the gate wiring, the data wiring, and the thin film transistor; And a color filter layer corresponding to the pixel region and located on the second substrate, And the common electrode is located on the color filter layer. 3. The method of claim 2, And the upper surface of the common electrode located in the non-display area is completely covered by the seal pattern and the electric-discharge preventing pattern. Forming a gate wiring in a display region of the first substrate and forming a common wiring in a non-display region around the display region; Forming a data line crossing the gate line and defining a pixel region on the first substrate; Forming a thin film transistor connected to the gate line and the data line and located on the first substrate; Forming a pixel electrode connected to the thin film transistor and located in the pixel region; Forming a common electrode on the entire surface of the second substrate on which the display area and the non-display area are defined; Forming an electric discharge preventing pattern covering the column spacer corresponding to the display region and the upper surface of the common electrode located in the non-display region on the common electrode; Forming a seal pattern on an edge of the second substrate; Attaching the first and second substrates such that the inner space is defined by the seal pattern and the column spacer; And forming a liquid crystal layer in an inner space of the first and second substrates, And the upper surface of the common electrode of the non-display area is completely covered by the seal pattern and the electric-discharge preventing pattern. 9. The method of claim 8, Forming a black matrix on the second substrate corresponding to the gate wiring, the data wiring, and the thin film transistor; And forming a color filter layer corresponding to the pixel region on the second substrate, And the common electrode is located on the color filter layer. delete

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