KR101582612B1

KR101582612B1 - Coaxial through silicon via structure and manufacturing method thereof

Info

Publication number: KR101582612B1
Application number: KR1020140052324A
Authority: KR
Inventors: 김준철; 김동수; 박세훈; 육종민
Original assignee: 전자부품연구원
Priority date: 2014-04-30
Filing date: 2014-04-30
Publication date: 2016-01-05
Also published as: KR20150125272A

Abstract

The present invention relates to a coaxial through silicon via structure.
The present invention relates to a semiconductor device comprising a substrate on which a cavity surrounding a sidewall of a central pole is formed, an inner conductor formed on a sidewall of the center pole and an upper surface of the sidewall, An outer conductor formed on a portion of the substrate extending from the top to the outer periphery, and a filling insulating layer formed in the region including the cavity to electrically insulate the inner conductor and the outer conductor from each other.
According to the present invention, by using a silicon structure having a high aspect ratio as a part of a core metal of TSV, it is possible to solve the difficulty of a high-aspect ratio plating process and shorten the plating time, Can be manufactured.

Description

TECHNICAL FIELD [0001] The present invention relates to a coaxial through silicon via structure and a method of manufacturing the same.

The present invention relates to a coaxial through silicon via structure and a manufacturing method thereof. More particularly, the present invention relates to a coaxial through silicon via technique for three-dimensional interconnection, which is very simple in fabrication process and yet has a new coaxial through silicon To a via structure and a manufacturing method thereof.

In the case of a general through silicon via (TSV) technique, there is a problem that an electrical loss is very large at a high frequency due to a lossy characteristic of silicon.

Further, in the case of a general filling TSV and a coaxial TSV, since the core portion must be completely filled with metal, the manufacturing time becomes long, and due to the difference in thermal expansion coefficient between the silicon substrate and the metal in the high- Cracks can occur.

To solve this problem, U.S. Patent Application Publication No. US 2011/0095435 A1 proposes a technique of forming a silicon center post on the core portion and coating the metal only on the side wall of the center post.

However, according to this conventional technique, as shown in FIG. 1 (a), since the upper electrode portion after CMP is finally exposed only to the thickness of the plated metal, it has a metal strip shape when viewed from the top. There is a disadvantage that a contact process for connection with the additional forming electrode becomes difficult. This metal contact problem causes problems such as poor electrical connection and electrode pattern alignment in the future process, which leads to a decrease in mass productivity.

2 (a), since the upper primary contact region must be larger than the area of the lower metal core portion, the clearance D1 defined by the distance between the signal line and the ground ) Is reduced.

Also, according to the related art, a structure is shown in which a primary insulating layer is formed, a primary metal layer is formed, a hole is filled with a polymer, and then an upper polymer and a metal layer are removed. In general, the primary insulating layer is silicon dioxide, which has a limited thickness within a few microns and is generally less than 1 micron. Therefore, in this structure, when the electrode is formed on the upper part, the thickness of the insulating layer is so thin that electrical loss of the wiring formed may be large, so that there is a problem that additional insulating layer formation is indispensably required.

U.S. Published Patent Application No. US 2011/0095435 A1 (public date: April 28, 2011, name: COAXIAL THROUGH-SILICON VIA)

The present invention provides a coaxial through silicon via structure having excellent electrical characteristics even in the case of Lossy silicon and a method for manufacturing the same.

Another object of the present invention is to provide a novel coaxial through silicon via structure having a lining structure which is very simple in manufacturing process as compared with existing TSVs and has almost the same performance at high frequencies, and a manufacturing method thereof.

The present invention also relates to a coaxial through silicon via structure which can reduce the amount of metal to be filled in a silicon substrate and can prevent generation of cracks due to a difference in thermal expansion coefficient between the silicon substrate and the filling metal, And to provide a method of manufacturing the same.

Further, the present invention uses a silicon structure having a high aspect ratio as a part of a core metal of TSV, thereby solving the difficulty of a high-step-ratio plating process and shortening a plating time, To provide a silicon via structure and a manufacturing method thereof.

According to an aspect of the present invention, there is provided a coaxial through silicon via structure comprising: a substrate having a cavity surrounding a sidewall of a central pole, a sidewall formed on the sidewall of the center pole, An outer conductor formed on a side wall of the cavity and a portion of the substrate extending outwardly from the top of the side wall of the cavity and the cavity to electrically insulate the inner conductor and the outer conductor, And a filling insulating layer formed in the region.

In the coaxial through silicon via structure according to the present invention, the filling insulating layer is formed on the substrate so as to cover the internal conductor and the external conductor.

In the coaxial through silicon via structure according to the present invention, the filling insulating layer is formed with wiring via holes for filling a conductive material for wiring for electrically connecting the internal conductor and the external conductor to the outside. do.

In the coaxial through silicon via structure according to the present invention, the filling insulating layer has a thickness substantially equal to a thickness of the external conductor, and is formed on a surface of the substrate extending from the external conductor.

The coaxial through silicon via structure according to the present invention is characterized by further comprising a first insulating layer formed to cover the charge insulating layer, the internal conductor, and the external conductor.

In the coaxial through silicon via structure according to the present invention, the first insulating layer is formed with wiring via holes for filling a conductive material for wiring for electrically connecting the internal conductor and the external conductor to the outside .

The method of manufacturing a silicon via structure according to the present invention includes the steps of: forming a cavity surrounding a central pole and a sidewall of the central pole by etching one surface of the substrate; A conductive layer forming step of forming a conductive layer on the substrate and a portion of the substrate extending above the sidewalls of the cavity; a filling insulating layer forming step of forming a filling insulating layer in a region including the cavity; And separating the conductive layer into an inner conductor formed on the center pole and an outer conductor formed on the sidewall of the cavity to polish the other surface of the substrate to remove the conductive layer formed on the center pole.

In the manufacturing method of a coaxial through silicon via structure according to the present invention, in the filling insulating layer forming step, the filling insulating layer is formed using an organic lamination process.

In the method of manufacturing a silicon via structure for a coaxial through-hole according to the present invention, the organic lamination process is performed in a vacuum atmosphere.

In the manufacturing method of a coaxial through silicon via structure according to the present invention, in the filling insulating layer forming step, the filling insulating layer is formed on the substrate so as to cover the conductive layer.

The method for fabricating a coaxial through silicon via structure according to the present invention includes the steps of forming a via hole for forming wiring via holes in the filling insulating layer and forming a wiring conductive material for electrical connection with the outside to the wiring via holes, And forming an electrode pad by filling the electrode pad.

The method for fabricating a coaxial through silicon via structure according to the present invention is characterized by further comprising a planarizing step of planarizing the filling insulating layer to expose the conductive layer after the filling insulating layer forming step.

In the method of manufacturing a silicon via structure according to the present invention, after the planarization step, a filling insulating layer having a thickness substantially equal to the thickness of the conductive layer remains on the substrate.

The method of manufacturing a silicon via structure according to the present invention is characterized by further comprising a first insulating layer forming step of forming a first insulating layer to cover the filling insulating layer and the conductive layer.

The method for manufacturing a silicon via structure according to the present invention is characterized in that the method comprises a via hole forming step of forming wiring via holes in the first insulating layer after the first insulating layer forming step and a via hole forming step of forming a via hole for electrically connecting the wiring via holes to the outside And an electrode pad forming step of filling the material to form an electrode pad.

According to the present invention, there is provided an effect of providing a coaxial through silicon via structure having excellent electrical characteristics even in the case of Lossy silicon and a method of manufacturing the same.

Also, there is an effect that a new coaxial through silicon via structure having a lining structure with a very simple manufacturing process as compared with the existing TSV and having almost the same performance at high frequency, and a manufacturing method thereof are provided.

Also, there is provided a coaxial through-silicon via structure that can reduce the amount of metal to be filled in a silicon substrate and prevent generation of cracks due to a difference in thermal expansion coefficient between the silicon substrate and the filler metal, It is effective.

Also, by using a silicon structure having a high aspect ratio as a part of a core metal of TSV, it is possible to solve the difficulty of a high-aspect ratio plating process and to manufacture a coaxial through-silicon via structure And a manufacturing method thereof are provided.

FIG. 1 is a cross-sectional view illustrating a top view of a conventional silicon via structure according to the present invention.
FIG. 2 is a diagram for explaining the contact process in the coaxial through silicon via structure according to the present invention and the related art.
3 is a cross-sectional view of a coaxial through silicon via structure according to the first embodiment of the present invention.
4 is a cross-sectional view of a coaxial through silicon via structure according to a second embodiment of the present invention.
5 to 10 are views for explaining a method of manufacturing a silicon via structure according to a first embodiment of the present invention.
11 to 18 are views for explaining a method of manufacturing a silicon via structure according to a second embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a cross-sectional view of a conventional silicon via structure according to the present invention. FIG. 2 is a cross-sectional view for explaining the contact process, and FIG. 3 is a cross- Sectional view of the coaxial through silicon via structure according to the second embodiment of the present invention.

1 to 3, a coaxial through silicon via structure according to a first embodiment of the present invention includes a substrate 10, an internal conductor 22, an external conductor 24, a filling insulating layer 30, And an electrode pad.

The substrate 10 is provided with a central pole 12 and a cavity 14 surrounding the sidewalls of the central pole 12. For example, the substrate 10 may be configured to have a silicon material and the center pawl 12 and the cavity 14 may be formed on the substrate 10 in the shape of the center pawl 12 and the cavity 14 After the mask pattern having the corresponding shape is formed, the substrate 10 is etched. An inner conductor 22 to be described later is formed in the center pole 12 and a filling insulating layer 30 for electrically insulating the inner conductor 22 and the outer conductor 24 is formed in the cavity 14 It is filled. Here, the diameter of the center pole 12 is a parameter that can determine the core diameter of the through via in the coaxial through silicon via structure according to the first embodiment of the present invention, and the cavity 14 is a It is a parameter that can determine the outer diameter of a coaxial via.

The inner conductor (22) is formed on the side wall and the upper surface of the center pole (12). The inner conductor 22 is electrically insulated from the outer conductor 24 by the filling insulating layer 30 to be described later, and serves as a signal line for transmitting a signal.

1 and 2, the inner conductor 22 is formed so as to cover not only the side wall of the center pole 12 but also the entire upper surface of the center pole 12.

When the internal conductor 22 is formed as described above, the following effects are obtained.

In order to realize a silicon via structure with a coaxial through-hole, the center pole 12, which is a silicon structure having a high aspect ratio, is used as a part of the core metal, thereby solving the difficulty of the high-stiffness plating process and shortening the plating time . The step ratio is the ratio of the height and diameter of the inner conductor 22. That is, conventionally, in order to realize the silicon via structure of the coaxial penetration, since the entire core must be formed of metal, the plating time for forming the core metal becomes long, and cracks are generated due to the difference of the thermal expansion coefficient in the high temperature process I could. However, in this embodiment, in order to form the internal conductor 22, a metal for forming the internal conductor 22 in a state where the center pole 12 is formed on the substrate 10 without filling the entire core with metal Is coated on the surface of the center pawl 12, the plating time is shortened and the risk of occurrence of cracks due to the difference in thermal expansion coefficient is reduced. That is, the amount of metal to be plated is small, and the plating time is shortened, and the risk of cracking due to the difference in thermal expansion coefficient between the silicon substrate 10 and the plated metal can be reduced.

A diffusion barrier film, an insulating film, a metal seed layer, or the like required in a general through-silicon via (TSV) process is formed between the internal conductor 22 and the silicon substrate 10 and between the external conductor 24 and the substrate 10 May be additionally formed.

As the material of the inner conductor 22 and the outer conductor 24, a metal generally used for a semiconductor process such as copper, gold, aluminum, or nickel may be used. Depending on the application frequency, the thickness of the coating can be varied in consideration of the depth, and the thickness can be generally set to a few micrometers.

The outer conductor 24 is formed on a portion of the substrate 10 that extends outwardly from the sidewall of the cavity 14 and from the top of the sidewall of the cavity 14. The inner conductor 22 and the outer conductor 24 are coated with the same conductive layer on the silicon substrate 10 on which the center pole 12 and the cavity 14 are formed, And thereafter, this conductive layer is separated. Thus, the inner conductor 22 and the outer conductor 24 are made of the same material and have substantially the same thickness. On the other hand, the outer conductor 24 is formed not only on the sidewall of the cavity 14, but also on a portion of the substrate 10 which extends from the top of the sidewall of the cavity 14 to the outside.

The effect obtained by forming the external conductor 24 in this way is as follows.

1 and 2, the outer conductor 24 is formed not only on the sidewall of the cavity 14 but also on a portion of the substrate 10 that extends outward from the top of the sidewall of the cavity 14 And the inner conductor 22 is also formed on the upper surface of the center pole 12, the convenience of the contact process for electrical connection with the outside is improved.

More specifically, according to the prior art, after the CMP, the upper electrode portion is exposed only to the thickness of the plated metal, so that it has a metal strip shape when viewed from above. Therefore, contact process is difficult. This metal contact problem causes problems such as poor electrical connection and electrode pattern alignment in the future process, which leads to a decrease in mass productivity.

According to the present embodiment, on the other hand, the outer conductor 24 is formed not only on the sidewall of the cavity 14 but also on a part of the substrate 10 which extends outward from the upper portion of the sidewall of the cavity 14, (22) is formed not only on the sidewall of the center pole (12) but also on the upper surface thereof, the convenience of the contact process for electrical connection with the outside is greatly improved.

Further, according to this embodiment, since the clearance D2 indicating the degree of separation between the internal conductor 22, which is a signal line, and the external conductor 24, which is a ground, can be secured more widely than in the prior art, For example, a coaxial through silicon via structure that is finer and occupies a smaller area can be realized.

More specifically, according to the related art, since the upper primary contact region must be larger than the area of the lower metal core portion, the clearance D1 defined by the distance between the signal line and the ground is reduced. However, The outer conductor 24 is formed on the upper portion of the center pole 12 and the outer conductor 24 so as to extend to the outer periphery of the substrate 10 above the sidewall of the cavity 14 , And the clearance D2 is maintained at a distance between the signal line and the ground.

The filling insulating layer 30 is formed in the region including the cavity 14 to electrically insulate the inner conductor 22 from the outer conductor 24. [

More specifically, the filler dielectric layer 30 is not only filled to fill the cavities 14 but also on the substrate 10 so as to completely cover the internal conductor 22 and the external conductor 24 Respectively. For example, the thickness of the filling insulating layer 30 formed on the substrate 10 may be set to 20 to 40 mu m. When the filling insulating layer 30 is formed on the upper surface of the substrate 10 in the process of filling the filling insulating layer 30 into the cavity 14, The electrical loss of the wiring can be reduced. In order to secure a sufficient thickness, the filling insulating layer 30 can be formed by using a polymer capable of forming a thick insulating layer.

The structure, forming method and effect of the filling insulating layer 30 will be described in detail with reference to the prior art.

1 and 2, the prior art has a structure in which a primary insulating layer is formed, a primary metal layer is formed, a hole is filled with a polymer, and then an upper polymer and a metal layer are removed. Lt; / RTI > In general, the primary insulating layer is silicon dioxide, which has a limited thickness within a few microns and is generally less than 1 micron. Therefore, when the electrode is formed on the upper part of the structure, the thickness of the insulating layer is so small that electrical loss of the wiring formed may be large, so that formation of an additional insulating layer is indispensable. If the insulating layer can be left to have a uniform thickness on the substrate 10 other than the hole filling, the electrical effect of the upper wiring can be improved, but the conventional structure must expose the electrodes, Therefore, it is necessary to remove all of the insulating layer on the electrode by CMP process or the like. Therefore, additional insulating layer formation is necessarily required.

On the other hand, according to the present embodiment, the upper surface of the filling insulating layer 30 can be subjected to an upper electrical connection and wiring process without performing a CMP process, and the thick filling insulating layer 30 can be used as it is.

The filling insulating layer 30 is formed with wiring via holes for filling a conductive material for wiring for electrically connecting the internal conductor 22 and the external conductor 24 to the outside. Reference numerals 52, 54 and 56 denote electrode pads.

4 is a cross-sectional view of a coaxial through silicon via structure according to a second embodiment of the present invention. Hereinafter, the second embodiment will be described focusing on the filling insulating layer 32 and the first insulating layer 40 which are different from the first embodiment in order to avoid duplication of description.

Referring to FIG. 4, in comparison with the first embodiment described in detail above, the second embodiment differs in shape of the filling insulating layer 32 and additionally includes the first insulating layer 40.

The filler insulation layer 32 is not only filled in the cavity 14 but also has a thickness substantially equal to the thickness of the outer conductor 24 and extends from the outer conductor 24 to form on the surface of the substrate 10 .

The first insulating layer 40 is formed so as to cover the filling insulating layer 32, the internal conductor 22 and the external conductor 24 and the first insulating layer 40 is provided with the internal conductor 22 And via holes for filling wiring conductive material for electrically connecting the external conductor 24 to the outside are formed. Reference numerals 52, 54, and 56 denote electrode pads formed by filling the via holes with conductive material.

According to the second embodiment of the present invention, since the filling insulating layer 32 of the thickness of the plated metal, that is, the outer conductor 24 and the inner conductor 22, is secured on the substrate 10, The thickness of the first insulating layer 40 can be reduced.

5 to 10 are views for explaining a method of manufacturing a silicon via structure according to a first embodiment of the present invention.

5 to 10, a method of manufacturing a silicon via via-hole structure according to a first embodiment of the present invention includes a substrate forming step, a conductive layer forming step, a filling insulating layer forming step, a via hole forming step, And an electrode separating step.

Referring to FIG. 5, in the substrate formation step, a process of forming a cavity 14 surrounding the center pole 12 and the side wall of the center pole 12 is performed by etching one side of the substrate 10 . For example, the substrate 10 may be configured to have a silicon material and the center pawl 12 and the cavity 14 may be formed on the substrate 10 in the shape of the center pawl 12 and the cavity 14 After the mask pattern having the corresponding shape is formed, the substrate 10 is etched. An inner conductor 22 to be described later is formed in the center pole 12 and a filling insulating layer 30 for electrically insulating the inner conductor 22 and the outer conductor 24 is formed in the cavity 14 It is filled. The diameter of the center pole 12 is a parameter that can determine the core diameter of the through via and the cavity 14 is a parameter that can determine the outer diameter of the coaxial via.

6, a conductive layer 20 is formed on the center pole 12, the cavity 14, and a part of the substrate 10 extending from the top of the side wall of the cavity 14, Are formed. For this, a conductive material such as a metal is coated on the substrate 10 in a state where a mask pattern for forming the conductive layer 20 is formed on the substrate 10. As the material of the conductive layer 20, a metal generally used for a semiconductor process such as copper, gold, aluminum, or nickel can be used. The thickness of the conductive layer 20 may vary depending on the application frequency depending on the skin depth. And can usually be formed to the order of a few micrometers. Between the conductive layer 20 and the substrate 10, a diffusion barrier layer, an insulating layer, a metal seed layer, and the like required in a general through silicon via (TSV) process may be additionally formed.

The conductive layer 20 is separated into an internal conductor 22 functioning as a signal line and an external conductor 24 functioning as a ground via an electrode separation step to be described later. The conductive layer 20 formed on the sidewalls and the upper surface of the center pole 12 through the conductive layer forming step finally becomes the internal conductor 22 and the sidewall of the cavity 14, The conductive layer 20 formed on a portion of the substrate 10 extending above the sidewalls of the outer conductor 24 becomes the outer conductor 24.

When the internal conductor 22 is formed by this method, the following effects can be obtained.

In order to realize a silicon via structure with a coaxial through-hole, the center pole 12, which is a silicon structure having a high aspect ratio, is used as a part of the core metal, thereby solving the difficulty of the high-stiffness plating process and shortening the plating time . That is, conventionally, in order to realize the silicon via structure of the coaxial penetration, since the entire core must be formed of metal, the plating time for forming the core metal becomes long, and cracks are generated due to the difference of the thermal expansion coefficient in the high temperature process I could. However, in the present embodiment, in order to form the internal conductor 22, the entire core is not filled with the metal, and the conductive pillar 12 is formed on the substrate 10, Since the layer 20 is coated on the surface of the center pawl 12, the plating time is shortened and the risk of occurrence of cracks due to the difference in thermal expansion coefficient is reduced. That is, the amount of metal to be plated is small, and the plating time is shortened, and the risk of cracking due to the difference in thermal expansion coefficient between the silicon substrate 10 and the plated metal can be reduced.

The inner conductor 22 and the outer conductor 24 are formed by coating the same conductive layer 20 on the silicon substrate 10 on which the center pole 12 and the cavity 14 are formed, 20 are separated from each other. Thus, the inner conductor 22 and the outer conductor 24 are made of the same material and have substantially the same thickness. The outer conductor 24 is formed not only on the sidewall of the cavity 14 but also on a portion of the substrate 10 extending from the top of the sidewall of the cavity 14 to the outside.

The outer conductor 24 is formed not only on the sidewall of the cavity 14 but also on a portion of the substrate 10 that extends outwardly from the top of the sidewall of the cavity 14, And also on the upper surface of the substrate 12, the convenience of the contact process for electrical connection with the outside is improved.

7, in the filling insulating layer forming step, the conductive layer 20 is formed so as to completely cover the region including the cavity 14, that is, the cavity 14 and the conductive layer 20 A process of forming the filling insulating layer 30 on the entire surface of the substrate 10 is performed.

More specifically, the filler dielectric layer 30 is not only filled to fill the cavities 14 but also on the substrate 10 so as to completely cover the internal conductor 22 and the external conductor 24 . For example, the thickness of the filling insulating layer 30 formed on the substrate 10 may be set to 20 to 40 mu m. When the filling insulating layer 30 is formed on the upper surface of the substrate 10 in the process of filling the filling insulating layer 30 into the cavity 14, The electrical loss of the wiring can be reduced. In order to secure a sufficient thickness, the filling insulating layer 30 can be formed by using a polymer capable of forming a thick insulating layer.

For example, the filling insulating layer forming step may be configured to form the filling insulating layer 30 using an organic lamination process.

The prior art discloses the use of an insulating material such as polyimide for filling holes with an insulating layer.

In general, a spin coating method is used to charge a hole by using a liquid material such as polyimide.

According to the spin coating method, voids are generated in the process of filling a hole having a deep hole, that is, a high aspect ratio with an insulator, and problems such as flatness at the hole, edge, and surface are uneven And the like. In general, the liquid polymer has a problem that its price is very high.

On the other hand, if a low-viscosity polymer is applied to the spin coating, the void problem can be solved. However, as the spin speed of the spin coater is increased during the coating process, the polymer may not be able to fill the hole, When the viscosity of the polymer is high, there is a problem that voids may be formed in the inside of the deep hole, particularly in the bottom surface of the hole.

In addition to the spin coating method, a spray method or the like can be used for filling the insulator, but it is difficult to control and the thickness of the insulator layer to be formed may be uneven.

However, when the filling insulating layer 30 is formed using the organic lamination as in the present embodiment, the following effects are obtained.

The lamination technology proposed in this embodiment is a technique which is not used in a general semiconductor process and is originally used in a PCB lamination process. Until now, few cases have been applied to semiconductor product technology.

This lamination technique is a technique for uniformly forming an insulating layer on a substrate surface by placing an epoxy sheet on a substrate in a vacuum or a standby state, for example, by increasing the temperature and applying pressure. At this time, the sheet is softly solid at room temperature, but weakly melted at a point of time when pressure is applied at the former temperature, and flowability is improved, so that the fine holes formed in the substrate can be effectively filled.

This lamination technology is very simple in process and low in material cost, which enables a low-cost process as a whole. Also, when the lamination process is conducted in a vacuum state, the flowability of the resin is improved in the gap, so that a small hole can be effectively charged so that voids do not occur.

Next, referring to FIG. 8, in the via hole forming step, a process of forming wiring via-holes 42, 44, and 46 in the filling insulating layer 30 is performed.

Next, referring to FIG. 9, in the electrode pad forming step, a process for forming the electrode pads 52, 54, and 56 is performed by filling the wiring via holes with a conductive material for electrical connection to the outside.

10, in the electrode separating step, the other surface of the substrate 10 is polished so that the conductive layer 20 formed on the lower surface of the cavity 14 is completely removed, A process of separating the substrate 20 into an inner conductor 22 formed on the center pole 12 and an outer conductor 24 formed on a part of the upper surface of the substrate 10 and the side wall of the cavity 14 is performed.

11 to 18 are views for explaining a method of manufacturing a silicon via structure according to a second embodiment of the present invention.

Hereinafter, the second embodiment will be described focusing on the planarizing step and the first insulating layer forming step, which are different from the first embodiment, in order to avoid duplication of description.

The substrate forming step, the conductive layer forming step, and the filling insulating layer forming step disclosed in Figs. 11 to 13 are configured in the same manner as in the first embodiment.

Referring to FIG. 14, the second embodiment further includes a planarizing step of planarizing the filling insulating layer 30 so that the surface of the conductive layer 20 is exposed after the filling insulating layer forming step. After the planarization step, the filling insulating layer 32 having a thickness substantially equal to the thickness of the conductive layer 20 remains on the substrate 10. [ That is, the filling insulating layer 32 is not only filled in the cavity 14 but also has a thickness substantially equal to the thickness of the conductive layer 20 and extends from the conductive layer 20 to be formed on the surface of the substrate 10 .

15, the second embodiment further includes a first insulating layer forming step of forming a first insulating layer 40 so as to cover the filling insulating layer 32 and the conductive layer 20 .

According to the second embodiment of the present invention, since the filling insulating layer 32 corresponding to the thickness of the plated metal, that is, the conductive layer 20 is secured on the substrate 10, the first insulating layer 40 Can be reduced.

The via hole forming step, the electrode pad forming step and the electrode separating step shown in FIGS. 16 to 18 are configured in the same manner as in the first embodiment.

As described in detail above, according to the present invention, a coaxial through silicon via structure having excellent electrical characteristics even in the case of Lossy silicon and its manufacturing method are provided.

While the present invention has been described in connection with what is presently considered to be preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. In addition, it is a matter of course that various modifications and variations are possible without departing from the scope of the technical idea of the present invention by anyone having ordinary skill in the art.

10: substrate
12: Center pole
14: Cavity
20: conductive layer
22: inner conductor
24: external conductor
30, 32: Charging insulation layer
40: first insulating layer
42, 44, 46: via holes
52, 54, 56: electrode pads

Claims

In the coaxial through silicon via structure,
A substrate having a cavity surrounding a side wall of a central pole;
An inner conductor formed on a side wall and an upper surface of the center pole;
An outer conductor formed on a sidewall of the cavity and on a portion of the substrate that extends outward from a top of the sidewall of the cavity; And
And a filler insulation layer formed in a region including the cavity to electrically insulate the internal conductor and the external conductor,
Wherein the filler insulation layer has a thickness substantially equal to the thickness of the external conductor and is formed on the surface of the substrate extending from the external conductor.

The method according to claim 1,
Wherein the filling insulating layer is formed on the substrate so as to cover the inner conductor and the outer conductor.

3. The method of claim 2,
Wherein the filling insulating layer is formed with wiring via holes for filling a conductive material for wiring for electrically connecting the internal conductor and the external conductor to the outside.

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The method according to claim 1,
Further comprising a first insulating layer formed to cover the charge insulating layer, the internal conductor, and the external conductor.

6. The method of claim 5,
Wherein the first insulating layer is provided with wiring via holes for filling a conductive material for wiring for electrically connecting the internal conductor and the external conductor to the outside.

A method of manufacturing a silicon via structure,
A substrate forming step of etching a surface of the substrate to form a center pole and a cavity surrounding the side wall of the center pole;
A conductive layer forming step of forming a conductive layer on the center pole, the cavity, and a part of the substrate extending above the sidewalls of the cavity;
A filling insulating layer forming step of forming a filling insulating layer in an area including the cavity; And
Separating the conductive layer into an outer conductor formed on the side wall of the cavity and an inner conductor formed on the center pole by polishing the other surface of the substrate so that the conductive layer formed on the lower surface of the cavity is removed, Including,
Wherein the filling insulating layer is formed by using an organic lamination process in the filling insulating layer forming step.

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8. The method of claim 7,
Wherein the organic lamination process is performed in a vacuum atmosphere.

8. The method of claim 7,
Wherein the filling insulating layer is formed on the substrate so as to cover the conductive layer in the filling insulating layer forming step.

11. The method of claim 10,
After the filling insulating layer forming step,
A via hole forming step of forming wiring via holes in the filling insulating layer; And
And forming an electrode pad by filling the wiring via holes with a conductive material for wiring for electrical connection to the outside, thereby forming an electrode pad.

11. The method of claim 10,
After the filling insulating layer forming step,
Further comprising a planarizing step of planarizing the filling insulating layer so that the conductive layer is exposed.

13. The method of claim 12,
Wherein after the planarization step, a filler dielectric layer having a thickness substantially equal to the thickness of the conductive layer remains on the substrate.

14. The method of claim 13,
Further comprising a first insulating layer forming step of forming a first insulating layer to cover the charge insulating layer and the conductive layer.

15. The method of claim 14,
After the step of forming the first insulating layer,
A via hole forming step of forming wiring via holes in the first insulating layer; And
And forming an electrode pad by filling the wiring via holes with a conductive material for wiring for electrical connection to the outside, thereby forming an electrode pad.