KR101528340B1 - 부동 소수점 유닛에서 오버시프트의 빠른 검출을 위한 메카니즘 - Google Patents

부동 소수점 유닛에서 오버시프트의 빠른 검출을 위한 메카니즘 Download PDF

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KR101528340B1
KR101528340B1 KR1020117023161A KR20117023161A KR101528340B1 KR 101528340 B1 KR101528340 B1 KR 101528340B1 KR 1020117023161 A KR1020117023161 A KR 1020117023161A KR 20117023161 A KR20117023161 A KR 20117023161A KR 101528340 B1 KR101528340 B1 KR 101528340B1
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mantissa
overshift
floating point
unit
shift
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KR20120003878A (ko
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데이비드 에스. 올리버
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/485—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G06F5/012—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising in floating-point computations

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  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)
KR1020117023161A 2009-03-16 2010-03-11 부동 소수점 유닛에서 오버시프트의 빠른 검출을 위한 메카니즘 Active KR101528340B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/404,426 US8402075B2 (en) 2009-03-16 2009-03-16 Mechanism for fast detection of overshift in a floating point unit of a processing device
US12/404,426 2009-03-16
PCT/US2010/026908 WO2010107650A1 (en) 2009-03-16 2010-03-11 Mechanism for fast detection of overshift in a floating point unit

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KR20120003878A KR20120003878A (ko) 2012-01-11
KR101528340B1 true KR101528340B1 (ko) 2015-06-11

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US (1) US8402075B2 (enExample)
EP (1) EP2409219B1 (enExample)
JP (1) JP5719341B2 (enExample)
KR (1) KR101528340B1 (enExample)
CN (1) CN102349049B (enExample)
WO (1) WO2010107650A1 (enExample)

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US9354875B2 (en) * 2012-12-27 2016-05-31 Intel Corporation Enhanced loop streaming detector to drive logic optimization
US20150193203A1 (en) * 2014-01-07 2015-07-09 Nvidia Corporation Efficiency in a fused floating-point multiply-add unit
US9720646B2 (en) * 2015-11-12 2017-08-01 Arm Limited Redundant representation of numeric value using overlap bits
US9928031B2 (en) * 2015-11-12 2018-03-27 Arm Limited Overlap propagation operation
US10402168B2 (en) * 2016-10-01 2019-09-03 Intel Corporation Low energy consumption mantissa multiplication for floating point multiply-add operations
US11200186B2 (en) 2018-06-30 2021-12-14 Intel Corporation Apparatuses, methods, and systems for operations in a configurable spatial accelerator
US11907713B2 (en) 2019-12-28 2024-02-20 Intel Corporation Apparatuses, methods, and systems for fused operations using sign modification in a processing element of a configurable spatial accelerator
US12086080B2 (en) 2020-09-26 2024-09-10 Intel Corporation Apparatuses, methods, and systems for a configurable accelerator having dataflow execution circuits
KR102706124B1 (ko) * 2021-12-14 2024-09-12 서울대학교산학협력단 부동 소수점 연산 방법 및 장치

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KR970016935A (ko) * 1995-09-29 1997-04-28 김광호 부동소숫점 덧셈기에서 스티키비트 검출방법
KR20020037278A (ko) * 2000-11-13 2002-05-18 가네꼬 히사시 축소된 회로 규모로 고정 소수점 데이터를 생성하는 회로및 방법

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KR970016935A (ko) * 1995-09-29 1997-04-28 김광호 부동소숫점 덧셈기에서 스티키비트 검출방법
KR20020037278A (ko) * 2000-11-13 2002-05-18 가네꼬 히사시 축소된 회로 규모로 고정 소수점 데이터를 생성하는 회로및 방법

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Publication number Publication date
EP2409219A1 (en) 2012-01-25
CN102349049B (zh) 2014-07-23
CN102349049A (zh) 2012-02-08
WO2010107650A1 (en) 2010-09-23
JP2012521047A (ja) 2012-09-10
KR20120003878A (ko) 2012-01-11
US20100235416A1 (en) 2010-09-16
EP2409219B1 (en) 2017-04-19
JP5719341B2 (ja) 2015-05-20
US8402075B2 (en) 2013-03-19

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