CN102349049B - 快速检测浮点单元中的移位的机制 - Google Patents

快速检测浮点单元中的移位的机制 Download PDF

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Publication number
CN102349049B
CN102349049B CN201080011918.6A CN201080011918A CN102349049B CN 102349049 B CN102349049 B CN 102349049B CN 201080011918 A CN201080011918 A CN 201080011918A CN 102349049 B CN102349049 B CN 102349049B
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mantissa
floating point
overshift
bits
shift
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Chinese (zh)
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CN102349049A (zh
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大卫·S·奥利弗
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Onasta Intellectual Property Co ltd
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/485—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G06F5/012—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising in floating-point computations

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)
CN201080011918.6A 2009-03-16 2010-03-11 快速检测浮点单元中的移位的机制 Active CN102349049B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/404,426 US8402075B2 (en) 2009-03-16 2009-03-16 Mechanism for fast detection of overshift in a floating point unit of a processing device
US12/404,426 2009-03-16
PCT/US2010/026908 WO2010107650A1 (en) 2009-03-16 2010-03-11 Mechanism for fast detection of overshift in a floating point unit

Publications (2)

Publication Number Publication Date
CN102349049A CN102349049A (zh) 2012-02-08
CN102349049B true CN102349049B (zh) 2014-07-23

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CN201080011918.6A Active CN102349049B (zh) 2009-03-16 2010-03-11 快速检测浮点单元中的移位的机制

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US (1) US8402075B2 (enExample)
EP (1) EP2409219B1 (enExample)
JP (1) JP5719341B2 (enExample)
KR (1) KR101528340B1 (enExample)
CN (1) CN102349049B (enExample)
WO (1) WO2010107650A1 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8694572B2 (en) * 2010-07-06 2014-04-08 Silminds, Llc, Egypt Decimal floating-point fused multiply-add unit
US9354875B2 (en) * 2012-12-27 2016-05-31 Intel Corporation Enhanced loop streaming detector to drive logic optimization
US20150193203A1 (en) * 2014-01-07 2015-07-09 Nvidia Corporation Efficiency in a fused floating-point multiply-add unit
US9720646B2 (en) * 2015-11-12 2017-08-01 Arm Limited Redundant representation of numeric value using overlap bits
US9928031B2 (en) * 2015-11-12 2018-03-27 Arm Limited Overlap propagation operation
US10402168B2 (en) * 2016-10-01 2019-09-03 Intel Corporation Low energy consumption mantissa multiplication for floating point multiply-add operations
US11200186B2 (en) 2018-06-30 2021-12-14 Intel Corporation Apparatuses, methods, and systems for operations in a configurable spatial accelerator
US11907713B2 (en) 2019-12-28 2024-02-20 Intel Corporation Apparatuses, methods, and systems for fused operations using sign modification in a processing element of a configurable spatial accelerator
US12086080B2 (en) 2020-09-26 2024-09-10 Intel Corporation Apparatuses, methods, and systems for a configurable accelerator having dataflow execution circuits
KR102706124B1 (ko) * 2021-12-14 2024-09-12 서울대학교산학협력단 부동 소수점 연산 방법 및 장치

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5796644A (en) * 1996-11-18 1998-08-18 Samsung Electronics Company, Ltd. Floating-point multiply-and-accumulate unit with classes for alignment and normalization
CN1472636A (zh) * 2002-07-29 2004-02-04 矽统科技股份有限公司 浮点数的对数运算方法和装置
CN1619484A (zh) * 2003-11-20 2005-05-25 国际商业机器公司 浮点单元及计算指数的方法
CN101042638A (zh) * 2006-03-23 2007-09-26 富士通株式会社 浮点数求和的处理方法及计算机系统
US20080244241A1 (en) * 2007-03-30 2008-10-02 Transitive Limited Handling floating point operations

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0139733B1 (ko) * 1994-04-29 1998-07-01 구자홍 부동 소수점 덧셈/뺄셈 연산기의 반올림 방법 및 장치
US5502401A (en) * 1995-04-26 1996-03-26 Texas Instruments Incorporated Controllable width or gate
KR970016935A (ko) * 1995-09-29 1997-04-28 김광호 부동소숫점 덧셈기에서 스티키비트 검출방법
US5757686A (en) * 1995-11-30 1998-05-26 Hewlett-Packard Company Method of decoupling the high order portion of the addend from the multiply result in an FMAC
JPH09204295A (ja) * 1996-01-29 1997-08-05 Kofu Nippon Denki Kk スティッキービット検出回路
US5771183A (en) * 1996-06-28 1998-06-23 Intel Corporation Apparatus and method for computation of sticky bit in a multi-stage shifter used for floating point arithmetic
US6381624B1 (en) * 1999-04-29 2002-04-30 Hewlett-Packard Company Faster multiply/accumulator
DE10050589B4 (de) * 2000-02-18 2006-04-06 Hewlett-Packard Development Co., L.P., Houston Vorrichtung und Verfahren zur Verwendung beim Durchführen einer Gleitkomma-Multiplizier-Akkumulier-Operation
JP4086459B2 (ja) * 2000-11-13 2008-05-14 Ｎｅｃエレクトロニクス株式会社 固定小数点データ生成方法及び固定小数点データ生成回路
US6754688B2 (en) * 2001-02-14 2004-06-22 Intel Corporation Method and apparatus to calculate the difference of two numbers
US7080111B2 (en) * 2001-06-04 2006-07-18 Intel Corporation Floating point multiply accumulator
US7003539B1 (en) * 2001-08-08 2006-02-21 Pasternak Solutions Llc Efficiently determining a floor for a floating-point number
US6947962B2 (en) * 2002-01-24 2005-09-20 Intel Corporation Overflow prediction algorithm and logic for high speed arithmetic units
US8069200B2 (en) * 2005-04-28 2011-11-29 Qsigma, Inc. Apparatus and method for implementing floating point additive and shift operations
JP4571903B2 (ja) * 2005-12-02 2010-10-27 富士通株式会社 演算処理装置，情報処理装置，及び演算処理方法
US8214417B2 (en) * 2008-08-14 2012-07-03 Oracle America, Inc. Subnormal number handling in floating point adder without detection of subnormal numbers before exponent subtraction

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5796644A (en) * 1996-11-18 1998-08-18 Samsung Electronics Company, Ltd. Floating-point multiply-and-accumulate unit with classes for alignment and normalization
CN1472636A (zh) * 2002-07-29 2004-02-04 矽统科技股份有限公司 浮点数的对数运算方法和装置
CN1619484A (zh) * 2003-11-20 2005-05-25 国际商业机器公司 浮点单元及计算指数的方法
CN101042638A (zh) * 2006-03-23 2007-09-26 富士通株式会社 浮点数求和的处理方法及计算机系统
US20080244241A1 (en) * 2007-03-30 2008-10-02 Transitive Limited Handling floating point operations

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Delay-Optimized Implementation of IEEE Floating-Point Addition;Peter-Michael Seidel等;《IEEE TRANSACTIONS ON COMPUTERS》;20040229;第53卷(第2期);第97-113页 *
P6 Binary Floating-Point Unit;Son Dao Trong等;《2007.ARITH "07. 18th IEEE Symposium on Computer Arithmetic》;20070627;第77-86页 *

Also Published As

Publication number Publication date
EP2409219A1 (en) 2012-01-25
CN102349049A (zh) 2012-02-08
WO2010107650A1 (en) 2010-09-23
JP2012521047A (ja) 2012-09-10
KR20120003878A (ko) 2012-01-11
KR101528340B1 (ko) 2015-06-11
US20100235416A1 (en) 2010-09-16
EP2409219B1 (en) 2017-04-19
JP5719341B2 (ja) 2015-05-20
US8402075B2 (en) 2013-03-19

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