JP5719341B2 - 浮動小数点ユニットにおけるオーバーシフトの高速検出のためのメカニズム - Google Patents

浮動小数点ユニットにおけるオーバーシフトの高速検出のためのメカニズム Download PDF

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JP5719341B2
JP5719341B2 JP2012500839A JP2012500839A JP5719341B2 JP 5719341 B2 JP5719341 B2 JP 5719341B2 JP 2012500839 A JP2012500839 A JP 2012500839A JP 2012500839 A JP2012500839 A JP 2012500839A JP 5719341 B2 JP5719341 B2 JP 5719341B2
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mantissa
overshift
floating point
bits
threshold value
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JP2012521047A5 (enExample
JP2012521047A (ja
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エス． オリヴァー ディビッド
エス． オリヴァー ディビッド
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/485—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G06F5/012—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising in floating-point computations

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)
JP2012500839A 2009-03-16 2010-03-11 浮動小数点ユニットにおけるオーバーシフトの高速検出のためのメカニズム Active JP5719341B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/404,426 2009-03-16
US12/404,426 US8402075B2 (en) 2009-03-16 2009-03-16 Mechanism for fast detection of overshift in a floating point unit of a processing device
PCT/US2010/026908 WO2010107650A1 (en) 2009-03-16 2010-03-11 Mechanism for fast detection of overshift in a floating point unit

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JP2012521047A JP2012521047A (ja) 2012-09-10
JP2012521047A5 JP2012521047A5 (enExample) 2013-05-02
JP5719341B2 true JP5719341B2 (ja) 2015-05-20

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JP2012500839A Active JP5719341B2 (ja) 2009-03-16 2010-03-11 浮動小数点ユニットにおけるオーバーシフトの高速検出のためのメカニズム

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US (1) US8402075B2 (enExample)
EP (1) EP2409219B1 (enExample)
JP (1) JP5719341B2 (enExample)
KR (1) KR101528340B1 (enExample)
CN (1) CN102349049B (enExample)
WO (1) WO2010107650A1 (enExample)

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US20150193203A1 (en) * 2014-01-07 2015-07-09 Nvidia Corporation Efficiency in a fused floating-point multiply-add unit
US9928031B2 (en) * 2015-11-12 2018-03-27 Arm Limited Overlap propagation operation
US9720646B2 (en) * 2015-11-12 2017-08-01 Arm Limited Redundant representation of numeric value using overlap bits
US10402168B2 (en) * 2016-10-01 2019-09-03 Intel Corporation Low energy consumption mantissa multiplication for floating point multiply-add operations
US11200186B2 (en) 2018-06-30 2021-12-14 Intel Corporation Apparatuses, methods, and systems for operations in a configurable spatial accelerator
US11907713B2 (en) 2019-12-28 2024-02-20 Intel Corporation Apparatuses, methods, and systems for fused operations using sign modification in a processing element of a configurable spatial accelerator
US12086080B2 (en) 2020-09-26 2024-09-10 Intel Corporation Apparatuses, methods, and systems for a configurable accelerator having dataflow execution circuits
KR102706124B1 (ko) * 2021-12-14 2024-09-12 서울대학교산학협력단 부동 소수점 연산 방법 및 장치

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JP4086459B2 (ja) * 2000-11-13 2008-05-14 Ｎｅｃエレクトロニクス株式会社 固定小数点データ生成方法及び固定小数点データ生成回路
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Also Published As

Publication number Publication date
WO2010107650A1 (en) 2010-09-23
CN102349049A (zh) 2012-02-08
US20100235416A1 (en) 2010-09-16
EP2409219B1 (en) 2017-04-19
KR20120003878A (ko) 2012-01-11
JP2012521047A (ja) 2012-09-10
CN102349049B (zh) 2014-07-23
KR101528340B1 (ko) 2015-06-11
EP2409219A1 (en) 2012-01-25
US8402075B2 (en) 2013-03-19

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