KR101526892B1 - Apparatus and method for shifting voltage level - Google Patents

Abstract

A voltage level converting apparatus and method are provided. Wherein the voltage level conversion device comprises: an inverter connected between a first node to which an input signal is input and a second node to which an inverted signal of the input signal is output; an inverter connected between the first node and the voltage line, A second voltage conversion unit connected between the second node and the voltage line and turned on when a low level signal is input to the first node, a first voltage conversion unit turned on when a high level signal is input, And a current limiting unit coupled to the first and second voltage conversion units and configured to limit an amount of current flowing to the first or second voltage conversion unit, wherein the first voltage conversion unit and the second voltage conversion unit include a current mirror (current mirror) circuit.

Description

[0001] Apparatus and method for shifting voltage level [0002]

The present invention relates to an apparatus and method for voltage level conversion.

In general, a level shifter acts as an interface between circuits that use different supply voltages, shifting a lower voltage to a higher voltage level. For example, a word line driver of a semiconductor memory device uses a voltage VPP higher than a power supply voltage VDD supplied from the outside. However, the voltage for driving the word line driver swings at a level between the power supply voltage VDD and the ground voltage VSS. On the other hand, the word line driver swings at a level between the pumping voltage VPP and the ground voltage VSS. Therefore, when two circuits are directly connected between the two circuits, that is, without the level conversion between the word line driver and the word line driver, a leakage current can flow in the word line driver using the pumping voltage VPP as the power supply voltage. For this reason, the level shifter is used to connect the two circuits.

Korean Patent Publication No. 2012-0092920 discloses a level-down shifter.

A problem to be solved by the present invention is to use a current mirror structure in a voltage level shifter so that the output voltage level of the level shifter is prevented from falling below the voltage level reduced by the gate-source voltage of the transistor at the power supply voltage level, And to provide a voltage level conversion device capable of reducing the power consumption by fixing the amount of current flowing through the transistor in accordance with the application of the bias voltage.

Another problem to be solved by the present invention is to limit the output voltage level of the level shifter not to fall below the voltage level reduced by the gate-source voltage of the transistor at the power supply voltage level, to reduce the power consumption by fixing the amount of current flowing in the transistor Voltage level conversion method.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other matters not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided an apparatus for converting a voltage level into an inverter, the inverter including an inverter connected between a first node receiving an input signal and a second node outputting an inverted signal of the input signal, A first voltage conversion unit coupled between the voltage line and turned on when a high level signal is input to the first node, a first voltage conversion unit connected between the second node and the voltage line, And a current limiting unit connected to the first and second voltage conversion units and configured to limit an amount of current flowing to the first or second voltage conversion unit, The voltage converting unit and the second voltage converting unit are current mirror circuits.

Here, the voltage level converter may be configured to provide the boosted high level signal to the output terminal when the first voltage converter is turned on and the second voltage converter is turned off, and the first voltage converter turns off Level signal to the output terminal when the second voltage converter is turned on.

The boosted high level signal may have the same voltage level as the voltage level applied to the voltage line.

The second voltage converter may include a MOS transistor, and a source node of the MOS transistor may be connected to the output terminal.

The boosted low level signal may have a voltage level reduced by a gate-source voltage of the MOS transistor from a voltage level applied to the voltage line.

The output stage may include a plurality of output nodes.

The amount of current flowing to the first or second voltage converting unit may be fixed by a bias voltage applied to the current limiting unit.

According to another aspect of the present invention, there is provided a voltage level converting method comprising: applying a high level signal to turn on a first voltage converting unit, turn off a second voltage converting unit, And applying a low level signal to turn off the first voltage converting unit, turn on the second voltage converting unit, provide a boosted low level signal to the output terminal, and apply a bias voltage to the first or second And fixing the amount of current flowing in the voltage converting portion.

Here, in the voltage level conversion method, the boosted high level signal may have the same voltage level as the voltage level applied to the voltage line.

The boosted low level signal may have a voltage level reduced by a gate-source voltage of a MOS transistor included in the second voltage conversion unit from a voltage level applied to the voltage line.

The output stage may include a plurality of output nodes.

Other specific details of the invention are included in the detailed description and drawings.

According to the voltage level converting apparatus and method of the present invention, the current mirror structure can be used to limit the output voltage level of the voltage level converting apparatus from falling below the voltage level reduced by the gate-source voltage of the transistor at the power supply voltage level And the amount of current flowing through the transistor is fixed according to the application of the bias voltage, so that the power consumption can be reduced. In addition, the leakage current can be limited.

1 is a circuit diagram of a voltage level converting apparatus according to an embodiment of the present invention.
2 and 3 are circuit diagrams for explaining an operation method of the voltage level conversion apparatus according to an embodiment of the present invention.
4 is a graph for explaining the range of change of the output voltage level of the voltage level converting apparatus according to an embodiment of the present invention.
5 is a circuit diagram to which a voltage level converting apparatus according to an embodiment of the present invention is applied.
6 is a circuit diagram of a voltage level converting apparatus according to another embodiment of the present invention.
7 is a flowchart sequentially illustrating a voltage level conversion method according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

One element is referred to as being "connected to " or " coupled to" another element, either directly connected or coupled to another element, . On the other hand, when one element is referred to as being "directly connected to" or "directly coupled to " another element, it means that no other element is interposed in between. Like reference numerals refer to like elements throughout the specification. "And / or" include each and every combination of one or more of the mentioned items.

It is to be understood that when an element or layer is referred to as being "on" or " on "of another element or layer, All included. On the other hand, a device being referred to as "directly on" or "directly above " indicates that no other device or layer is interposed in between.

The terms spatially relative, "below", "beneath", "lower", "above", "upper" May be used to readily describe a device or a relationship of components to other devices or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when inverting an element shown in the figures, an element described as "below" or "beneath" of another element may be placed "above" another element. Thus, the exemplary term "below" can include both downward and upward directions. The elements can also be oriented in different directions, so that spatially relative terms can be interpreted according to orientation.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

The voltage level converting apparatus and method described below can prevent the voltage level of the output of the voltage level converting apparatus from being lowered below the voltage level lowered by the gate-source voltage of the transistor at the power source voltage level, Lt; / RTI > Particularly, among the breakdown voltages of semiconductor devices, the gate-source voltage (Vgs) is lowest, which may affect the breakdown of the circuit element. According to the present invention, the output of the voltage level converter can utilize a plurality of (e.g., two) output voltage levels using a plurality of (e.g., two) output nodes. Accordingly, a voltage level suitable for an application of a subsequent block of the voltage level conversion apparatus can be used. Further, by using the transistor of the current mirror structure, the amount of current in the subsequent block can be adjusted, and the voltage limit range can be adjusted by the current value of the bias and the size of the transistor. It is possible to reduce the power consumption of the voltage level converter by fixing the value of the current flowing through the voltage level converter by the bias current.

1 is a circuit diagram of a voltage level converting apparatus according to an embodiment of the present invention. 2 and 3 are circuit diagrams for explaining an operation method of the voltage level conversion apparatus according to an embodiment of the present invention. 4 is a graph for explaining the range of change of the output voltage level of the voltage level converting apparatus according to an embodiment of the present invention.

Referring to FIG. 1, a voltage level converting apparatus according to an embodiment of the present invention includes an inverter 100, a first voltage converting unit 200, a second voltage converting unit 300, a current limiting unit 400, And an output stage 500.

The inverter 100 is connected between a first node N1 to which the input signal Vin is input and a second node N2 to which the inverted signal of the input signal Vin is output. That is, when the input signal Vin input to the first node N1 by the inverter 100 is a high level signal, the output signal output to the second node N2 is inverted into a low level signal, When the input signal Vin input to the first node N1 is a low level signal, the output signal output to the second node N2 is inverted to a high level signal. 1, the power supply voltage LVDD applied to the inverter 100 is represented by LVDD in order to distinguish it from the power supply voltage HVDD applied to the voltage line VL.

The first voltage converter 200 is connected between the first node N1 and the voltage line VL and is turned on when a high level signal is input to the first node N1. For example, the first voltage conversion unit 200 may be configured using a PMOS transistor and an NMOS transistor. 1, the first voltage conversion unit 200 includes a first MOS transistor M1, a third MOS transistor M3, a fourth MOS transistor M4, and a fifth MOS transistor M5 Respectively. The gate node of the first MOS transistor M1 may be connected to the first node N1. That is, the input signal Vin can operate with the gate voltage for driving the first MOS transistor M1. The drain node of the first MOS transistor M1 is connected to the source node and the gate node of the third MOS transistor M3, the source node and gate node of the fourth MOS transistor M4, the source node of the fifth MOS transistor M5, Can be connected. The drain node of the third MOS transistor M3 and the drain node of the fifth MOS transistor M5 may be connected to the voltage line VL. For example, the first MOS transistor M1 may be a PMOS transistor, and the third MOS transistor M3, the fourth MOS transistor M4, and the fifth MOS transistor M5 may be NMOS transistors.

The second voltage converter 300 is connected between the second node N2 and the voltage line VL and is turned on when a low level signal is input to the first node N1. The second voltage converter 300 is a circuit having a current mirror structure with the first voltage converter 200. For example, the second voltage converter 300 may be configured using a PMOS transistor and an NMOS transistor. 1, the second voltage conversion unit 300 includes a second MOS transistor M2, a sixth MOS transistor M6, a seventh MOS transistor M7, and an eighth MOS transistor M8 Respectively. The gate node of the second MOS transistor M2 may be connected to the second node N2. That is, the inverted signal for the input signal Vin can operate as the gate voltage for driving the second MOS transistor M2. When the input signal Vin is a high level signal, the low level signal can operate as a gate voltage for driving the second MOS transistor M2. When the input signal Vin is a low level signal, And can operate as a gate voltage for driving the second MOS transistor M2. The source node of the sixth MOS transistor M6 may be connected to the first output node Vout1. The drain node of the second MOS transistor M2 may be connected to the source node of the seventh MOS transistor M7, the source node of the eighth MOS transistor M8, and the second output node Vout2. For example, the second MOS transistor M2 may be a PMOS transistor, and the sixth MOS transistor M6, the seventh MOS transistor M7, and the eighth MOS transistor M8 may be NMOS transistors.

The current limiting unit 400 is connected to the first voltage converting unit 200 and the second voltage converting unit 300 to limit the amount of current flowing to the first voltage converting unit 200 or the second voltage converting unit 300 do. The current limiting unit 400 may be composed of a ninth MOS transistor M9 and may be, for example, a PMOS transistor. The bias voltage Vb may be applied to the current limiting section 400 and driven by the gate voltage of the ninth MOS transistor M9. A fixed current can flow through the first voltage converting unit 200 or the second voltage converting unit 300 connected to the current limiting unit 400 as a constant bias voltage Vb is applied to the current limiting unit 400, And the power consumption of the voltage level converter can be reduced. The bias current can be adjusted according to the size of the ninth MOS transistor M9, and thus the amount of current in the subsequent block can be adjusted.

The output stage 500 may include a plurality of output nodes (e.g., Vout1, Vout2). The first output node Vout1 may be connected to the gate node of the fifth MOS transistor M5 and the source node and the gate node of the sixth MOS transistor M6. The second output node Vout2 may be connected to the source node and the gate node of the seventh MOS transistor M7 and the source node of the eighth MOS transistor M8.

Hereinafter, an operation method of the voltage level converting apparatus according to an embodiment of the present invention will be described with reference to FIG. 2 and FIG.

Referring to FIG. 2, a case where a high level voltage VH is input to the first node N1 is shown. At this time, the high level voltage VH is applied to the gate node of the first MOS transistor M1 connected to the first node N1, and the first MOS transistor M1 is turned on. Accordingly, the first voltage converter 200 is turned on and the current path Ia is formed in the first voltage converter 200. On the other hand, a low level voltage VL is output to the second node N2 and a gate node of the second MOS transistor M2 is connected to the second node N2, so that the second MOS transistor M2 is turned And the second voltage converter 300 is turned off. When the first voltage converter 200 is turned on and the second voltage converter 300 is turned off, the first output node Vout1 and the second output node Vout2 are connected to the voltage line VL The voltage HVDD corresponding to the power supply voltage HVDD is outputted.

Referring to FIG. 3, a case where a low level voltage VL is input to the first node N1 is shown. At this time, the low level voltage VL is applied to the gate node of the first MOS transistor M1 connected to the first node N1, and the first MOS transistor M1 is turned off. Accordingly, the first voltage converter 200 is turned off. On the other hand, a high level voltage VH is outputted to the second node N2 and a gate node of the second MOS transistor M2 is connected to the second node N2, so that the second MOS transistor M2 is turned on The second voltage conversion unit 300 is turned on and a current path Ib is formed in the second voltage conversion unit 300. When the first voltage converter 200 is turned off and the second voltage converter 300 is turned on, the voltage of HVDD-Vgs is output to the first output node Vout1 and the voltage of HVDD-Vgs is output to the second output node Vout2. The voltage of HVDD-2Vgs is output.

Referring to FIG. 4, when a conventional voltage level converting apparatus is used, when the low level signal (for example, 0) is applied to the input signal Vin, the boosted low level signal is also zero. However, according to the present invention, when a low level signal (for example, 0) is applied to the input signal Vin, the boosted low level signal is supplied to the breakdown voltage range of the device such as HVDD-Vgs or HVDD- Lt; RTI ID = 0.0 > VB. ≪ / RTI > Therefore, the variation width of the boosted output signal when the high level signal is input to the first node N1 and when the low level signal is input can be reduced, thereby preventing the device from being destroyed.

5 is a circuit diagram to which a voltage level converting apparatus according to an embodiment of the present invention is applied.

Referring to FIG. 5, a MOS transistor MP1 is connected to the output terminal 600. In this case, when a low level signal is input to the first node N1, the voltage applied to the gate node of the MOS transistor MP1 is HVDD-2Vgs, and when a high level signal is input to the first node N1 , The voltage applied to the gate node of the MOS transistor MP1 is HVDD, and the swing width of the voltage level is limited. Therefore, it is possible to prevent the MOS transistor MP1 from being destroyed by applying a voltage equal to or lower than the breakdown voltage to the MOS transistor MP1.

6 is a circuit diagram of a voltage level converting apparatus according to another embodiment of the present invention. For the sake of convenience of description, description of portions substantially the same as those of the voltage level converting apparatus according to the embodiment of the present invention will be omitted.

Referring to FIG. 6, the voltage level converting apparatus according to another embodiment of the present invention does not include the current limiting unit 400. That is, the current limiting unit 400 is not necessarily required to limit the swing width of the boosted voltage signal output to the output nodes (for example, Vout1, Vout2) of the output stage 500. [

Hereinafter, a voltage level conversion method according to an embodiment of the present invention will be described with reference to FIG.

7 is a flowchart sequentially illustrating a voltage level conversion method according to an embodiment of the present invention.

Referring to FIG. 7, first, a high-level signal is applied to turn on the first voltage converter, turn off the second voltage converter, and provide a stepped-up high-level signal at the output terminal (S100). The inverter can be used to turn on the first voltage converter while turning off the second voltage converter. The first voltage converting unit and the second voltage converting unit may be circuits having a current mirror structure. The boosted high level signal may have the same voltage level as the voltage level of the power supply voltage applied to the voltage line. The output stage may include a plurality of output nodes.

Conversely, a low level signal is applied to turn off the first voltage conversion unit, turn on the second voltage conversion unit, and provide the boosted low level signal to the output stage (S200). The boosted low level signal may have a voltage level reduced by the gate-source voltage of the MOS transistor included in the second voltage conversion section from the voltage level of the power supply voltage applied to the voltage line.

In addition, the amount of current flowing to the first or second voltage converting unit is fixed using a MOS transistor to which a bias voltage is applied (S300).

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

100: inverter 200: first voltage converter
300: second voltage converter 400: current limiter
500: Output stage

Claims (11)

An inverter connected between a first node for receiving an input signal and a second node for outputting an inverted signal of the input signal;
A first voltage conversion unit connected between the first node and a voltage line and turned on when a high level signal is input to the first node;
A second voltage conversion unit connected between the second node and the voltage line and turned on when a low level signal is input to the first node;
A current limiter connected to the first and second voltage converters, for limiting an amount of current flowing to the first or second voltage converter;
A first output terminal for outputting a boosted high level signal when the first voltage converter is turned on and the second voltage converter is turned off; And
And a second output terminal for outputting a boosted low level signal when the first voltage conversion section is turned off and the second voltage conversion section is turned on,
Wherein the first output terminal is connected to a gate node of a first MOS transistor included in the first voltage converting unit and a gate node of a second MOS transistor included in the second voltage converting unit,
And the second output terminal is connected to a gate node of a third MOS transistor which is different from the second MOS transistor included in the second voltage converter, and the first voltage converter and the second voltage converter are connected to a current mirror ) Circuit. delete The method according to claim 1,
Wherein the boosted high level signal has a voltage level equal to a voltage level applied to the voltage line. The method according to claim 1,
And a source node of the third MOS transistor is connected to the second output terminal. 5. The method of claim 4,
Wherein the boosted low level signal has a voltage level reduced by a gate-source voltage of the third MOS transistor from a voltage level applied to the voltage line. delete The method according to claim 1,
Wherein the amount of current flowing in the first or second voltage converting unit is fixed by a bias voltage applied to the current limiting unit. delete delete delete delete

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