KR101490109B1 - Semiconductor device and methods of manufacturing and operating the same - Google Patents

Abstract

A semiconductor device and its manufacturing and operating method are disclosed. The disclosed semiconductor devices may include different nanostructures. For example, the semiconductor device may include a first component formed of a nanowire and a second component formed of a nanoparticle. Here, the nanowire may be an ambipolar carbon nanotube. The first component may be a channel layer and the second component may be a charge trap layer, in which case the semiconductor device may be a transistor or a memory device.

Description

Semiconductor device and method of manufacturing and operating same

This disclosure relates to semiconductor devices and methods of making and operating them.

Silicon (Si) based semiconductor devices have been highly integrated and high performance at a high speed. However, due to limitations in the properties of Si materials and limitations of the manufacturing process, it is expected that from the next several years, it will be difficult to further increase the integration and performance of Si-based semiconductor devices.

Therefore, research on a next-generation device that can overcome the limitations of Si-based semiconductor devices is underway. For example, attempts have been made to fabricate nanodevices such as carbon nanotubes (CNTs) to produce fine devices with excellent performance. Carbon nanotubes are very small in diameter from several to several tens nanometers (nm), and can be advantageous in miniaturization of devices, and have excellent properties such as high mobility, high electric conductivity, high thermal conductivity, and strong mechanical strength. Accordingly, carbon nanotubes are attracting attention as materials capable of overcoming the limitations of existing devices.

However, there are problems to be solved in applying carbon nanotubes to semiconductor devices, so it is not easy to implement the devices using them. Typically, there is a problem that it is difficult to reproducibly synthesize carbon nanotubes, and it is difficult to handle the synthesized carbon nanotubes. For example, in order to realize a device using carbon nanotubes, a technique for accurately arranging carbon nanotubes in a desired region of a substrate for device fabrication is required. In addition, since it is not easy to apply carbon nanotubes and other nanostructures together in one device, there are restrictions on implementation of various devices having high performance.

An aspect of the present invention provides a semiconductor device comprising an aminopolar nanostructure.

Another aspect of the present invention provides a method of manufacturing the semiconductor device.

Another aspect of the present invention provides a method of operating the semiconductor device.

One embodiment of the present invention provides a nanostructure comprising: a channel layer comprising a first nanostructure; A source and a drain respectively connected to both ends of the channel layer; A first tunnel insulating layer provided on the channel layer; A first charge trap layer provided on the first tunnel insulating layer and including a second nanostructure different from the first nanostructure; A first blocking insulating layer disposed on the first charge trap layer; And a first control gate provided on the first blocking insulating layer.

The first nanostructure may have polarity.

The first nanostructure may be a nanowire.

The nanowire may be a carbon nanotube.

The second nanostructure may be a nanoparticle.

The channel layer may be provided on the hydrophilic layer.

A hydrophobic layer may be provided on the hydrophilic layer around the channel layer, and the source and the drain may be provided on the hydrophobic layer.

The first tunnel insulating layer may include sequentially stacked first and second insulating layers, and the second insulating layer may be a hydrophilic molecular layer or a hydrophobic molecular layer.

A second control gate spaced apart from the channel layer may be further provided, and the channel layer may be provided between the first and second control gates.

A second charge trap layer between the channel layer and the second control gate; A second tunnel insulating layer between the channel layer and the second charge trap layer; And a second blocking insulating layer between the second charge trap layer and the second control gate.

The second charge trap layer may comprise a nanostructure, such as nanoparticles.

The semiconductor device of this embodiment may be a transistor or a nonvolatile memory element.

Another embodiment of the present invention provides a method of fabricating a semiconductor device, comprising: forming a channel layer comprising a first nanostructure on a substrate; Forming a source and a drain in contact with both ends of the channel layer, respectively; Forming a first tunnel insulating layer on the channel layer; Forming a first charge trap layer on the first tunnel insulating layer, the first charge trap layer including a second nanostructure different from the first nanostructure; Forming a first blocking insulating layer on the first charge trap layer; And forming a first control gate on the first blocking insulating layer.

The first nanostructure may have polarity.

Wherein forming the channel layer comprises: forming a non-aqueous layer on the substrate; Forming a hydrophobic layer on the non-aqueous layer, the hydrophobic layer having an opening exposing the first region of the non-aqueous layer; And adsorbing a plurality of the first nanostructures to the first region exposed by the openings.

The first nanostructure may be nanowires.

The nanowire may be a carbon nanotube.

The forming of the first tunnel insulating layer may include: forming an insulating layer covering the channel layer, the source and the drain; And forming an adsorption layer for adsorbing the second nanostructure on the insulating layer above the channel layer between the source and the drain.

The manufacturing method of this embodiment is characterized in that, between the step of forming the insulating layer and the step of forming the adsorption layer, a semi-adsorptive layer which does not adsorb the second nanostructure on a region other than the adsorption layer- The method comprising the steps of:

The second nanostructure may be a nanostructure, such as nanoparticles.

The manufacturing method of the present embodiment may further include forming a second control gate spaced apart from the channel layer. At this time, the channel layer may be provided between the first and second control gates.

The manufacturing method of the present embodiment includes: forming a second charge trap layer between the second control gate and the channel layer; Forming a second blocking insulating layer between the second control gate and the second charge trap layer; And forming a second tunnel insulating layer between the second charge trap layer and the channel layer.

In another embodiment of the present invention, there is provided a semiconductor device comprising: a channel layer including a first nanostructure; a source and a drain respectively contacting both ends of the channel layer; a first tunnel insulating layer provided on the channel layer; A first charge trap layer provided on the first charge trap layer and including a second nanostructure different from the first nanostructure, a first blocking insulating layer provided on the first charge trap layer, and a second blocking insulating layer provided on the first blocking insulating layer, A method of operating a semiconductor device comprising one control gate, the method comprising: trapping charge in the first charge trap layer.

The charge may be electron or hole.

The semiconductor device may further include a second charge trap layer and a second control gate, and the method of operation of the present embodiment may further include trapping electrons or holes in the second charge trap layer .

According to an embodiment of the present invention, a predetermined nanostructure, for example, nanowires or nanoparticles, can be easily arranged in a desired region of a substrate. In addition, at least two different nanostructures can be applied together in one device. Therefore, by using the embodiment of the present invention, it is possible to easily manufacture various devices using the nanostructure.

In particular, since the semiconductor device according to the embodiment of the present invention can be a reversible type-switching device, it can have various advantages.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. The widths and thicknesses of the layers or regions illustrated in the accompanying drawings are exaggeratedly shown for clarity of the description. Like reference numerals designate like elements throughout the specification.

1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, a channel layer C1 is provided on a substrate SUB1. The channel layer C1 may include a plurality of first nanostructures n1. The first nanostructure n1 may be a nanowire laid on the substrate SUB1. The first nanostructure n1 may be composed of an ambipolar material having both an n-type semiconductor characteristic and a p-type semiconductor characteristic. The bipolar material may be, for example, a carbon nanotube (CNT). Accordingly, the channel layer C1 may include a plurality of nanowires made of carbon nanotubes. The non-aqueous layer L1 may be provided between the channel layer C1 and the substrate SUB1. The non-aqueous layer L1 may be formed on the front surface of the substrate SUB1 and the channel layer C1 may be formed on a predetermined region of the non-aqueous layer L1. The non-aqueous layer (L1) may be a hydrophilic layer. For example, the non-aqueous layer L1 may be an insulating material layer such as a SiO ₂ layer, a glass, an Al ₂ O ₃ layer, a ZrO ₂ layer, and a HfO ₂ layer. The hydrophobic layer L2 may be further provided on the non-aqueous layer L1 around the channel layer C1. The hydrophobic layer L2 may be a layer containing hydrophobic molecules such as octadecyl-trichlorosilane (OTS), octadecyl-trimethoxysilane (OTMS), octadecyl-triethoxysilane (OTE) Since the first nanostructure n1 is not adsorbed in the hydrophobic layer L2 but can be adsorbed only in the non-aqueous layer L1 (for example, the hydrophilic layer), the channel layer C1 is not formed in the hydrophobic layer L2 May be formed on the non-aqueous non-aqueous layer (L1) in a self-assembling manner. A hydrophilic molecular layer (not shown) may be further provided between the non-aqueous layer L1 and the channel layer C1. In this case, the first nanostructure n1 may be self-assembled to the hydrophilic molecular layer (not shown). The hydrophilic molecular layer (not shown) may include hydrophilic molecules such as, for example, APTES (aminopropyl-triexothysilane) and MPTMS [(3-mercaptopropyl) trimethoxysilane].

And a source electrode S1 and a drain electrode D1 which are in contact with both ends of the channel layer C1, respectively. The source electrode S1 and the drain electrode D1 may have a structure extending from both ends of the channel layer C1 to the hydrophobic layer L2. The source electrode S1 and the drain electrode D1 may be formed of a metal such as gold (Au) or palladium (Pd), or a semiconductor doped with a metal oxide or a conductive impurity at a high concentration.

A first charge trap layer CT1 may be provided above the channel layer C1. The first charge trap layer CT1 may be referred to as a floating gate in some cases. The first charge trap layer CT1 may include a plurality of second nanostructures n2. The second nanostructure n2 may have a different structure from the first nanostructure n1. For example, the second nanostructure n2 may be a nanoparticle. The nanoparticle may include at least one of a metal, a metal oxide, and a semiconductor. For example, the second nanostructure n2 may be a nanoparticle formed of a metal such as gold (Au).

A first tunnel insulating layer TL1 may be provided between the channel layer C1 and the first charge trap layer CT1. The first tunnel insulating layer TL1 may include a first layer L10 and a second layer L20 sequentially disposed on the channel layer C1. The first layer L10 may have a structure extending over the source electrode S1 and the drain electrode D1 and the second layer L20 may have a structure extending from the channel layer between the source electrode S1 and the drain electrode D1. (C1). The third layer L30 may be further provided on the first layer L10 where the second layer L20 is not provided. The first layer (L10) is, for example, as _{SiO 2, Al 2 O 3,} ZrO 2, HfO 2 , and the other may be formed of other insulating materials, e.g., about 10nm or less, the smaller the thickness of about 1~5nm . The second layer L20 is an adsorption layer for easy adsorption of the second nanostructure n2, and may be a hydrophilic molecular layer or a hydrophobic molecular layer. The material of the second layer L20 may be determined depending on the kind of the second nanostructure n2. The third layer L30 may be a semi-adsorptive layer to which the second nanostructure n2 is not adsorbed. The third layer L30 may have properties opposite to those of the second layer L20. That is, when the second layer L20 is a hydrophilic molecular layer, the third layer L30 may be a hydrophobic molecular layer. Conversely, when the second layer L20 is a hydrophobic molecular layer, the third layer L30 may be a hydrophilic molecular layer. Since the second nanostructure n2 can be adsorbed only on the second layer L20 without being adsorbed on the third layer L30, the first charge trap layer CT1 is formed on the second layer L20, And may be formed in a self-assembly manner. When the second nanostructure n2 is a gold nanoparticle, the second layer L20 may be a layer formed of a hydrophilic molecule such as APTES, and the third layer L30 may be a hydrophobic molecule such as OTS, OTMS, OTE, May be a layer formed of a molecule. Depending on the material of the second nanoparticle n2 and the first layer L10, the second layer L20 may not be required. In some cases, only the second layer L20 may be provided, and the third layer L30 may not be provided. In other cases, the first layer L10 is formed only on the channel layer C1 between the source electrode S1 and the drain electrode D1, and the second layer L20 and the third layer L30 are provided .

A first blocking insulating layer BL1 may be provided on the first charge trap layer CT1 and the third layer L30. A first blocking insulating layer (BL1) can be a layer formed of another insulating material, _{e.g., SiO 2, Al 2 O 3} , ZrO 2, HfO 2 and others. The first blocking insulating layer BL1 may be formed of the same material as or different from the non-aqueous layer L1 and the first layer L10. The thickness of the first blocking insulating layer BL1 may be thicker than that of the first layer L10. For example, the thickness of the first blocking insulating layer BL1 may be several tens of nanometers or more.

A first control gate G1 may be provided on the first blocking insulating layer BL1 above the first charge trap layer CT1. The first control gate G1 may be formed of a metal such as gold (Au) or palladium (Pd), or a semiconductor doped with a metal oxide or a conductive impurity at a high concentration.

Although FIG. 1 shows a semiconductor device having a single gate structure, according to another embodiment of the present invention, a semiconductor device having a double gate structure is also possible. Examples thereof are shown in Figs. 2 and 3. Fig.

2 shows a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 2, a second control gate G2 may be provided in an upper portion of the substrate SUB1 '. The substrate SUB1 'may be a semiconductor substrate, and the second control gate G2 may be a region doped with a conductive impurity at a high concentration. The second control gate G2 may extend under the source electrode S1 and the drain electrode D1 under the channel layer C1 but may be provided only under the channel layer C1 . The non-aqueous layer L1 between the second control gate G2 and the channel layer C1 may be a gate insulating layer. In Fig. 2, the non-aqueous layer L1 and its superstructure may be the same as those of Fig.

According to another embodiment of the present invention, a second charge trap layer may further be provided between the second control gate G2 and the channel layer C1 of FIG. An example thereof is shown in Fig.

Referring to FIG. 3, a second charge trap layer CT2 is further provided between the second control gate G2 and the channel layer C1. Similar to the first charge trap layer CT1, the second charge trap layer CT2 may also be referred to as a floating gate. The second charge trap layer CT2 may comprise a nanostructure. For example, the second charge trap layer CT2 may be the same or the same layer as the first charge trap layer CT1. That is, the second charge trap layer CT2 may include the same or the same nano structure n2 'as the second nano structure n2. However, the present invention is not limited thereto. The second charge trap layer CT2 may be composed of a different structure and material from the first charge trap layer CT1. Several layers L10 ', L20', L30 'may be provided between the second charge trap layer CT2 and the second control gate G2. More specifically, a fourth layer L10 'may be provided on the second control gate G2 and a fifth layer L10' may be provided between the second charge trap layer CT2 and the fourth layer L10 ' L20 ') may be further provided. The fifth layer L20 'may be an adsorption layer for adsorption of the nanostructure n2'. A sixth layer L30 'may be further provided on the fourth layer L10' around the fifth layer L20 '. The sixth layer L30 'may be a semi-adsorptive layer in which the nanostructure n2' is not adsorbed. The fourth and fifth layers L10 'and L20' provided between the second charge trap layer CT2 and the second control gate G2 may constitute a second blocking insulating layer. The materials of the fourth to sixth layers L10 ', L20' and L30 'may correspond to the materials of the first to third layers L10, L20 and L30, respectively. Accordingly, the second charge trap layer CT2 may be a layer formed in a self-assembled manner on the fifth layer L20 '. It is also optional to provide the fifth layer L20 'and the sixth layer L30' as it is optional to provide the second layer L20 and the third layer L30. The non-aqueous electrolyte layer L1 'covering the second charge trap layer CT2 may be provided on the sixth layer L30'. The non-aqueous layer L1 'may correspond to the non-aqueous layer L1 of FIG. The non-aqueous layer L1 'between the second charge trap layer CT2 and the channel layer C1 may be a second tunnel insulating layer. The structure formed on the non-aqueous layer L1 'may be similar to the structure formed on the non-aqueous layer L1 in FIG.

Although the second control gate G2 is provided in the upper portion of the substrate SUB1 'in FIGS. 2 and 3, according to another embodiment of the present invention, the second control gate may be formed on a separate layer (a metal layer or a doped Semiconductor layer). In addition, a structure in which the first charge trap layer CT1 and the first control gate G1 are not provided in FIG. 3 is also possible. That is, a bottom single gate structure is also possible.

4A to 4G are perspective views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 4A, the non-aqueous layer L1 may be formed on the substrate SUB1. The non-aqueous layer (L1) may be a hydrophilic layer. For example, the non-aqueous layer L1 may be an insulating material layer such as a SiO ₂ layer, a glass, an Al ₂ O ₃ layer, a ZrO ₂ layer, and a HfO ₂ layer. The hydrophobic layer L2 having an opening for exposing a part of the non-aqueous layer L1 (hereinafter referred to as the first region) may be formed on the non-aqueous layer L1. The hydrophobic layer L2 may be a layer containing hydrophobic molecules such as OTS, OTMS, OTE, and the like. A method of forming the hydrophobic layer L2 will be described in more detail. First, a resin layer (not shown) is formed on the first region of the non-aqueous layer L1, If the hydrophobic molecule is put in a solution in which the hydrophobic molecule is dissolved, the hydrophobic molecule is adsorbed only to the portion where the resin film is not present, so that the hydrophobic layer (L2) can be formed. The resin film may be a photoresist or a photolithography method, for example. In addition, the solvent of the solution in which the hydrophobic molecules are dissolved may not dissolve the resin film like hexane. After forming the hydrophobic layer (L2), the resin film can be selectively removed using a solvent such as acetone. The method of forming the hydrophobic layer L2 can be variously changed. For example, microcontact printing or photolithography may be used to form the hydrophobic layer L2.

Although not shown here, it is also possible to further provide the exposed region of the non-aqueous layer (L1), that is, the hydrophilic molecule layer in the first region. To this end, the substrate SUB1 may be put into a solution in which hydrophilic molecules are dispersed. In this case, the hydrophilic molecule may be adsorbed only in the non-aqueous layer (L1) and not in the hydrophobic layer (L2). The hydrophilic molecule may be, for example, APTES and MPTMS, and the solvent of the solution in which the hydrophilic molecule is dispersed may be ethanol, hexane and the like. Since the non-aqueous layer (L1) itself may be a hydrophilic layer, it is optional to form the hydrophilic molecular layer.

Referring to FIG. 4B, a solution (hereinafter referred to as a first nanostructure solution) NS1 in which a plurality of first nanostructures n1 are dispersed is provided. The first nanostructure n1 may be a nanowire, for example, carbon or nanotubes. The solvent of the first nanostructure solution (NS1) may not affect the first nanostructure (n1) like dichlorobenzene. The structure of FIG. 4A is put into the first nanostructure solution NS1. Since the first nanostructure n1 is not adsorbed in the hydrophobic layer L2 and can be absorbed only in the non-aqueous layer L1 (for example, the hydrophilic layer), the non-aqueous layer L1 in which the hydrophobic layer L2 is not formed, And can be self-assembled on the substrate. The result is shown in Figure 4c.

In FIG. 4C, the plurality of first nanostructures n1 may constitute one channel layer C1. As described above, by using the self-assembly method, the nanostructure channel layer C1 having a desired shape can be easily formed at a desired position of the substrate SUB1.

Referring to FIG. 4D, a source electrode S1 and a drain electrode D1, which are in contact with both ends of the channel layer C1, are formed. The source electrode S1 and the drain electrode D1 may be formed in a structure extending from both ends of the channel layer C1 to the hydrophobic layer L2. The source electrode S1 and the drain electrode D1 may be formed of a metal such as gold (Au) or palladium (Pd), a metal oxide, or a semiconductor doped with a conductive impurity at a high concentration. In this case, PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition) such as a sputtering method and a thermal evaporation method can be used for the film deposition. In order to pattern the deposited film, photolithography or electron beam E-beam lithography and the like can be used.

Referring to FIG. 4E, a first insulating layer L10 may be formed on the hydrophobic layer L2 to cover the channel layer C1, the source electrode S1, and the drain electrode D1. A first insulating layer (L10) is, for _{example, SiO 2, Al 2 O 3} , ZrO 2, HfO 2 , and the other may be formed of other insulating material, be formed with about 10nm or less, for example, a thickness of about 1~5nm . Methods such as CVD, plasma enhanced-CVD, and atomic layer deposition (ALD) may be used to form the first insulating layer L10. The step of forming the first insulating layer L10 may not affect the characteristics of the first nanostructure n1.

Referring to FIG. 4F, the second insulating layer L20 may be formed on the first insulating layer L10 above the channel layer C1 between the source electrode S1 and the drain electrode D1, The third insulating layer L30 may be formed on the first insulating layer L10 where the insulating layer L20 is not formed. The third insulating layer L30 may be formed first, and then the second insulating layer L20 may be formed, or vice versa. The second insulating layer L20 may be an adsorption layer having a property of adsorbing the second nanostructure n2 (see FIG. 4G), and the third insulating layer L30 may be a layer that does not adsorb the second nanostructure n2 Semi-adsorptive layer. Any one of the second and third insulating layers L20 and L30 may be hydrophilic and the other may be hydrophobic. For example, the second insulating layer L20 may be a hydrophilic layer, and the third insulating layer L30 may be a hydrophobic layer. In this case, the third insulating layer L30 may be formed by a method similar to the method of forming the hydrophobic layer L2 of FIG. 4A, and then the second insulating layer L20 may be formed. At this time, in order to form the second insulating layer L20, the substrate SUB1 on which the third insulating layer L30 is formed may be put into a solution in which the hydrophilic molecules are dispersed. In this case, since the hydrophilic molecules are adsorbed only to the first insulating layer L10 and not to the third insulating layer L30, the structure as shown in FIG. 4F can be obtained. The hydrophilic molecule may be, for example, APTES and MPTMS, and the solvent of the solution in which the hydrophilic molecule is dispersed may be ethanol, hexane and the like. In some cases, only the second insulating layer L20 may be formed without forming the third insulating layer L30, or both the second and third insulating layers L20 and L30 may not be formed.

Referring to FIG. 4G, a solution (hereinafter referred to as a second nanostructure solution) NS2 in which a plurality of second nanostructures n2 are dispersed is provided. The second nanostructure n2 may be, for example, a nanoparticle. The solvent of the second nanostructure solution (NS2) may be deionized water or the like. Put the structure of Figure 4f into the second nanostructure solution (NS2). The second nanostructure n2 is adsorbed only on the second insulating layer L20 and not on the third insulating layer L30 so that it can be self-assembled on the second insulating layer L20. The result is shown in Figure 4h.

The plurality of second nano structures n2 self-assembled in Fig. 4H may constitute the first charge trap layer CT1. As described above, by using the self-assembly method, the first charge trap layer CT1 of the nanostructure can be easily formed in a desired shape at a desired position of the substrate SUB1.

Referring to FIG. 4I, a first blocking insulating layer BL1 is formed on the third insulating layer L30 to cover the first charge trap layer CT1. A first blocking insulating layer (BL1), for example, may be formed of other insulating materials _{SiO 2, Al 2 O 3,} ZrO 2, HfO 2 and others. The first blocking insulating layer BL1 may be formed of the same material as or different from the non-aqueous layer L1 and the first insulating layer L10. The first blocking insulating layer BL1 may be thicker than the first insulating layer L10, for example, a thickness of about several tens of nm or more. The first blocking insulating layer BL1 may be formed by a method such as CVD, PE-CVD or ALD, and the characteristics of the second nanostructure n2 may not change. A first control gate G1 is formed on the first blocking insulating layer BL1. The first control gate G1 may include a first portion P1 extending over the central portion of the channel layer C1 and a second portion P2 extending from one end of the first portion P1. The second portion P2 may be perpendicular to the first portion P1. The shape of the first control gate G1 can be variously changed. The first control gate G1 may be formed of a metal such as gold (Au) or palladium (Pd), or a semiconductor doped with a metal oxide or a conductive impurity at a high concentration. In this case, PVD or CVD such as sputtering and thermal evaporation may be used for film deposition, and photolithography or electron beam lithography may be used for patterning the deposited film. Sectional view taken along line I-I 'of FIG. 4I may correspond to the structure of FIG.

Although FIGS. 4A to 4I illustrate and describe a method of manufacturing a semiconductor device having a single gate structure as shown in FIG. 1, by modifying the present embodiment, it is possible to manufacture a semiconductor device having a double gate structure as shown in FIGS. can do.

For example, the second control gate G2 of FIG. 2 can be formed by doping the upper portion of the substrate SUB1 with a high concentration of conductive impurities before or after the formation of the non-aqueous layer L1 in the step of FIG. 4A. Instead of forming the second control gate G2 by doping the upper portion of the substrate SUB1, a second control gate may be formed on the substrate SUB1 with a separate layer structure. The second charge trap layer CT2 of FIG. 3 can also be formed between the second control gate G2 and the channel layer C1 in a manner similar to the method of forming the first charge trap layer CT1 .

As described above, according to the embodiment of the present invention, it is possible to easily arrange a predetermined nanostructure, for example, a nanowire (carbon nanotube) or a nanoparticle in a desired region of a substrate. In addition, at least two different nanostructures can be applied together in one device. Therefore, by using the embodiment of the present invention, it is possible to easily manufacture various high-performance devices using one or more nanostructures.

Hereinafter, operation methods, characteristics, and application fields of semiconductor devices according to embodiments of the present invention will be described.

1, after electrons or holes are trapped in the first charge trap layer CT1, a normal operation voltage Vs is applied to the source electrode S1, the drain electrode D1 and the first control gate G1, To operate. Also, while using the element of FIG. 1, the type of charge trapped in the first charge trap layer CT1 can be changed. In order to trap electrons in the first charge trap layer CT1, a positive high voltage, for example, about + 10V, can be applied to the first control gate G1. At this time, electrons can be moved from the channel layer C1 to the first charge trap layer CT1 and trapped by the positive high voltage. On the other hand, in order to trap holes, a negative (-) high voltage, for example, about -10 V, can be applied to the first control gate G1. At this time, holes can be moved from the channel layer C1 to the first charge trap layer CT1 and trapped by the negative high voltage. Depending on what charges (electrons or holes) are trapped in the first charge trap layer CT1 by applying a positive (+) or negative (-) high voltage to the first control gate G1, Can vary. For example, when a high voltage of negative (-) is applied to the first control gate G1 to trap holes in the first charge trap layer CT1, in the normal operating voltage range, the device of FIG. (Hereinafter referred to as " n-type transistor "). Also, when electrons are trapped in the first charge trap layer CT1 by applying a positive high voltage to the first control gate G1, in the normal operating voltage range, the device of FIG. (Hereinafter referred to as a p-type transistor). This will be described in more detail with reference to FIG.

FIG. 5 is a graph showing the gate voltage (Vg) -drain current (Id) characteristic of the device of FIG. Here, the gate voltage Vg means a voltage applied to the first control gate G1, and the drain current Id means a current flowing between the source electrode S1 and the drain electrode D1. The drain current Id was measured while changing the gate voltage Vg and a voltage of about 1 V was applied between the source electrode S1 and the drain electrode D1.

5, when the gate voltage Vg is increased from -10 V to +10 V (hereinafter referred to as a first graph) G1 and the gate voltage Vg is decreased from + 10V to -10V It can be seen that the graph (hereinafter referred to as the second graph) G2 has a distinct difference. That is, the electrical hysteresis is obvious. More specifically, if the gate voltage Vg is increased after the gate voltage Vg of -10V is applied, the characteristic of the first graph G1 is followed until the gate voltage Vg of + 10V is applied . When a gate voltage Vg of -10V is applied, holes are trapped in the first charge trap layer CT1 and the electric field applied to the channel layer C1 by the trapped holes is positive + ). Therefore, the first graph G1 can be biased toward the negative direction as a whole. Once the holes are trapped in the first charge trap layer CT1, the charges trapped in the first charge trap layer CT1 are held in the positive holes until a positive (+) voltage equal to or lower than the threshold voltage, The kind of charge trapped in the first charge trap layer CT1 can be changed to electrons. When the gate voltage Vg is decreased after applying the gate voltage Vg of +10 V corresponding to the high positive voltage higher than the threshold voltage, (G2). Electrons are trapped in the first charge trap layer CT1 when a gate voltage Vg of +10 V is applied and the electric field applied to the channel layer C1 is shifted in the negative direction . Therefore, the second graph G2 can be biased toward the positive direction as a whole rather than the first graph G1.

The characteristics of the gate voltage Vg-drain current Id can be greatly changed depending on what charge is trapped in the first charge trap layer CT1. The first graph G1 and the second graph G2 may exhibit properties opposite to each other within a predetermined voltage range. For example, the first graph G1 increases as the gate voltage Vg increases in a gate voltage (Vg) range (hereinafter referred to as a first range) R1 between about -4 V and about +5 V, The graph G2 decreases. The increase in the drain current Id as the gate voltage Vg increases is a feature of the n-type transistor and the decrease in the drain current Id as the gate voltage Vg increases is due to the characteristics of the p- to be. The normal operating voltage may be in the first range R1. Therefore, the semiconductor device according to the embodiment of the present invention may have an n-type transistor characteristic or a p-type transistor characteristic depending on the type of charge trapped in the first charge trap layer CT1. This can be used as an n-type transistor for a given first purpose when using the device according to an embodiment of the present invention, and as a p-type transistor by converting the type for a given second purpose . Thus, the semiconductor device according to the embodiment of the present invention has various advantages because it can be a reversible type-switching device (transistor or memory device). For example, using an embodiment of the present invention, a reconfigurable circuit can be fabricated.

FIG. 6 is a graph showing the waveform of the gate voltage Vg applied to the element of FIG. 1 and the change of the drain current Id according to the gate voltage Vg.

6, when a first positive voltage V1 of a small intensity is applied after applying a positive high voltage to the first control gate G1, the waveform of the first voltage V1 and the The waveform of the drain current Id generated by V1 is opposite. This shows that when the positive high voltage is applied to the first control gate G1, the device can characterize the p-type transistor. On the other hand, when the second voltage V2 of a small intensity is applied after the negative high voltage is applied to the first control gate G1, the waveform of the second voltage V2 and the waveform of the second voltage V2 The waveform of the generated drain current Id shows a similar tendency. This shows that when the negative (-) high voltage is applied to the first control gate G1, the device can exhibit the characteristics of an n-type transistor.

On the other hand, when the semiconductor device according to the embodiment of the present invention is used as a memory device, depending on whether a charge (electron or hole) is trapped in the first charge trap layer CT1 or whether or not the charge is trapped, The magnitude of the drain current Id may vary. With this principle, a nonvolatile memory device using the first charge trap layer CT1 as a memory layer can be realized.

7 is a waveform diagram of two gate voltages (hereinafter referred to as first and second gate voltages) Vg1 and Vg2 applied to the element of FIG. 2, that is, the double gate element, and the waveforms of the first and second gate voltages Vg1, Vg2) of the drain current Id. The first and second gate voltages Vg1 and Vg2 represent voltages applied to the first and second control gates G1 and G2, respectively.

Referring to FIG. 7, if a first voltage V1 'having a normal operating voltage level is applied to the second control gate G2 after applying the first gate voltage Vg1 of +10 V, The waveform of the drain current Id generated by the first voltage V1 'and the waveform of the first voltage V1' are opposite. This shows that when the first gate voltage Vg1 of + 10V is applied, the device can characterize a p-type transistor. It is also shown that after the electrons are trapped in the first charge trap layer CT1 by the first control gate G1, the device can be normally operated by the second control gate G2. On the other hand, if the second voltage V2 'having the normal operating voltage level is applied to the second control gate G2 after applying the first gate voltage Vg1 of -10V, The waveform of the drain current Id and the waveform of the second voltage V2 'are similar. This shows that applying a first gate voltage (Vgl) of-10V can characterize an n-type transistor. It is also shown that the device can be normally operated by the second control gate G2 after trapping holes in the first charge trap layer CT1 with the first control gate G1. 2, after the electrons or the holes are trapped in the first charge trap layer CT1, the source electrode S1, the drain electrode D1 and the first control gate G1 are supplied with a normal operation voltage Or a normal operation voltage can be applied to the source electrode S1, the drain electrode D1 and the second control gate G2. The element of Fig. 2 can also be used as a transistor or a memory element.

FIGS. 8A and 8B are graphs showing the gate voltage (Vg) -drain current (Id) characteristics of the two devices having the structure of FIG. 3 but somewhat different in manufacturing method. Here, the gate voltage Vg means a voltage applied to the first control gate G1, and the drain current Id means a current flowing between the source electrode S1 and the drain electrode D1. The drain current Id was measured while changing the gate voltage Vg and a voltage of about 1 V was applied between the source electrode S1 and the drain electrode D1.

In the case of FIG. 8A, a very similar pattern as FIG. 5 is shown. That is, the first graph G1 'shows the characteristic of the n-type transistor as the gate voltage Vg increases in the gate voltage Vg range of about -4 V to about +5 V, and the second graph G2' ) Characterize a p-type transistor.

On the other hand, in the case of FIG. 8B, it can be seen that the drain current Id when a positive high voltage is applied is about 0.2 ㎂, which is considerably lower than 0.4 에서 in Fig. 8A. It can also be seen that the first and second graphs G1 "and G2" show the characteristics of the p-type transistor from about -10V to about 0V.

That is, in the case of the device corresponding to FIG. 8A, the characteristics of the n-type transistor and the characteristics of the p-type transistor are in balance, while the characteristics of the p-type transistor This is strong. 8A and 8B, the characteristics of the hysteresis phenomenon, that is, characteristics of the gate voltage (Vg) -drain current (Id) may be different depending on the manufacturing method even if the structures are similar. This may be the same for the elements of Figs. 1 and 2 as well.

In operation of the device of FIG. 3, electrons or holes are trapped in the first charge trap layer CT1, electrons or holes are trapped in the second charge trap layer CT2, and then the source electrode S1, A normal operation voltage can be applied to the electrode D1 and the first control gate G1 or a normal operation voltage can be applied to the source electrode S1, the drain electrode D1 and the second control gate G2. In addition, the element of Fig. 3 can be used as a transistor or a memory element as in the elements of Figs. Since the device of FIG. 3 has two charge trap layers CT1 and CT2, it can have various states than the devices of FIGS. 1 and 2 having one charge trap layer CT1. 3 are different from each other depending on the type of charge trapped in the first charge trap layer CT1 and the type of charge trapped in the second charge trap layer CT2, (0, 0), (1,0), (0,1), and (1,1). The four states may correspond to the states of Figs. 9A to 9D, respectively.

Referring to FIG. 9A, electrons are trapped in both the first charge trap layer CT1 and the second charge trap layer CT2. To this end, a positive high voltage may be applied to the first control gate G1 and the second control gate G2.

Referring to FIG. 9B, holes are trapped in the first charge trap layer CT1, and electrons are trapped in the second charge trap layer CT2. To this end, a negative high voltage may be applied to the first control gate G1 and a positive high voltage may be applied to the second control gate G2.

Referring to FIG. 9C, electrons are trapped in the first charge trap layer CT1, and holes are trapped in the second charge trap layer CT2. To this end, a positive high voltage may be applied to the first control gate G1 and a negative high voltage may be applied to the second control gate G2. The state of FIG. 9C can be considered to be similar to the state of FIG. 9B in that holes are trapped on one side of the channel layer C1 and electrons are trapped on the other side. However, if the configuration above the channel layer C1 and the configuration below the channel layer C1 are not perfectly symmetric about the channel layer C1, the states of FIGS. 9B and 9C may exhibit different resistances. More specifically, the thickness and material difference between the first tunnel insulating layer TL1 and the second tunnel insulating layer L10 '+ L20' and the material and size of the first and second charge trap layers CT1 and CT2 The state of Fig. 9B and Fig. 9C may exhibit different resistances.

Referring to FIG. 9D, holes are trapped in both the first charge trap layer CT1 and the second charge trap layer CT2. To this end, a negative high voltage may be applied to the first control gate G1 and the second control gate G2.

Therefore, according to the embodiment of the present invention, it is possible to implement a multi-bit memory device in which one unit memory cell has four different resistance states.

10 is a graph showing the relationship between two voltages (i.e., first and second gate voltages) Vg1 and Vg2 applied to the first and second control gates G1 and G2 of the device of FIG. 3 and the drain current Id Show changes. This result is the result for a device having the structure of FIG. 3 but having characteristics corresponding to FIG. 8A. The drain voltage used to obtain such a result, that is, the voltage between the source electrode S1 and the drain electrode D1 was about 1V.

10, the (0, 0) state is a state after applying +10 V to the first and second control gates G1 and G2, the (1,0) state is a state after the first control gate G1, A voltage of -10 V is applied to the second control gate G2 and a voltage of +10 V is applied to the second control gate G2. In the (0,1) state, a voltage of +10 V is applied to the first control gate G1 The state after the voltage of -10 V is applied to the second control gate G2 and the state of (1, 1) after applying -10 V to the first and second control gates G1 and G2 Lt; / RTI > The drain currents Id in the (0, 0), (1,0), (0,1), and (1,1) states are different from each other.

Although a number of matters have been specifically described in the above description, they should be interpreted as examples of preferred embodiments rather than limiting the scope of the invention. For example, those of ordinary skill in the art will appreciate that the structures of FIGS. 1-3 and the fabrication methods of FIGS. 4A-4I may vary. As a specific example, it is to be understood that the channel layer C1 in FIGS. 1 to 3 may be formed of a bipolar material other than carbon nanotubes, for example, graphene. It will also be appreciated that other devices not specifically disclosed herein may be fabricated using the idea of the present invention. Therefore, the scope of the present invention is not to be determined by the described embodiments but should be determined by the technical idea described in the claims.

1 to 3 are sectional views of semiconductor devices according to embodiments of the present invention.

4A to 4I are perspective views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a graph showing the gate voltage (Vg) -drain current (Id) characteristic of the device of FIG.

6 is a graph showing the waveform of the gate voltage Vg applied to the element of FIG. 1 and the change of the drain current Id in accordance with the gate voltage Vg.

FIG. 7 is a graph showing waveforms of two gate voltages Vg1 and Vg2 applied to the device of FIG. 2 and a change of a drain current Id according to the two gate voltages Vg1 and Vg2.

FIGS. 8A and 8B are graphs showing gate voltage (Vg) -drain current (Id) characteristics of the two devices having the structure of FIG. 3 but somewhat different from each other.

9A-9D are cross-sectional views showing four different states of the device of FIG.

10 is a graph showing waveforms of two gate voltages Vg1 and Vg2 applied to the device of FIG. 3 and a graph of changes in drain current Id according to the two gate voltages Vg1 and Vg2.

Description of the Related Art [0002]

BL1: blocking insulating layer C1: channel layer

CT1, CT2: charge trap layer D1: drain electrode

G1, G2: control gate L1, L1 ': non-aqueous layer

L2: hydrophobic layer L10 to L30: first to third layers

L10 'to L30': fourth to sixth layers n1: first nanostructure

n2: second nanostructure NS1: first nanostructure solution

NS2: second nanostructure solution R1: first region

S1: source electrode SUB1, SUB1 ': substrate

TL1: Tunnel insulation layer

Claims (24)

A channel layer comprising a first nanostructure; A source and a drain respectively connected to both ends of the channel layer; A first tunnel insulating layer provided on the channel layer; A first charge trap layer provided on the first tunnel insulating layer and including a second nanostructure different from the first nanostructure; A first blocking insulating layer disposed on the first charge trap layer; And And a first control gate provided on the first blocking insulating layer, The channel layer is provided on the hydrophilic layer, Wherein a hydrophobic layer is provided on the hydrophilic layer around the channel layer, And the source and the drain are provided on the hydrophobic layer. The method according to claim 1, Wherein the first nanostructure has a polarity. 3. The method according to claim 1 or 2, Wherein the first nanostructure is a nanowire. The method according to claim 1, And the second nanostructure is a nanoparticle. delete delete The method according to claim 1, Wherein the first tunnel insulating layer includes first and second insulating layers sequentially stacked, Wherein the second insulating layer is a hydrophilic molecular layer or a hydrophobic molecular layer. The method according to claim 1, Further comprising a second control gate spaced apart from the channel layer, And the channel layer is provided between the first and second control gates. 9. The method of claim 8, A second charge trap layer between the channel layer and the second control gate; A second tunnel insulating layer between the channel layer and the second charge trap layer; And And a second blocking insulating layer between the second charge trap layer and the second control gate. 10. The method of claim 9, Wherein the second charge trap layer comprises nanoparticles. The method according to claim 1, Wherein the semiconductor element is a transistor or a nonvolatile memory element. Forming a channel layer comprising a first nanostructure on a substrate; Forming a source and a drain in contact with both ends of the channel layer, respectively; Forming a first tunnel insulating layer on the channel layer; Forming a first charge trap layer on the first tunnel insulating layer, the first charge trap layer including a second nanostructure different from the first nanostructure; Forming a first blocking insulating layer on the first charge trap layer; And Forming a first control gate on the first blocking insulating layer, Wherein forming the channel layer comprises: Forming a non-aqueous layer on the substrate; Forming a hydrophobic layer on the non-aqueous layer, the hydrophobic layer having an opening exposing the first region of the non-aqueous layer; And And adsorbing a plurality of the first nanostructures to the first region exposed by the opening. 13. The method of claim 12, Wherein the first nanostructure has a polarity. delete The method according to claim 12 or 13, Wherein the first nanostructure is a nanowire. 13. The method of claim 12, wherein forming the first tunnel insulating layer comprises: Forming an insulating layer covering the channel layer, the source and the drain; And And forming an adsorption layer for adsorbing the second nanostructure on the insulating layer above the channel layer between the source and the drain. 17. The method of claim 16, Between the step of forming the insulating layer and the step of forming the adsorption layer, Forming a semi-adsorptive layer on the insulating layer, the semi-adsorptive layer not adsorbing the second nanostructure on a region other than the adsorption layer formation region. The method according to any one of claims 12,16 and 17, And the second nanostructure is a nanoparticle. 13. The method of claim 12, Further comprising forming a second control gate spaced apart from the channel layer, And the channel layer is provided between the first and second control gates. 20. The method of claim 19, Forming a second charge trap layer between the second control gate and the channel layer; Forming a second blocking insulating layer between the second control gate and the second charge trap layer; And And forming a second tunnel insulating layer between the second charge trap layer and the channel layer. The method of operating a semiconductor device according to claim 1, Trapping charges in the first charge trap layer. 22. The method of claim 21, Wherein the charge is electrons or holes. 22. The method of claim 21, Wherein the semiconductor device further comprises a second charge trap layer and a second control gate, Trapping electrons or holes in the second charge trap layer. ≪ RTI ID = 0.0 > 11. < / RTI > A channel layer comprising a first nanostructure; A source and a drain respectively connected to both ends of the channel layer; A first tunnel insulating layer provided on the channel layer; A first charge trap layer provided on the first tunnel insulating layer and including a second nanostructure different from the first nanostructure; A first blocking insulating layer disposed on the first charge trap layer; And And a first control gate provided on the first blocking insulating layer, Wherein the first tunnel insulating layer comprises first and second insulating layers sequentially stacked, and the second insulating layer is one of a hydrophilic molecular layer and a hydrophobic molecular layer.

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