CN107978603A - A kind of thin-film transistor memory and its multilevel storage method - Google Patents
A kind of thin-film transistor memory and its multilevel storage method Download PDFInfo
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- CN107978603A CN107978603A CN201610914897.8A CN201610914897A CN107978603A CN 107978603 A CN107978603 A CN 107978603A CN 201610914897 A CN201610914897 A CN 201610914897A CN 107978603 A CN107978603 A CN 107978603A
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
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- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical group O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 4
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
Abstract
The invention discloses a kind of thin-film transistor memory and its multilevel storage method, the thin-film transistor memory uses double-gate structure, in semiconductive thin film both sides, two independent charge accumulation layers are set, and apply certain grid, drain voltage by programming, electronics or hole is injected separately into upper and lower charge storage layer, 24 value informations are stored in single thin-film transistor memory.The thin-film transistor memory for storing 1 information with common individual devices to threshold voltage distribution after programming and the requirement of charge maintenance capability using the thin-film transistor memory multilevel storage method is identical, and the realization of multilevel storage is not to sacrifice the reliability and stability of device as cost, suitable for current thin-film transistor memory, there is stronger feasibility.
Description
Technical field
The present invention relates to flexible electronic device field, is more precisely related to a kind of thin-film transistor memory and its multivalue
Storage method.
Background technology
As current market constantly increases the demand of flexible electronic information products, to flexible memory performance, size with
And the requirement of cost etc. is also continuously improved.Traditional silicon-based memory is limited to its preparation process, it is difficult to it is compatible with flexible substrate,
In order to solve the problems, such as this, there is the memory of various structures in this area, and in the memory of these different structures, film
Transistorized memory performance is the most prominent, is most widely used.Thin-film transistor memory has to be stored in single transistor
Information, non-destructive read, are easy to carry out the advantages that integrated with circuit, and in low cost radio frequency identification, flexible sensor, soft
Property storage and large area flexible show etc. that field has broad application prospects.
Solve the problems, such as mainly how to improve storage density and how to reduce storage needed for existing flexible memory
Cost, and the maximally efficient method that solves the above problems is exactly to reduce device size and realize multilevel storage.It is limited by preparation work
Skill, the size of existing thin-film transistor memory is generally larger, and how to reduce the size of thin-film transistor memory simultaneously
And it is that flexible circuit develops faced a great problem not influence its other performance, therefore, it is thin to realize that multilevel storage becomes raising
Film transistor storage density, reduce the maximally efficient approach of carrying cost.
Multilevel storage technology is broadly divided into multistage (Multi-Level-Cell) and multidigit (Multi-Bit-Cell) two
Kind.Wherein, multilevel storage technique is by controlling program conditions (program voltage or programming time), injecting floating boom when adjusting programming
Amount of charge, make program window threshold voltage be distributed positioned at different numerical value multilevel storage technology；Multidigit memory technology is then
It is that electric charge is stored in the two or more difference of a unit at the same time physically, the technology stored using more physical bits.But
It is that localization Spreading requirements of the multidigit multilevel storage technology to electric charge are higher, and since the distribution character for storing electric charge is difficult to control
System, can cause the reliability decrease of device, such as fatigue properties and retention performance.Multilevel storage technology had both overcome floating boom storage
The bottleneck of device minification, and cost of the bits per inch according to storage is reduced, therefore multilevel storage technology becomes floating gate type quick flashing
Memory improves a kind of important method of storage density.
Chinese invention patent 200910134374.1 proposes a kind of oxide-nitride-oxygen of layer containing multilevel oxide
Compound storehouse improves charge storage density, the method for improving storage performance；Chinese invention patent 200910077724.5 proposes
One kind improves charge storage density, the method for realizing multilevel storage using double-level-metal nano particle；Chinese invention patent
201110067070.5, which propose two kinds of different storage materials, is alternately arranged the method for preparing High Density Charge accumulation layer, also may be used
To realize multivalue.But above method is suitable for traditional silicon-based devices, since technological temperature height cannot be used in based on flexibility
The memory device of film transistor of substrate.
In addition, traditional multilevel storage technique realizes multilevel storage, it is necessary to according to threshold voltage and injection electric charge capture layer
The quantity of electric charge between relation, accurately controlled by varying program voltage amplitude or time and charge storage layer injected in programming process
Electricity, the programming reliability requirement to device is high.Simultaneously because after using multilevel storage technique, each storage state is corresponding
Threshold voltage interval reduces, and charge maintenance capability is put forward higher requirements.Therefore, point of threshold voltage after accurate control programs
The high reliability of cloth and each storage state and stability are to successfully pass the premise that multi-level techniques realize multilevel storage, and current
Thin-film transistor memory is difficult to reach this requirement.
The content of the invention
It is an object of the invention to provide a kind of thin-film transistor memory, the thin-film transistor memory is used half
Conductor thin film both sides set two independent charge accumulation layers, and apply certain grid, drain voltage by programming, and make electronics
Or hole is injected separately into upper and lower charge storage layer, 24 value informations are stored in single thin-film transistor memory.
It is another object of the present invention to provide a kind of thin-film transistor memory, the thin-film transistor memory
Manufacture method is suitable for flexible substrate, and preparation process is simple.
It is another object of the present invention to provide a kind of thin-film transistor memory multilevel storage method, the film is brilliant
Body pipe memory multilevel storage method applies certain grid, drain voltage by programming, and electronics or hole is injected separately into upper and lower electricity
Lotus accumulation layer, stores 24 value informations in single thin-film transistor memory, and that improves the thin-film transistor memory can
Control property and stability, while improve amount of storage.
In order to achieve the above object, the present invention provides a kind of thin-film transistor memory, including
One flexible substrate；
One gate electrode group, the gate electrode group includes a bottom gate thin film and a top-gated electrode, wherein the bottom gate thin film is set
It is placed in the flexible substrate, and the bottom gate thin film is close to fix with the flexible substrate；
One charge storage layer group, the charge storage layer group include charge storage layer on charge storage layer and one, under
Charge storage layer is arranged in the flexible substrate, and the lower charge storage layer is close to fix with the flexible substrate, described
Lower charge storage layer also is close to fix with the bottom gate thin film；
Semiconductor film, the semiconductive thin film is between the lower charge storage layer and the upper charge storage layer
The semiconductive thin film is arranged on the lower charge storage layer, and the semiconductive thin film is close to the lower charge storage layer
Fixed, the upper charge storage layer is arranged at the semiconductive thin film, and the upper charge storage layer and the semiconductive thin film
It is close to fix, the top-gated electrode is arranged at the upper charge storage layer, and the top-gated electrode and the upper charge storage layer
It is close to fix；And
One electrode group, the electrode group include a source electrode and a drain electrode, and the source electrode and the drain electrode are all provided with
It is placed on the semiconductive thin film, the source electrode and the drain electrode are close to fix with the semiconductive thin film, and described
Upper charge storage layer is close to fix with the source electrode and the drain electrode.
Preferably, the flexible substrate is made of PET or PI or other flexible materials.
Preferably, the bottom gate thin film using ITO or gold or copper into, the top-gated electrode using gold or copper into.
Preferably, the source electrode and the drain electrode using gold or copper into.
Preferably, the semiconductive thin film is pentacene semiconductive thin film or polymer semiconductor thin film.
Preferably, the lower charge storage layer includes controlling insulating layer, a metal membrane and once tunnelling is exhausted
Edge layer, the lower control insulating layer is arranged in the flexible substrate, and the lower control insulating layer and the flexible substrate are tight
Patch is fixed, and the lower control insulating layer also is close to fix with the bottom gate thin film at the same time, and the metal membrane is arranged at described
On lower control insulating layer, and the metal membrane is close to fix with the lower control insulating layer, and the tunneling insulation layer is set
It is placed between the metallic film and the semiconductive thin film, and the tunneling insulation layer and the metallic film and described partly leads
Body thin film is close to fix.
Preferably, it is described it is lower to control insulating layer be aluminum oxide film, the metal membrane is gold thin film, the lower tunnelling
Insulating layer is aluminum oxide film.
Preferably, the upper charge storage layer includes control insulating layer on one, tunnelling is exhausted on metallic film and one on one
Edge layer, the upper tunneling insulation layer are arranged at the semiconductive thin film, and the upper tunneling insulation layer and the semiconductive thin film
It is close to fix, the upper metallic film is arranged on the upper tunneling insulation layer, and the upper metallic film and the upper tunnelling
Insulating layer is close to connect, and the upper control insulating layer is arranged between the upper metallic film and the top-gated electrode, and described
Upper control insulating layer is close to fix with the upper metallic film and the top-gated electrode.
Preferably, the upper tunneling insulation layer is polystyrene film, and the upper metallic film is gold thin film, the control
Insulating layer is made of polymethyl methacrylate or Cytop.
A kind of multilevel storage method of thin-film transistor memory, it is characterised in that including step：
(A) thin-film transistor memory receiving grid, drain voltage；
(B) electronics in thin-film transistor memory or hole are injected separately into upper and lower charge storage layer.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is attached drawing needed in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, without creative efforts, can be with
Other attached drawings are obtained according to these attached drawings.
Fig. 1 is a kind of structure diagram of thin-film transistor memory of the present invention.
Fig. 2 is a kind of flow chart of thin-film transistor memory multilevel storage method of the present invention.
Fig. 3 is that a kind of thin-film transistor memory of the present invention realizes that storage information mutually changes corresponding program conditions
Table.
Fig. 4 is a kind of knot of the one embodiment of thin-film transistor memory based on metal nanoparticle floating boom of the present invention
Structure schematic diagram.
Fig. 5 is a kind of flow chart of thin-film transistor memory preparation method of the present invention.
Embodiment
Deposited as shown in Figure 1 for a kind of structure diagram of thin-film transistor memory of the invention, the thin film transistor (TFT)
Reservoir includes a flexible substrate 10, a gate electrode group 20, a charge storage layer group 30,40 and one electrode group of semiconductor film
50.Wherein described gate electrode group 20 includes a bottom gate thin film 201 and a top-gated electrode 202, and the charge storage layer group 30 includes
Charge storage layer 302 on charge storage layer 301 and one once, the electrode group 50 include a source electrode 501 and a drain electrode
502.The flexible substrate 10 is located at the bottom of the thin-film transistor memory, and the bottom gate thin film 201 is arranged at described
In flexible substrate 10, and the bottom gate thin film 201 is close to fix with the flexible substrate 10.The lower charge storage layer 301
It is arranged in the flexible substrate 10, and the lower charge storage layer 301 is close to fix with the flexible substrate 10, the lower electricity
Lotus accumulation layer 301 also is close to fix with the bottom gate thin film 201 at the same time.The semiconductive thin film 40 is arranged at the lower electric charge and deposits
On reservoir 301, and the semiconductive thin film 40 is close to fix with the lower charge storage layer 301.The source electrode 501 and described
Drain electrode 502 may be contained within the semiconductive thin film 40, and the source electrode 501 and the drain electrode 502 are with described half
Conductor thin film 40 is close to fix.The upper charge storage layer 302 is arranged at the semiconductive thin film 40, and the upper electric charge storage
Layer 302 is close to fix with the semiconductive thin film 40, the upper charge storage layer 302 and meanwhile also with the source electrode 501 and institute
Drain electrode 502 is stated to be close to fix.The top-gated electrode 202 is arranged at the upper charge storage layer 302, and the top-gated electrode
202 are close to fix with the upper charge storage layer 302.
The thin-film transistor memory uses double-gate structure, i.e., described with bottom gate thin film 201 and top-gated electrode 202
Bottom gate thin film 201 is contacted with the flexible substrates, and the top-gated electrode 202 is located at the top of the thin-film transistor memory.Institute
State charge storage layer 302 and the lower charge storage layer 301 is respectively arranged at the both sides up and down of the semiconductive thin film 40.Institute
Source electrode 501 and the drain electrode 502 is stated to be connected with the semiconductive thin film 40.By controlling the bottom gate thin film 201, top
The voltage that gate electrode 202 and the drain electrode 501 are applied, can control electronics or hole note in the thin-film transistor memory
Enter the lower charge storage layer 301 or upper charge storage layer 302, so as to complete the lower charge storage layer 301 and described power on
Storage of the lotus accumulation layer 302 to information, and the lower charge storage layer 301 and the upper charge storage layer 302 store 1 respectively
2 value informations of position, it is achieved thereby that 24 value informations storages of the thin-film transistor memory.
It is illustrated in figure 2 the flow chart of the thin-film transistor memory multilevel storage method of the present invention, including step：
(A) thin-film transistor memory receiving grid, drain voltage；
(B) electronics in thin-film transistor memory or hole are injected separately into upper and lower charge storage layer.
Wherein, the step (A) applies the thin-film transistor memory grid, drain voltage value are by programming Control
's.It is illustrated in figure 3 realization storage information and mutually changes corresponding program conditions, is worth " 11 " for four of 2 information,
" 10 ", " 01 " and " 00 " specifies previous position to correspond to the state that electric charge stores in the lower charge storage layer 301, and latter position corresponds to
The state that electric charge stores in the upper charge storage layer 302.Using the thin-film transistor memory multilevel storage method
The film that the requirement of distribution and charge maintenance capability to threshold voltage after programming and common individual devices store 1 information is brilliant
Body pipe memory is identical, compared to the feasibility that traditional multistage multilevel storage technology has higher.
It is illustrated in figure 4 an a kind of implementation of the thin-film transistor memory of the present invention based on metal nanoparticle floating boom
The structure diagram of example.Wherein, the lower charge storage layer 301 includes controlling insulating layer 3011, a metal membrane
3012 and once tunneling insulation layer 3013, the lower control insulating layer 3011 be arranged in the flexible substrate 10, it is and described
It is lower control insulating layer 3011 be close to fix with the flexible substrate 10, it is described it is lower control insulating layer 3011 and meanwhile also with the bottom gate
Electrode 201 is close to fix, and the metal membrane 3012 is arranged on the lower control insulating layer 3011, and the lower metal foil
Film 3012 is close to fix with the lower control insulating layer 3011, and the tunneling insulation layer 3013 is arranged at the metallic film
Between 3012 and the semiconductive thin film 40, and the tunneling insulation layer 3013 and the metallic film 3012 and the semiconductor
Film 40 is close to fix；The upper charge storage layer 302 include one on control insulating layer 3021, one on metallic film 3022 and
Tunneling insulation layer 3023 on one, the upper tunneling insulation layer 3023 is arranged at the semiconductive thin film 40, and the upper tunnelling is exhausted
Edge layer 3023 is close to fix with the semiconductive thin film 40, and the upper metallic film 3022 is arranged at the upper tunneling insulation layer
On 3023, and the upper metallic film 3022 is close to connect with the upper tunneling insulation layer 3023, the upper control insulating layer
3021 are arranged between the upper metallic film 3022 and the top-gated electrode 202, and the upper control insulating layer 3021 and institute
State metallic film 3022 and the top-gated electrode 202 is close to fix.The lower charge storage layer 301 and the upper electric charge storage
Layer 302 is able to 12 value information of storage.
It is illustrated in figure 5 the flow chart of the thin-film transistor memory preparation method of the present invention, the film crystal
Pipe memory preparation method includes step：
(1) generation bottom gate thin film is prepared on flexible substrates；
(2) insulating layer is controlled under being prepared in bottom gate thin film；
(3) metal membrane is prepared on lower control insulating layer；
(4) tunneling insulation layer under being prepared on metal membrane；
(5) semiconductive thin film is prepared on lower tunneling insulation layer；
(6) source, drain electrode are prepared on semiconductive thin film；
(7) tunneling insulation layer is prepared on semiconductive thin film；
(8) metallic film is prepared on upper tunneling insulation layer；
(9) prepared on upper metallic film and control insulating layer；
(10) top-gated electrode is prepared on upper control insulating layer.
Further, the flexible substrate 10 can use PET or PI or other flexible materials to make.
The preparation of bottom gate thin film 201 described in the step (1) can be splashed using mask plate in the flexible substrate 10
ITO or gold evaporation or copper are penetrated to complete.The preparation of lower control insulating layer 3011 can pass through solwution method described in the step (2)
Or magnetron sputtering or atomic layer deposition prepare about 100nm thickness aluminum oxide film to complete.Lower metal foil described in the step (3)
Preparing for film 3012 can be by the gold thin film on the lower control insulating layer 3011 using d.c. sputtering deposition about 2nm thickness
(spontaneously form gold nano grain) completes.The preparation of lower tunneling insulation layer 3013 described in the step (4) can by
Spin coating or atomic layer deposition prepare 5-10nm aluminum oxide films to complete on the metal membrane 3012.In the step (5)
The semiconductive thin film 40 can be by being deposited pentacene (Pentacene) semiconductor film on the lower tunneling insulation layer 3013
Film or spin on polymers semiconductor P (NDI2OD-T2) film, solvent select paraxylene, and the semiconductive thin film can also select
With the semiconductive thin film of other materials；The preparation of source electrode 501 and the drain electrode 502 described in the step (6) can profit
With mask plate, gold evaporation or copper or other metals are completed on the semiconductive thin film 40.Upper tunnel described in the step (7)
Wear insulating layer 3023 preparation can by the semiconductive thin film 40 spin coating about 30nm thickness polystyrene film (PS,
Solvent n-butyl acetate) complete.The preparation of upper metallic film 3022 can be by institute described in the step (8)
State on tunneling insulation layer 3023 using the gold thin film (spontaneously forming gold nano grain) of d.c. sputtering deposition about 2nm thickness come complete
Into.The preparation of upper control insulating layer 3021 can pass through the spin coating on metallic film 3022 on described described in the step (9)
Polymethyl methacrylate (PMMA, solvent 2-ethoxyethanol) or Cytop are completed；Pushed up described in the step (10)
The preparation of gate electrode 202 can be completed by mask plate gold evaporation or copper or other metals.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or use the present invention.
A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and the principles and novel features disclosed herein phase one
The most wide scope caused.
Claims (10)
- A kind of 1. thin-film transistor memory, it is characterised in that including：One flexible substrate；One gate electrode group, the gate electrode group includes a bottom gate thin film and a top-gated electrode, wherein the bottom gate thin film is arranged at In the flexible substrate, and the bottom gate thin film is close to fix with the flexible substrate；One charge storage layer group, the charge storage layer group include charge storage layer on charge storage layer and one, lower electric charge Accumulation layer is arranged in the flexible substrate, and the lower charge storage layer is close to fix with the flexible substrate, the lower electricity Lotus accumulation layer also is close to fix with the bottom gate thin film；Semiconductor film, the semiconductive thin film are described between the lower charge storage layer and the upper charge storage layer Semiconductive thin film is arranged on the lower charge storage layer, and the semiconductive thin film is close to admittedly with the lower charge storage layer Fixed, the upper charge storage layer is arranged at the semiconductive thin film, and the upper charge storage layer and the semiconductive thin film are tight Patch is fixed, and the top-gated electrode is arranged at the upper charge storage layer, and the top-gated electrode and the upper charge storage layer are tight Patch is fixed；AndOne electrode group, the electrode group include a source electrode and a drain electrode, and the source electrode and the drain electrode may be contained within On the semiconductive thin film, the source electrode and the drain electrode are close to fix with the semiconductive thin film, and described power on Lotus accumulation layer is close to fix with the source electrode and the drain electrode.
- A kind of 2. thin-film transistor memory as claimed in claim 1, it is characterised in that the flexible substrate using PET or PI or other flexible materials are made.
- A kind of 3. thin-film transistor memory as claimed in claim 1, it is characterised in that the bottom gate thin film using ITO or Gold or copper into, the top-gated electrode using gold or copper into.
- 4. a kind of thin-film transistor memory as claimed in claim 1, it is characterised in that the source electrode and the drain electrode Using gold or copper into.
- 5. a kind of thin-film transistor memory as claimed in claim 1, it is characterised in that the semiconductive thin film is pentacene Semiconductive thin film or polymer semiconductor thin film.
- 6. a kind of thin-film transistor memory as claimed in claim 1, it is characterised in that the lower charge storage layer includes one Lower control insulating layer, once a metal membrane and tunneling insulation layer, the lower control insulating layer are arranged at the flexible liner On bottom, and it is described it is lower control insulating layer be close to fix with the flexible substrate, it is described it is lower control insulating layer and meanwhile also with the bottom Gate electrode is close to fix, the metal membrane be arranged at it is described it is lower control insulating layer on, and the metal membrane with it is described Lower control insulating layer is close to fix, and the tunneling insulation layer is arranged between the metallic film and the semiconductive thin film, And the tunneling insulation layer is close to fix with the metallic film and the semiconductive thin film.
- 7. a kind of thin-film transistor memory as claimed in claim 6, it is characterised in that described lower control insulating layer to aoxidize Aluminium film, the metal membrane are gold thin film, and the lower tunneling insulation layer is aluminum oxide film.
- 8. a kind of thin-film transistor memory as claimed in claim 1, it is characterised in that the upper charge storage layer includes one Upper control insulating layer, tunneling insulation layer, the upper tunneling insulation layer are arranged at the semiconductor on metallic film and one on one Film, and the upper tunneling insulation layer is close to fix with the semiconductive thin film, the upper metallic film is arranged at the upper tunnel Wear on insulating layer, and the upper metallic film is close to connect with the upper tunneling insulation layer, the upper control insulating layer is arranged at Between the upper metallic film and the top-gated electrode, and the upper control insulating layer and the upper metallic film and the top-gated Electrode is close to fix.
- 9. a kind of thin-film transistor memory as claimed in claim 8, it is characterised in that the upper tunneling insulation layer is polyphenyl Vinyl film, the upper metallic film are gold thin film, and the control insulating layer is made of polymethyl methacrylate or Cytop.
- 10. a kind of multilevel storage method of thin-film transistor memory, it is characterised in that including step：(A) thin-film transistor memory receiving grid, drain voltage；(B) electronics in thin-film transistor memory or hole are injected separately into upper and lower charge storage layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610914897.8A CN107978603A (en) | 2016-10-20 | 2016-10-20 | A kind of thin-film transistor memory and its multilevel storage method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610914897.8A CN107978603A (en) | 2016-10-20 | 2016-10-20 | A kind of thin-film transistor memory and its multilevel storage method |
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| US20120199821A1 (en) * | 2009-10-05 | 2012-08-09 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Organic dual-gate memory and method for producing same |
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| US20120199821A1 (en) * | 2009-10-05 | 2012-08-09 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Organic dual-gate memory and method for producing same |
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