KR101483931B1 - 캐시 로킹 디바이스 및 그 방법들 - Google Patents

캐시 로킹 디바이스 및 그 방법들 Download PDF

Info

Publication number
KR101483931B1
KR101483931B1 KR1020107002280A KR20107002280A KR101483931B1 KR 101483931 B1 KR101483931 B1 KR 101483931B1 KR 1020107002280 A KR1020107002280 A KR 1020107002280A KR 20107002280 A KR20107002280 A KR 20107002280A KR 101483931 B1 KR101483931 B1 KR 101483931B1
Authority
KR
South Korea
Prior art keywords
cache
cache line
state
data
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020107002280A
Other languages
English (en)
Korean (ko)
Other versions
KR20100053540A (ko
Inventor
셰드 알. 라만
데이비드 에프. 그린버그
캐서린 씨. 스테이서
클라스 엠. 브루스
맷 비. 스미틀
마이클 디. 스나이더
게리 엘. 휘센헌트
Original Assignee
프리스케일 세미컨덕터, 인크.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 프리스케일 세미컨덕터, 인크. filed Critical 프리스케일 세미컨덕터, 인크.
Publication of KR20100053540A publication Critical patent/KR20100053540A/ko
Application granted granted Critical
Publication of KR101483931B1 publication Critical patent/KR101483931B1/ko
Assigned to 제니스 인베스트먼츠, 엘엘씨 reassignment 제니스 인베스트먼츠, 엘엘씨 권리의 전부이전등록 Assignors: 프리스케일 세미컨덕터, 인크.
Assigned to 애플 인크. reassignment 애플 인크. 권리의 전부이전등록 Assignors: 제니스 인베스트먼츠, 엘엘씨
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020107002280A 2007-08-02 2008-06-17 캐시 로킹 디바이스 및 그 방법들 Expired - Fee Related KR101483931B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/832,797 2007-08-02
US11/832,797 US7827360B2 (en) 2007-08-02 2007-08-02 Cache locking device and methods thereof
PCT/US2008/067225 WO2009017890A2 (en) 2007-08-02 2008-06-17 Cache locking device and methods thereof

Publications (2)

Publication Number Publication Date
KR20100053540A KR20100053540A (ko) 2010-05-20
KR101483931B1 true KR101483931B1 (ko) 2015-01-19

Family

ID=40305158

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020107002280A Expired - Fee Related KR101483931B1 (ko) 2007-08-02 2008-06-17 캐시 로킹 디바이스 및 그 방법들

Country Status (5)

Country Link
US (1) US7827360B2 (https=)
JP (1) JP5419102B2 (https=)
KR (1) KR101483931B1 (https=)
CN (1) CN101772759B (https=)
WO (1) WO2009017890A2 (https=)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8856448B2 (en) * 2009-02-19 2014-10-07 Qualcomm Incorporated Methods and apparatus for low intrusion snoop invalidation
US8301838B2 (en) * 2009-11-04 2012-10-30 Nokia Corporation Method and apparatus for providing an application-level cache with a locked region and a floating region
US9448938B2 (en) * 2010-06-09 2016-09-20 Micron Technology, Inc. Cache coherence protocol for persistent memories
US8694737B2 (en) 2010-06-09 2014-04-08 Micron Technology, Inc. Persistent memory for processor main memory
US8613074B2 (en) 2010-09-30 2013-12-17 Micron Technology, Inc. Security protection for memory content of processor main memory
US8856587B2 (en) 2011-05-31 2014-10-07 Freescale Semiconductor, Inc. Control of interrupt generation for cache
US8775863B2 (en) * 2011-05-31 2014-07-08 Freescale Semiconductor, Inc. Cache locking control
TW201308079A (zh) * 2011-08-09 2013-02-16 Realtek Semiconductor Corp 快取記憶體裝置與快取記憶體資料存取方法
KR101291040B1 (ko) * 2011-08-12 2013-08-01 주식회사 에이디칩스 캐시메모리의 캐시 라인 락킹방법
KR101306623B1 (ko) * 2011-08-12 2013-09-11 주식회사 에이디칩스 캐시메모리의 캐시 웨이 락킹방법
CN103019954A (zh) * 2011-09-22 2013-04-03 瑞昱半导体股份有限公司 高速缓存装置与高速缓存数据存取方法
US9176885B2 (en) * 2012-01-23 2015-11-03 International Business Machines Corporation Combined cache inject and lock operation
US9141544B2 (en) 2012-06-26 2015-09-22 Qualcomm Incorporated Cache memory with write through, no allocate mode
US20140164708A1 (en) * 2012-12-07 2014-06-12 Advanced Micro Devices, Inc. Spill data management
CN103885892A (zh) * 2012-12-20 2014-06-25 株式会社东芝 存储器控制器
CN104641347B (zh) * 2013-03-11 2018-06-05 华为技术有限公司 函数调用方法、装置和终端设备
CN103136080B (zh) * 2013-03-12 2016-07-13 青岛中星微电子有限公司 一种缓存锁定功能的测试方法和装置
KR102116364B1 (ko) 2013-11-18 2020-05-28 삼성전자주식회사 메모리 시스템 및 그에 따른 반도체 메모리의 결함 메모리 셀 관리방법
US9268715B2 (en) * 2014-02-24 2016-02-23 Freescale Semiconductor, Inc. System and method for validation of cache memory locking
US9356602B1 (en) * 2015-05-14 2016-05-31 Xilinx, Inc. Management of memory resources in a programmable integrated circuit
US10621119B2 (en) 2016-03-03 2020-04-14 Samsung Electronics Co., Ltd. Asynchronous communication protocol compatible with synchronous DDR protocol
US10592114B2 (en) 2016-03-03 2020-03-17 Samsung Electronics Co., Ltd. Coordinated in-module RAS features for synchronous DDR compatible memory
US10810144B2 (en) * 2016-06-08 2020-10-20 Samsung Electronics Co., Ltd. System and method for operating a DRR-compatible asynchronous memory module
GB2566469B (en) * 2017-09-13 2021-03-24 Advanced Risc Mach Ltd Cache line statuses
CN109933543B (zh) * 2019-03-11 2022-03-18 珠海市杰理科技股份有限公司 Cache的数据锁定方法、装置和计算机设备
CN119782211A (zh) * 2024-12-04 2025-04-08 天翼云科技有限公司 一种缓存操作方法、装置和电子设备

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000090009A (ja) 1998-07-31 2000-03-31 Hewlett Packard Co <Hp> キャッシュメモリにおいてキャッシュラインを置き換えるための方法および装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4513367A (en) * 1981-03-23 1985-04-23 International Business Machines Corporation Cache locking controls in a multiprocessor
JPH01255944A (ja) * 1988-04-05 1989-10-12 Mitsubishi Electric Corp キャッシュメモリ
US5353425A (en) 1992-04-29 1994-10-04 Sun Microsystems, Inc. Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature
US5493667A (en) * 1993-02-09 1996-02-20 Intel Corporation Apparatus and method for an instruction cache locking scheme
US5694567A (en) * 1995-02-09 1997-12-02 Integrated Device Technology, Inc. Direct-mapped cache with cache locking allowing expanded contiguous memory storage by swapping one or more tag bits with one or more index bits
US5822764A (en) * 1996-03-04 1998-10-13 Motorola, Inc. Method and circuit for efficiently replacing invalid locked portions of a cache with valid data
US6044478A (en) 1997-05-30 2000-03-28 National Semiconductor Corporation Cache with finely granular locked-down regions
KR20000026339A (ko) * 1998-10-20 2000-05-15 윤종용 잠금 및 플러쉬 기능을 갖는 캐쉬 메모리 시스템
JP3495266B2 (ja) * 1998-11-13 2004-02-09 Ｎｅｃエレクトロニクス株式会社 キャッシュロック装置及びキャッシュロック方法
US6438655B1 (en) * 1999-04-20 2002-08-20 Lucent Technologies Inc. Method and memory cache for cache locking on bank-by-bank basis
US6629209B1 (en) * 1999-11-09 2003-09-30 International Business Machines Corporation Cache coherency protocol permitting sharing of a locked data granule
US7900023B2 (en) * 2004-12-16 2011-03-01 Intel Corporation Technique to enable store forwarding during long latency instruction execution

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000090009A (ja) 1998-07-31 2000-03-31 Hewlett Packard Co <Hp> キャッシュメモリにおいてキャッシュラインを置き換えるための方法および装置

Also Published As

Publication number Publication date
WO2009017890A3 (en) 2009-04-09
CN101772759B (zh) 2012-06-27
US20090037666A1 (en) 2009-02-05
WO2009017890A2 (en) 2009-02-05
JP2010535387A (ja) 2010-11-18
US7827360B2 (en) 2010-11-02
KR20100053540A (ko) 2010-05-20
CN101772759A (zh) 2010-07-07
JP5419102B2 (ja) 2014-02-19

Similar Documents

Publication Publication Date Title
KR101483931B1 (ko) 캐시 로킹 디바이스 및 그 방법들
US5740400A (en) Reducing cache snooping overhead in a multilevel cache system with multiple bus masters and a shared level two cache by using an inclusion field
US8495308B2 (en) Processor, data processing system and method supporting a shared global coherency state
EP0434250B1 (en) Apparatus and method for reducing interference in two-level cache memories
US8909871B2 (en) Data processing system and method for reducing cache pollution by write stream memory access patterns
US20070136535A1 (en) System and Method for Reducing Unnecessary Cache Operations
US6275909B1 (en) Multiprocessor system bus with system controller explicitly updating snooper cache state information
WO2010035426A1 (ja) バッファメモリ装置、メモリシステム及びデータ転送方法
US8117399B2 (en) Processing of coherent and incoherent accesses at a uniform cache
EP2224343B1 (en) Data processing system
US6763433B1 (en) High performance cache intervention mechanism for symmetric multiprocessor systems
US20100030966A1 (en) Cache memory and cache memory control apparatus
US8473686B2 (en) Computer cache system with stratified replacement
US7325102B1 (en) Mechanism and method for cache snoop filtering
US5987544A (en) System interface protocol with optional module cache
JPH10326226A (ja) キャッシュ動作要求間の競合に応答して置換用の代替キャッシュ・エントリを選択する方法及びシステム
GB2546245A (en) Cache memory
US6826656B2 (en) Reducing power in a snooping cache based multiprocessor environment
US7472226B1 (en) Methods involving memory caches
US6279086B1 (en) Multiprocessor system bus with combined snoop responses implicitly updating snooper LRU position
KR100326632B1 (ko) 에이치_알 상태를 포함하는 캐시 일관성 프로토콜
US8271733B2 (en) Line allocation in multi-level hierarchical data stores
US20060015689A1 (en) Implementation and management of moveable buffers in cache system
EP4006734B1 (en) Methods and apparatus for transferring data within hierarchical cache circuitry
US20060224834A1 (en) Write-back cache methods and apparatus

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

A201 Request for examination
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R14-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R14-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

FPAY Annual fee payment

Payment date: 20171219

Year of fee payment: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

FPAY Annual fee payment

Payment date: 20181226

Year of fee payment: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

FPAY Annual fee payment

Payment date: 20191217

Year of fee payment: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20250114

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

H13 Ip right lapsed

Free format text: ST27 STATUS EVENT CODE: N-4-6-H10-H13-OTH-PC1903 (AS PROVIDED BY THE NATIONAL OFFICE); TERMINATION CATEGORY : DEFAULT_OF_REGISTRATION_FEE

Effective date: 20250114

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20250114