KR101457243B1 - Passivation layer for a circuit device and method of manufacture - Google Patents

Abstract

According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter 2 /day, a moisture absorption less than 0.04 percent, a dielectric constant less than 10, a dielectric loss less than 0.005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 1015 ohm- centimeter, and a defect density less than 0.5/centimeter 2 . To be accompanied, when published, by Figure 1 of the accompanying drawings.

Description

≪ Desc / Clms Page number 1 > PASSIVATION LAYER FOR A CIRCUIT DEVICE AND METHOD OF MANUFACTURE [

BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] The present disclosure relates generally to circuit devices and circuit boards, and more particularly to passivation systems of circuit devices and / or circuit boards and methods of making same.

Circuit devices having electronic components that are integrated and formed on a substrate have enjoyed wide acceptance due to the extensive use they can provide. The use of such circuit devices may include applications that are not easy to operate in a protected environment, are costly, and / or limit system performance. In these applications, the electrical performance of the components is improved, and the components of the circuit device are exposed to noxious contaminants such as moisture, moisture, particulates, or ionic impurities, such as those generated from gases or elements based on sodium or chlorine A passivation technique may be employed to protect it from the material. These techniques enable the elimination of costly enclosure enclosures or packages, allowing circuit functions to be packed more densely, enabling higher packaging density, lower weight, and higher frequency performance.

According to one embodiment of the present disclosure, a method of passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and electrically connecting the substrate surface and the electrical component to the first protective dielectric layer. . ≪ / RTI > A first protective dielectric layer is 0.01 g / m ² / day small moisture permeability than, less water absorbency than 0.04%, a dielectric constant, a large breakdown voltage strength of a smaller dielectric loss, 8,000,000 V / cm than 0.005 than 10, and 10 ¹⁵ Ω Lt; RTI ID = 0.0 > cm < / RTI >

According to another embodiment of the disclosure, a circuit device generally comprises a substrate and a first protective dielectric layer. The substrate has a substrate surface on which at least one electrical circuit component is formed. A first protective dielectric layer is 0.01 g / m ² / day small moisture permeability than, less water absorbency than 0.04%, a dielectric constant, a large breakdown voltage strength of a smaller dielectric loss, 8,000,000 V / cm than 0.005 than 10, and 10 ¹⁵ Ω Lt; RTI ID = 0.0 > cm < / RTI >

Embodiments of the present disclosure may provide a number of technical advantages. Some or all of the embodiments may benefit from the advantages described below, or none of the embodiments may benefit. According to one embodiment, systems and methods are provided for passivation of circuit devices having electrical components or other additional components formed on a substrate during different processing steps. The proposed technique for dielectric coating, in some embodiments, provides relatively accurate control of thickness uniformity and absolute thickness across the substrate or wafer, as well as good z conformality to three-dimensional features Bring it. Accurate control of thickness results in both excellent electrical performance and excellent moisture and contaminant protection. The use of the proposed technique eliminates the need for conventional hermetic packaging techniques and enclosures and also improves performance and reliability for both sealed and non-sealed applications.

Other technical advantages will be apparent to those of ordinary skill in the art.

A more complete understanding of the embodiments of the disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

1 is a side elevational view of one embodiment of an integrated circuit device including a passivation system in accordance with the teachings of the present disclosure;

Figure 2 is a flow diagram illustrating several measures that may be performed to produce the embodiment of Figure 1;

3 is a diagram illustrating a schematic summary of various wafer level embodiments of the present disclosure.

Figures 4A-4D are side elevation views shown during various stages of fabrication of the circuit device of Figure 1, which may be manufactured according to the teachings of the present disclosure.

5A and 5B are perspective sectional views of one embodiment of a passivation layer system of a circuit assembly of the present disclosure.

Figure 6 is a flow diagram illustrating several measures that may be performed to produce the embodiment of Figures 5A and 5B.

Figure 7 is a diagrammatic representation of a specific assembly level embodiment of the disclosure.

8 is a partial enlarged view of a transistor having a passivation system according to another embodiment of the present invention.

Referring to the drawings, FIG. 1 illustrates one embodiment of a circuit device 10 constructed in accordance with the teachings of the present disclosure. Circuit device 10 generally includes a substrate 12 having a substrate surface 14 on which a number of electrical components 16 are integrated and formed. The substrate 12 of Figure 1 may be formed of any semiconductor material suitable for the fabrication of the circuit device 10 and may be formed of any suitable material such as, for example, silicon (Si), gallium arsenide (GaAs), gallium- Ge (germanium), SiC (silicon carbide), or InP (indium-phosphide). Each of these types of materials may be provided on a substantially planar surface 14 on which the electrical components 16 may be formed.

The electrical components 16 may include any component that may be formed on the substrate surface 14, which may be, for example, a transistor, a capacitor, a resistor, an inductor, In the particular embodiment shown, the electrical components 16 may be several transistors 16a, capacitors 16b, and resistors 16c, but the circuit device 10 may deviate from the teachings of the present disclosure. But may include other types of electrical components. In one embodiment, the transistor 16a may be a pseudomorphic high electron mobility transistor (pHEMT) device having a source region S, a gate region G, and a drain region D, respectively. And an air bridge 18a connecting the source region S of each transistor 16a is shown. Another air bridge 18b is provided for electrical connection of the capacitor 16b. Air bridges 18a and 18b may also be referred to herein as additional components 18. The additional component 18 may refer to any suitable component that rests on the components 16 for various purposes such as, but not limited to, electrical connection, thermal conduction, and / have.

A first protective dielectric layer 22, a second protective dielectric layer 24, and a third dielectric layer 26 are disposed on the substrate surface 14 and the electrical components 16. The first protective dielectric layer 22, the second protective dielectric layer 24 and the third dielectric layer 26 may be formed of a material such as moisture, moisture, particulate, corrosive material, and sodium, potassium, or chlorine To passivate the substrate 12 and components 16 and 18 from various harmful charge traps and contaminants such as ionic impurities of the substrate 12.

Implementations of known circuit devices have provided passivation of electrical components from hazardous contaminants using electrical components and a dielectric layer disposed directly on the substrate surface. Such a dielectric layer may be formed of an insulating material such as Si ₃ N ₄ (silicon-nitride) or SiO ₂ (silicon-dioxide). However, such known dielectric materials have the problem that their ability to prevent moisture degradation is generally less than required. Therefore, the use of silicon-nitride materials is not environmentally protected or requires application of a relatively thick layer to provide adequate protection to circuit devices in a non-sealed environment. The problem with this approach is that despite the relatively large thickness of the material, passivation of the circuit assembly is only usually achieved. Also, a relatively large thickness may adversely affect the performance of the circuit device due to the increased inter-node capacitance between the active regions of the device, such as the source (S), gate (G), and drain have. Also, due to the relatively thick layers of silicon nitride or other conventional dielectrics, high stresses can result in device or dielectric cracking, delamination, and / or piezoelectric effects that degrade device performance.

As an alternative to thick silicon nitride for moisture protection, a second layer of material, such as Chemical Vapor Deposition (CVD) of silicon carbide or atomic layer deposition (ALD) of aluminum oxide, Or a third passivation layer followed by a layer of silicon dioxide has been implemented. The use of additional silicon carbide or ALD protective layers on top of the first layer of silicon nitride further increases the inter-node capacitance beyond that of silicon nitride below, thereby degrading device performance. In addition, silicon nitride and / or silicon carbide can be attacked more and more over time due to high moisture susceptibility.

It is also known that the first protective dielectric layer 22 is capable of protecting the gate region from charge traps and contamination that may occur in subsequent processing steps. Therefore, the first protective dielectric layer 22 is applied immediately before and / or after the gate is fabricated. As a result, in subsequent manufacturing steps, such as formation of air bridges 18 and RF and DC conductors or interconnections, exposure that may be vulnerable to short circuiting due to particulate, electrochemical, or galvanic corrosion Metal lines can be left behind. To address the potential corrosion of these exposed metal lines, the proposed approach included chemical vapor deposition of silicon nitride or silicon carbide. One problem associated with conventional chemical vapor deposition processes may be line-of-sight deposition for dielectric coverage. Therefore, areas immediately below the air bridge may not be well coated and, if present, may be susceptible to corrosion attack or leakage current generation. In addition, the second protective dielectric layer of silicon nitride and / or silicon carbide may be vulnerable to moisture degradation. The use of atomic layer deposition coatings on silicon nitride layers provides conformality to three-dimensional surface features, but also increases inter-node capacitance, as described above, to degrade device performance. Certain embodiments such as high performance microwave and millimeter wave MMIC (Monolithic Microwave Integrated Circuit) may not tolerate significant loss of radio frequency (RF) performance.

In one embodiment of the disclosure, dielectric layers 22 and 24 may be provided that implement a water impermeable material that is superior to the moisture protection properties of known dielectric materials. In certain embodiments, protective dielectric layers 22 and 24 may be provided that implement a water impermeable material having excellent voltage yielding properties of known dielectric materials. That is, the use of materials having relatively high voltage yield characteristics can enable the formation of protective dielectric layers 22 and 24 thinner than conventionally used to achieve similar voltage yield performance. In this aspect, a layer of dielectric material, much thinner than known passivation systems, is deposited on the electrical component 16, additional components 18 and substrate surface 14 to provide passivation from moisture and other contaminants .

In one embodiment, the first protective dielectric layer generally has a water permeability of less than 0.01 g / m ² / day, a water absorbency of less than 0.04%, a dielectric constant of less than 10, a dielectric loss of less than 0.005, a dielectric loss of greater than 8,000,000 V / cm A breakdown voltage strength, and a sheet resistance greater than 10 < ¹⁵ > OMEGA cm. In certain embodiments, the first protective dielectric layer 22 may be formed of alumina (Al ₂ O ₃ ). Alumina can be deposited in a relatively thin layer in a continuous manner. Alumina also has relatively high voltage yield characteristics. In yet another embodiment, the first protective dielectric layer 22 may be formed of other materials such as high density silicon nitride, tantalum oxide, beryllium oxide, and hafnium oxide.

In certain embodiments, the first protective dielectric layer 22 is formed of alumina and has a thickness in the range of 50 to 2000 Angstroms. In this thickness range, the first protective dielectric layer 22 can adequately protect the circuit device 10 from moisture without undue influence on the apparent capacitance of the electrical components 16. In one embodiment, the thickness of this layer can be precisely controlled to maintain the repeatable performance of many circuit devices 10 that can be configured in accordance with various embodiments.

The second protective dielectric layer 24 may be operable to passivate additional components 18. The application of the second protective dielectric layer 24 provides passivation of the additional components 18 that are not passivated by the first protective dielectric layer 22. In certain embodiments in which the additional component 18 is an air bridge, application of the first protective dielectric layer 22 prior to forming the air bridge is limited to forming an air bridge 20 following formation of the air bridge. Lt; RTI ID = 0.0 > 22 < / RTI > The second protective dielectric layer 24 can also be used to protect the second protective dielectric layer 24 from being damaged by additional processing steps such as, for example, sawing, scribing moats, or providing interconnections to other devices. It may provide passivation for portions of the first protective dielectric layer 22 that may be damaged.

The second protective dielectric layer 24 may be made of the same dielectric material, but in some embodiments may be made of the dielectric material described above for the first protective dielectric layer 22. In another embodiment, the second protective dielectric layer 24 may be made of any material described below with respect to the third dielectric layer 26. In one embodiment, the second protective dielectric layer 24 may have a thickness ranging from 50 to 2000 Angstroms. Other specific embodiments are described in detail below with respect to FIG.

Alumina may be water impermeable, but its surface may exhibit chemical attack in the presence of low humidity, high humidity, and / or condensed moisture for long periods of time. Thus, a third dielectric layer 26 can be provided. The third dielectric layer 26 may be formed of any material that is chemically stable in the presence of high humidity, extended humidity, and / or moisture condensation and vapor penetration. In one embodiment, the third dielectric layer 26 may be formed of silicon dioxide (SiO ₂ ). In yet another embodiment, the third dielectric layer 26 may be formed of parylene. Poly-tetrafluoro-p-xylylene, aromatic-fluorinatetd VT-4, parylene HT® (a trademark of a special coating system), or other fluorinated parylene- like film may be delayed to prevent moisture from reaching the first protective dielectric layer 22 and / or the second protective dielectric layer 24, and may be used for the layer 26. These materials exhibit excellent moisture retardation properties and can remain functionally stable over a wider temperature range than other classes of parylene. Such materials can not exhibit high film stress due to high temperature exposure. Such materials may also have lower dielectric constants than silicon dioxide. In one embodiment, the third dielectric layer 26 may have a thickness ranging from about 100 to 1000 Angstroms. In addition to these parylene entities, any material that exhibits the properties described below with respect to layer 156 or 158 in connection with Fig. 5 may be used for the third dielectric layer 26. Fig.

Thus, the passivation of the circuit device 10 may be provided by the first protective dielectric layer 22, the second protective dielectric layer 24, and the optional third dielectric layer 26. Each of these layers 22, 24, and 26 may be thin enough to provide adequate protection from gaseous, liquid, and solid contaminants, including moisture, while not adversely affecting the performance characteristics of the circuit device 10. [

Figure 2 illustrates a series of operations that may be performed to fabricate an embodiment of circuit device 10 in accordance with the present disclosure. In operation 100, a method of providing an electrical and environmental protective coating system is disclosed. At operation 102, one or more electrical components 16 may be formed on the substrate surface 14 using known integrated circuit fabrication techniques. At operation 104, a first protective dielectric layer 22 may be deposited on the substrate surface 14 and the electrical component 16. In one embodiment, the thickness of the first protective dielectric layer 22 may have a thickness ranging from 50 to 2000 ANGSTROM. The first protective dielectric layer 22 may comprise a specific material as described above.

In operations 106-110, one approach may be provided for forming one or more additional components 18 on the circuit device 10. Selected portions of the first protective dielectric layer 22 from the circuit device 10 at operation 106 may be etched to provide a contact surface for attachment of the additional component 18. Next, in operation 108, one or more additional components 18 are formed on these contact surfaces. A second protective dielectric layer 24 may then be deposited over the first protective dielectric layer 22 and optional additional components 18 formed on the circuit device 10 at operation 110. In one embodiment, the second protective dielectric layer 24 may have a thickness ranging from 50 to 2000 Angstroms. Accordingly, the cumulative thickness of the first protective dielectric layer 22 and the second protective dielectric layer 24 may have a thickness ranging from 100 to 4000 A.

In one embodiment, an adhesion promoter may be applied over the second protective dielectric layer 24 to improve the adhesion of the third dielectric layer 26 to the second protective dielectric layer 24 in operation 112. In one embodiment, the adhesion promoter may be a layer of silicon dioxide that is used independently or in conjunction with gamma-methacryloxypropyltrimethoxysilane; However, other adhesion promoters may be used. A third dielectric layer 26 may then be applied to the second protective dielectric layer 24 at operation 114. In one embodiment, the thickness of the third dielectric layer 26 may range from 100 to 1000 Angstroms.

At operation 116, the method of application of the passivation layer has been completed and the circuit device 10 can then be used. Operations 100 through 116 illustrate one embodiment of a method of making a circuit device 10 in which protective dielectric layers 22 and 24 are applied in a number of processing steps. Using this approach, the thickness of the first protective dielectric layer 22 adjacent to the electronic components 16 in the air cavity 20 can be easily controlled. The thickness of the first protective dielectric layer 22 proximate to the electronic component 16 can be readily determined by applying various deposition techniques known in the art such as by applying the first protective dielectric layer 22 prior to formation of the additional component 18, Lt; / RTI >

3 is a table summarizing various embodiments 1-5 of the disclosure that can provide improved electrical performance and improved environmental protection over known passivation systems. Each of Embodiments 1 to 5 may include a material that can be used to form the first dielectric layer 22, the second dielectric layer 24, and / or the third dielectric layer 26 (e.g., alumina, silica, and / or parylene F, aromatic fluorinated VT-4, parylene HT®, or other fluorinated parylene-based membranes).

1, the first protective dielectric layer 22 of Examples 1 to 5 has a water permeability of less than 0.01 gram / meter ² / day, a water absorption of less than 0.04%, a dielectric constant of less than 10, Low dielectric loss, breakdown voltage strength greater than 8,000,000 volts / centimeter, and sheet resistance greater than 10 ¹⁵ ohm-centimeters. In one particular embodiment, the first protective dielectric layer 22 is formed of alumina having relatively low moisture permeability, relatively low ion mobility, and relatively high voltage yield strength characteristics than other known materials such as standard silicon nitride or silicon dioxide . The first protective dielectric layer 22 may be deposited by many deposition techniques such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition. It is possible to provide relatively accurate thickness control, good conformality on the substrate surface 14 and the components 16 and 18, and removal of physical or radiated damage during dielectric deposition, level deposition may be used.

Additional dielectric protection layers may be added according to specific device and / or assembly packaging methods, as described above with respect to FIG. The thickness of the dielectric layers 22, 24, and 26 may be a function of device design, operating frequency, and performance requirements. Embodiments 1 to 5 shown in FIG. 3 are similar to those of the first embodiment shown in FIG. 3 except that the RF integrated circuit (IC) including components such as a bipolar transistor such as a field effect transistor (FET) and a heterojunction bipolar transistor (HBT) including a pseudomorphic high electron mobility transistor (pHEMT) Can be customized specifically for the circuit. In general, a relatively low dielectric thickness improves device performance associated with dielectric load effects such as inter-node capacitance, increases capacitance per unit area of integrated capacitors, and reduces capacitor size. A relatively high dielectric thickness reduces moisture permeability and improves protection against particulates, physically occurring damage, ionic impurities, and corrosive contaminants, whether in the form of solid, liquid, or gas. The thickness of the dielectric layers 22, 24, and 26 shown in FIG. 3 can be tailored to RF integrated circuits where control of inter-node capacitance and control of dielectric load effects is critical to circuit performance. Other combinations of materials and thicknesses may be selected in accordance with the teachings of this disclosure.

In the first embodiment of FIG. 3, only the first protective dielectric layer 22 made of alumina is used. The first embodiment provides the electrical, physical, and environmental protection of the source region S, the gate region G, and the drain region D of the transistor 16a of Fig. 1 while minimizing the minimum inter-node capacitance Thereby providing improved electrical performance. Example 1 can also provide improved electrical performance over known materials such as silicon nitride or silicon dioxide in both hermetic and non-hermetic environments. Improved performance can be provided since thinner dielectrics than conventional silicon nitride or silicon dioxide can be utilized. Example 1 also provides partial control of temperature and / or humidity at the system level to provide conditions that minimize or eliminate moisture condensation on the active circuit for an extended period of time, and / or provide conditions that minimize or eliminate high temperature and humidity exposure of the active circuit Lt; / RTI > This protection can be achieved at the system level by humidification control through a dehumidifier or desiccant.

Example 2 provides a first protective dielectric layer 22 and a second protective dielectric layer 24 formed of alumina. The second protective dielectric layer 24 covers additional unprotected components 18 such as air bridges and thick metal lines and may be formed after the first protective dielectric layer 22 is applied. The second embodiment may also be desirable in an enclosed or less severe humidity environment where protection against conductive or corrosive solid, liquid, or gaseous materials may exist.

The third and fourth embodiments provide a third dielectric layer 26 that may be formed of silica, parylene F, parylene HT®, or other fluorinated parylene-based films as described above. The third dielectric layer 26, formed of silica or parylene F, parylene < RTI ID = 0.0 > HT, < / RTI > or other fluorinated parylene-based film yields the first protective dielectric layer 22 and / or the second protective dielectric layer 24 Protects the first protective dielectric layer 22 and / or the second protective dielectric layer 24 from high humidity, extended humidity, and / or condensed moisture that may expose the underlying components 16 and 18. Parylene < / RTI > F or parylene < RTI ID = 0.0 > HT < / RTI > may have a lower dielectric constant than silica and therefore have less impact on electrical performance. Parylene F or parylene < RTI ID = 0.0 > HT ~ < / RTI > such as ALD deposited silica can be vapor deposited and is highly conformal to penetrate into the smallest recesses and has an air bridge and high aspect ratio ) With a relatively uniform thickness underneath the additional components 18 with the recesses. The first protective dielectric layer 22 and / or the second protective dielectric layer 24 made of alumina may also function as an adhesion promoter since parylene F or parylene < RTI ID = 0.0 > HT < / RTI & can do. As noted above, the adhesion promoter may be applied to the second protective dielectric layer 24 prior to deposition of the third dielectric layer 26. The adhesion promoter can be any suitable material that enhances the adhesion of the third dielectric layer 26 and, in one particular embodiment, can be used independently or in conjunction with gamma-methacryloxypropyltrimethoxysilane Is a silicon dioxide layer used. Silicon dioxide provides an ideal surface for bonding to adhesion promoters such as gamma-methacryloxypropyltrimethoxysilane and binds well to alumina and parylene F or parylene HT®.

In Example 5, parylene F or parylene < RTI ID = 0.0 > HT < / RTI > is utilized as the second protective dielectric layer 24 in FIG. Parylene F or parylene < RTI ID = 0.0 > HT < / RTI > covers unprotected additional features such as air bridges and thick metal lines that can be formed after the first protective dielectric layer 22. Parylene F or parylene < RTI ID = 0.0 > HTR < / RTI > also protects the underlying first protective dielectric layer 22 from being dissolved or attacked by moisture condensation. Paraylenes F or parylenes HTs have the advantage of lower dielectric constant than silica or other inorganic materials and lower dielectric constants than most organic materials.

4A-4D are cross-sectional views that appear during various manufacturing steps of circuit device 40 in accordance with the teachings of the present disclosure. The circuit device 40 is generally similar to the circuit device 10 of Fig. 4A, a gate recess and gate metal applied to a plurality of transistor fingers 46a, a cap bottom applied to the capacitor 46b, and a resistor 46c are formed on the substrate surface 44 are shown. An isolation implant has been previously performed to form the active channel region 48 isolated from the transistor 46a and the resistor 46c. As described above in connection with FIG. 1, in one embodiment, transistor 46a may be a pHEMT. Electrical component 46 of FIG. 4A and associated substrate 42 may be fabricated in accordance with operation 100 of FIG.

4B shows the circuit device 40 of FIG. 4A with the first protective dielectric layer 50 applied in accordance with operation 102. As shown, each electrical component 46 can be exposed to a substantially line-of-sight deposition to enable uniform thickness deposition of the first protective dielectric layer 50. [ That is, access to the structures of the electrical component is generally not disturbed by additional devices, such as the air bridge 54.

FIG. 4C shows the results of circuit device 40 in which operations 104 through 108 are performed on circuit device 40 of FIG. 3B. A contact surface 52 was created by etching a portion of the first protective dielectric layer 50 for attachment of additional components 54, such as an air bridge. The air bridge may be used to establish a parallel connection to the source transistor finger 46a to increase the output power and to connect to the top plate of the capacitor 46b.

4D shows a second protective dielectric layer 56 and a third dielectric layer 58 applied to passivate the substrate surface 44, the electrical component 46, and the additional component 54 in accordance with operations 110-114. Circuit device 40 of FIG. Thus, a system and method is provided in which a circuit device (40) having additional components (54) can be effectively sealed from harmful contaminants without sacrificing the performance of the circuit device (40).

5A and 5B illustrate an embodiment of a circuit board assembly 160 that may be passivated in accordance with another embodiment of the teachings of the present disclosure. The circuit board assembly 160 generally includes a number of discrete electrical components 164 and 170 attached to the circuit device 140 and the circuit board 161. Circuit board assembly 160 includes a number of assemblies including board trace 162 and wire interconnection 166 that provide electrical interconnection between circuit device 140 and electrical components 164 and 170. [ Level structures. Above the circuit board assembly 160 is a dielectric layer 156 and a second protective dielectric layer 158. Circuit device 140 has a dielectric layer 150 that has been applied during device fabrication prior to assembly on the circuit board. The circuit device 140 and circuit components 164 and 164 of the circuit board assembly 160 may be formed by applying a second protective dielectric layer 156 and / or a third dielectric layer 158 during assembly level steps of fabrication, Passivation may be provided at the assembly level of the fabrication for protection of the device.

Circuit board 161 may be any suitable device from which a plurality of discrete electrical components 164 and 170 may be configured. In general, the circuit board 161 may be a rigid substrate or a flexible substrate in a structure for securing individual electrical components 164 and 170 in a fixed physical relationship with respect to each other. In one embodiment, the circuit board 161 includes a plurality of electrical components 164 and 170 and circuit devices 140 that can be attached using solder 172 or an adhesive 172, such as an isotropic conductive adhesive, And has a planar outer surface 168. The circuit board 161 may also have a board trace 162 formed of a conductive material to interconnect certain individual electrical components 164 and 170 with respect to each other and / or to the circuit device 140. The circuit device 140 may be similar to the circuit devices 10 and 40 of Figure 1 and Figures 4A-4D, respectively.

Individual electrical components 164 and 170 refer to electrical components that are manufactured independently of each other. That is, each discrete electrical component 164 or 170 may be fabricated on a substrate according to a particular process that may differ from other discrete electrical components configured on the circuit board assembly 160. Examples of individual electrical components include, but are not limited to, resistors, capacitors, inductors, diodes, transistors, and the like.

Circuit device 140 and individual electrical components 164 and 170 may be electrically coupled together on circuit board 161 using board traces 162 and / or interconnect 166 to produce any desired effect. Lt; / RTI > Circuit device 140 and individual electrical components 164 and 170 may be configured on circuit board 161 during the assembly level phase of manufacturing. The circuit device 140 may include a first protective dielectric layer 150 and / or a second protective dielectric layer 156 as described above for the first protective dielectric layer 22 and / or the second protective dielectric layer 24 of FIG. Can be coated.

In many cases, additional processing techniques of the circuit device 140 may be preferred following fabrication at the wafer level. For example, the circuit device 140 may be cut from the wafer using a saw or other cutting tool, which may be scribe moats. Interconnections 166 from circuit device 140 to component 164 may be formed at an assembly level that may be vulnerable to the harmful contaminants as described above. Thus, lack of dielectric protection at the perimeter, device edge, and interconnect 166 can cause the circuit device 140 to become susceptible to moisture attack, particulate, or other contaminants.

The circuit board 161 may also require environmental protection to perform reliably in the case of a non-hermetic enclosure and / or when physical particulates can not be properly controlled. Known passivation systems use a relatively thick layer of parylene C, D, or N, which may have a thickness of, for example, 10 micrometers (100,000 A) or more. This relatively thick parylene layer may be unsatisfactory for microwave and millimeter wave circuits where dielectric loading can alter and / or degrade circuit performance. Parylene C, D, or N can not withstand high temperatures. Exposure to high temperatures, which can occur in high power devices, can increase the crystallinity of parylene C, D, or N. Increasing the crystallinity increases the stress in the parylene film and at the parylene interface to the circuit board assembly 160. This increase in stress may cause de-lamination of the parylene species, which may result in performance degradation or failure.

In one embodiment of the disclosure, the application of the second protective dielectric layer 156 and / or the third dielectric layer 158 at the assembly level is provided in contrast to the wafer level in the production phase. By combining wafer level coatings with assembly level coatings, individual electrical components 164 and 170, circuit devices 140, board traces 162, metal interconnects 166, scribe moats, die edges ), And external interconnections to circuit board assemblies 160 such as wire or ribbon bonds, etc., and other assembled components may all be coated simultaneously. In addition, the required dielectric thickness using certain embodiments of the disclosure may in many cases be less than a second order of magnitude smaller than known passivation systems using parylene, silicon, or urethane coatings. Thus, this reduced thickness can minimize degradation of circuit performance in certain embodiments.

A dielectric constant of less than 3.0, a dielectric loss of less than 0.008, a breakdown voltage strength in excess of 2 MV / cm (million volts / centimeter), a temperature stability of up to 300 DEG C, A pinhole free of a film greater than Å, hydrophobic with a wetting angle greater than 45 degrees, conformally deposited above and below a 3D structure with thickness uniformity of less than 30% The second protective dielectric layer 156 and / or the third protective dielectric layer 158 may be coated with the dielectric material. This dielectric material can be applied during the assembly level production phase to passivate the circuit board 161, board traces 162, circuit devices 140, individual electrical components 164 and 170, and assembly level structures from the environment. have. This dielectric material may be applied as a second protective dielectric layer 156 or as a third dielectric layer 158. The dielectric material is generally chemically stable to water vapor or liquid, thus protecting the first protective dielectric layer 150 and / or the second protective dielectric layer 156. The dielectric material has excellent moisture delay characteristics and is functionally stable over a wider temperature range than the other known passivation materials described above. The dielectric material also has a lower intrinsic dielectric constant than other known passivation materials. In one embodiment, the third dielectric layer 26 may have a thickness ranging from about 100 to 1000 Angstroms. In one embodiment, the dielectric material is parylene F, aromatic fluorinated VT-4, parylene HT®, or other fluorinated parylene-based films.

The coating material of this embodiment can withstand higher temperatures than known passivation systems using parylene C, D, or N, so that even when exposed to the extreme temperature conditions, the coating material may not rapidly deteriorate. Additional assembly level dielectric layer (s) may also add additional protection for the active device area. By proper selection of the thickness of the first protective dielectric layer 150 applied at the wafer level of manufacture in conjunction with the second protective dielectric layer 156 and / or by appropriate selection of the third dielectric layer 158 applied at the assembly level of fabrication, The passivation of the board assembly 160 may be tailored to suit many kinds of applications.

Also, a first protective dielectric layer 150, formed from alumina, tantalum oxide, beryllium oxide, hafnium oxide, or high density silicon nitride, and silicon dioxide and the nanolaminate of these materials, The dielectric constant is controlled by controlling the thickness of the layer or other suitable material and can delay the growth of tin whiskers, an inherent problem associated with the use of low-lead solder formulations. Tin whisker growth was associated with the presence of moisture and stress conditions that could be exacerbated by moisture.

6 shows a series of operations that may be performed to fabricate one embodiment of circuit device 160 shown and described above with respect to Figs. 5A and 5B. At operation 200, a method of providing an electrically environmentally protective coating system is disclosed. At operation 202, one or more electrical components 146 may be formed on the substrate 142 using known integrated circuit fabrication techniques. In operation 204, a first protective dielectric layer 150 and / or a second protective dielectric layer 156 may be deposited on the substrate 142 and the electrical component 146. Operations 202 and 204 describe measures that may be performed during the wafer level fabrication step.

Operations 206 through 214 describe the actions that can be performed during the assembly-level fabrication steps. At operation 206, a circuit device 142 may be attached to the circuit board 161. At operation 208, one or more assembly level structures, such as one or more discrete electrical components 164 and / or 170, and / or interconnect 166, may be formed on the circuit board 161. Other circuit structures, such as perimeters or die edges, may also be formed on the circuit device 140.

Next, at operation 210, on each of the first protective dielectric layer 150 and / or the second protective dielectric layer 156, and on any of the individual electrical components or assembly level structures that were formed on the circuit board assembly 160 A second protective dielectric layer 156, and / or a third dielectric layer 158 may be deposited. In one embodiment, the second protective dielectric layer 150 or the third dielectric layer 158 may be made of a dielectric material, and in certain embodiments may be parylene F or parylene HT®. In one particular embodiment in which the second protective dielectric layer 156 and / or the third dielectric layer 158 consists of parylene F or parylene HT and is adjacent to an underlying layer of alumina, An adhesion promoter may be applied between the dielectric layer 156 and the third dielectric layer 158. In another embodiment, the adhesion promoter may be a layer of silicon dioxide that is used independently or in conjunction with gamma-methacryloxypropyltrimethoxysilane.

At operation 212, after the method of applying the passivation layer is completed, the circuit board assembly 160 may be used.

7 illustrates a plurality of embodiments 1a to 2c in which various combinations of the first protective dielectric layer 150, the second protective dielectric layer 156, and the third dielectric layer 158 can be applied in the wafer level and assembly level production steps . Embodiments 1a to 2c utilize the first protective dielectric layer 150 formed during the wafer level production step. As described above with respect to FIG. 3, the coating material and method of the first protective dielectric layer 150 are similar to those of Examples 1 to 5 in FIG.

Since the embodiments 1a, 1b, 1c, 1d, and 1e of FIG. 7 have a second protective dielectric layer 156 deposited at the assembly level, the second protective dielectric layer 156 may be added or modified during assembly- Level structure. ≪ RTI ID = 0.0 > Examples of assembly level structures that can be added or modified at the assembly level include processing of the substrate 142, addition of circuit board components 164 and 170, and formation of interconnections 166.

Example 1a shows a second protective dielectric layer 156 made of alumina. The application of the second protective dielectric layer 156 at the assembly level can provide improved environmental protection compared to known organic dielectrics, thereby minimizing the dielectric loading effect for components added at the assembly level . This effect becomes increasingly important as the operating frequency increases to microwave and millimeter wave frequencies.

Example 1b utilizes a second protective dielectric layer 156 comprising parylene F or parylene < RTI ID = 0.0 > HT < / RTI & In this particular embodiment, an adhesion promoter may be applied prior to application of the second protective dielectric layer 156. Example 1b can provide a relatively small electrical impact on the operation of circuit board assembly 160 due to the low dielectric constant of parylene F or parylene < RTI ID = 0.0 > HT. ≪ / RTI > Example 1c utilizes a second protective dielectric layer 156 made of silica without a third dielectric layer 158. [

Example Id utilizes a second protective dielectric layer 156 of alumina having a third dielectric layer of parylene F or parylene < RTI ID = 0.0 > HT. ≪ / RTI > As discussed above, the alumina layer is particularly useful when used in conjunction with an adhesion promoter such as a layer of silicon dioxide used in conjunction with gamma-methacryloxypropyltrimethoxysilane or in combination with the circuit assembly 160 and parylene < RTI ID = 0.0 > F or parylene < RTI ID = 0.0 > HT. ≪ / RTI >

Examples 2a, 2b, and 2c have a first protective dielectric layer 150 and a second protective dielectric layer 156 applied at the wafer level of production and a third dielectric layer 158 applied at the assembly level. Certain embodiments using this process can offer the advantage that devices can be electrically measured at the wafer level and only known good die is provided for the assembly level.

Still another embodiment of the disclosure is a method of manufacturing a semiconductor device, such as a conventional CVD (Chemical Vapor Deposition), ECR PECVD (Electron Cyclotron Resonance Plasma Enhanced CVD), ICPECVD (Inductively Coupled Plasma Enhanced CVD), HDICPCVD (High Density Inductively Coupled Plasma Chemical Vapor Deposition) Deposited by techniques known in the art including magnetron sputtering, high density plasma enhanced CVD techniques including hot wire CVD using hydrogen free precursor gases or deposition by PECVD And a relatively thin initial layer having a high density (greater than 2.5 gm / cm3) and / or a low hydrogen content silicon nitride or silicon dioxide film (less than 15 atomic%). High density and / or low hydrogen content silicon nitride may have inherently higher breakdown voltage and moisture penetration resistance. The selection of conventional CVD or high density plasma CVD techniques may be based on the device structure of the circuit board assembly. This initial layer of silicon nitride or silicon dioxide has been well developed and characterized in the industry to reduce charge trap and other surface interface defects. The thicker the first protective dielectric layer deposited on the initial silicon nitride or silicon dioxide layer, the better the performance and protection described above. An example of such an embodiment is shown in Fig.

FIG. 8 is an enlarged view of component 216, where in this particular case component 216 is a Field Effect Transistor (FET). The component 216 has a source 216s, a gate 216g, and a drain 216d that are separated from each other by an air gap 217. To achieve good performance, the air gap 217 is maintained by the design of the gate recess and gate geometry along with the protective dielectric layer 222 and the thin initial layer 221 of silicon nitride. As shown, the combined thickness of the first protective dielectric layer 222 and the thin initial layer 221 maintains the air gap 17 such that the inter-node capacitances Cgs and Cgd can be reduced. In one particular embodiment, this passivation layer comprises a thin layer 221 of silicon nitride in the range of 25 to 400 Angstroms and a low permeability layer 222 of amorphous alumina having a thickness in the range of 50 to 2000 Angstroms. The first dielectric layer 222 may also be formed of any of the same materials as the first protective dielectric layer 22 as described above.

Silicon nitride has proved to be a relatively good and well-characterized dielectric for microwave devices in device stability. Alumina was also found to be a relatively good dielectric for moisture permeability and breakdown voltage. The combination of these two materials having suitable thickness and physical properties as described in this disclosure can lead to an improved passivation system for known passivation systems. In one embodiment, a thin layer of silicon nitride may be used as the nano-laminate. The nano-laminate may comprise alternating layers of alumina and silicon dioxide, alumina and parylene F, aromatic fluorinated VT-4, parylene HT®, or other fluorinated parylene-based membranes, or alumina and acrylic. In yet another embodiment, the nano-laminate may comprise alternating layers of alumina, vapor-deposited Teflon (PFTE) and acrylic monomers.

Silicon nitride, silicon dioxide, and alumina have low dielectric constants when deposited with atomic layer deposition, especially at relatively low temperature conditions. The low dielectric constant further minimizes the inter-node capacitance and performance variations between the coated and uncoated devices, and leads to improvements in high frequency performance.

Other materials may be substituted for those shown in Figures 1 to 8 in accordance with the teachings of this disclosure. Other protective dielectric materials that may be suitable for such applications include, but are not limited to, standard density silicon nitride, high density silicon nitride, tantalum oxide, and beryllium oxide, hafnium oxide.

While this disclosure has been described in terms of several embodiments, numerous alternatives, modifications, variations, adaptations, and modifications may be suggested to one of ordinary skill in the art, Modifications, variations, adaptations, and adaptations are intended to be encompassed within the concept and scope of the appended claims.

Claims (38)

A method of manufacturing an integrated circuit, Providing a substrate having a substrate surface; Forming an electrical component comprising at least a transistor or a capacitor on the substrate surface; Coating the substrate surface and the electrical component with a first protective dielectric layer comprised of alumina, the first protective dielectric layer having a thickness in the range of about 50 to 2000 Angstroms; Etching a portion of the first protective dielectric layer from the substrate surface or the electrical component to form a contact surface; Forming an air bridge on the contact surface; Coating the first protective dielectric layer, the electrical component, and the air bridge with a second protective dielectric layer comprised of alumina, the second protective dielectric layer having a thickness in the range of about 50 to 2000 Angstroms; Applying an adhesion promoter to the second protective dielectric layer; And Coating said second protective dielectric layer with a third dielectric layer comprised of a material selected from the group consisting of alumina, silica, parylene F, aromatic-fluorinated VT-4, and parylene HT The third dielectric layer has a thickness in the range of about 100 to 1000 angstroms; / RTI > The method according to claim 1, Wherein the step of applying the adhesion promoter comprises applying an adhesion promoter comprising a layer of silicon dioxide that is used independently or in conjunction with gamma-methacryloxypropyltrimethoxysilane. Gt; The method according to claim 1, The step of providing the substrate may be performed in a group consisting of silicon (Si), gallium arsenide (GaAs), gallium-nitride (GaN), germanium, silicon carbide (SiC), and indium phosphide RTI ID = 0.0 > 1, < / RTI > providing a substrate made of a selected material. A method of manufacturing a circuit device, Providing a substrate having a substrate surface; Forming an electrical component on the substrate surface; And The substrate surface and the electrical ^{component, 0.01 g / m 2 / day} (gram / meter 2 / day) than the small moisture permeability (moisture permeability), a small water absorption than 0.04% (moisture absorption), a dielectric constant greater than 10, Insoluble material having a dielectric loss of less than 0.005, a breakdown voltage strength of greater than 8,000,000 V / cm, and a sheet resistivity of greater than 10 ¹⁵ ohm-centimeters. Coating with a protective dielectric layer ≪ / RTI > 5. The method of claim 4, Wherein coating the substrate surface and the electrical component with a first protective dielectric layer further comprises coating the substrate surface and the electrical component with a first protective dielectric layer of alumina. 6. The method of claim 5, Coating the substrate surface and the electrical component with a first protective dielectric layer of alumina comprises coating the substrate surface and the electrical component with a first protective dielectric layer of alumina in the range of 50 to 2000 Angstroms / RTI > 5. The method of claim 4, Wherein the step of coating the substrate surface and the electrical component with the first protective dielectric layer comprises depositing a first layer of silicon nitride, tantalum-oxide, beryllium-oxide, hafnium-oxide, And coating the substrate surface and the electrical component with a first protective dielectric layer selected from the group consisting of Al2O3, Al2O3, and Al2O3. 5. The method of claim 4, Etching a portion of the first protective dielectric layer from the substrate surface or the electrical component to form a contact surface; Forming an additional component on the contact surface; And Coating the first protective dielectric layer, the electrical component, and the additional component with a second protective dielectric layer ≪ / RTI > 9. The method of claim 8, Wherein the second protective dielectric layer has a modulus of elasticity less than 3.5 GPa, a dielectric constant less than 3.0, a dielectric loss less than 0.008, a breakdown voltage greater than 2 MV / cm (million volts / centimeter) Strength, temperature stability up to 3000 ° C, pinhole free of membranes greater than 50 Å, hydrophobic with wetting angles greater than 45 °, and thicknesses less than 30% A method of fabricating a circuit device comprising a dielectric material that can be deposited conformally above and below a 3D structure with uniformity. 9. The method of claim 8, Wherein the second protective dielectric layer is selected from the group consisting of alumina, silica, parylene F, aromatic fluorinated VT-4, parylene HT®, acrylic, and vapor deposited polytetrafluoroethylene (PTFE) ≪ / RTI > 9. The method of claim 8, The second protective dielectric layer may comprise at least one of alumina, silicon dioxide, beryllium oxide, hafnium oxide, tantalum oxide, parylene F or parylene HT®, aromatic fluorinated VT-4, acrylic, and vapor deposited Teflon (PTFE) ≪ / RTI > wherein the nano laminate is a nano laminate. 9. The method of claim 8, And coating the second protective dielectric layer with a third dielectric layer. 13. The method of claim 12, Wherein coating the second protective dielectric layer with a third dielectric layer comprises coating the second protective dielectric layer with a third dielectric layer comprised of parylene. 13. The method of claim 12, Wherein coating the second protective dielectric layer with a third dielectric layer comprises coating the second protective dielectric layer with a third dielectric layer comprised of silica. 13. The method of claim 12, The step of coating the second protective dielectric layer with a third dielectric layer comprises coating the second protective dielectric layer with a third dielectric layer comprising alumina, silica, parylene F, aromatic fluorinated VT-4, and parylene HT & ≪ / RTI > further comprising the step of: 13. The method of claim 12, Wherein the step of coating the second protective dielectric layer with a third dielectric layer further comprises the step of coating the second protective dielectric layer with at least one of alumina, silicon dioxide, beryllium oxide, hafnium oxide and silica, tantalum oxide and silica, alumina and parylene F, Further comprising coating with a third dielectric layer comprised of a nano-laminate comprising alternating combinations of alumina and acrylic, and nano-laminate material selected from the group consisting of alumina and vapor-deposited teflon (PTFE). 16. The method of claim 15, The step of coating the second protective dielectric layer with a third dielectric layer comprising alumina, silica, parylene F, aromatic fluorinated VT-4, and parylene < RTI ID = 0.0 > Further comprising coating a third dielectric layer made of alumina, tantalum oxide, beryllium oxide, hafnium oxide, or silicon nitride. 13. The method of claim 12, Further comprising applying an adhesion promoter to the second protective dielectric layer prior to coating the second protective dielectric layer with a third dielectric layer. 19. The method of claim 18, Wherein applying the adhesion promoter comprises applying an adhesion promoter consisting of a layer of silicon dioxide that is used independently or in conjunction with gamma-methacryloxypropyltrimethoxysilane. 5. The method of claim 4, Further comprising applying an initial layer of silicon nitride or silicon dioxide onto the substrate surface and the electrical component prior to coating the substrate surface and the electrical component with a first protective dielectric layer, Wherein the layer has a thickness in the range of 25 to 400 angstroms. 5. The method of claim 4, Wherein forming the electrical component comprises forming at least a transistor or a capacitor on the substrate. 9. The method of claim 8, Wherein forming the additional component comprises forming an air bridge on the substrate surface or the electrical component. As a circuit device, A substrate having a substrate surface; At least one electrical component formed on the substrate; And A first protective dielectric layer formed on the at least one electrical component, / RTI > Wherein the first protective dielectric layer has a water permeability of less than 0.01 g / m ² / day, a water absorbency of less than 0.04%, a dielectric constant of less than 10, a dielectric loss of less than 0.005, a breakdown voltage strength of greater than 8,000,000 V / A circuit device comprising a generally water-insoluble material having a sheet resistance greater than ¹⁵ ohm-cm. 24. The method of claim 23, Wherein the first protective dielectric layer is made of alumina. 24. The method of claim 23, Wherein the first protective dielectric layer is about 50 to 2000 Angstroms thick. 24. The method of claim 23, Wherein the first protective dielectric layer is made of any one material selected from the group consisting of high density silicon nitride, tantalum oxide, beryllium oxide, hafnium oxide, and alumina. 24. The method of claim 23, Further comprising at least one additional component formed on the substrate or on the at least one electrical component and a second protective dielectric layer formed on the substrate surface, the first protective dielectric layer, and the at least one additional component Lt; / RTI > 28. The method of claim 27, Wherein the second protective dielectric layer comprises at least one of alumina and silicon dioxide, beryllium oxide and silica, beryllium oxide and parylene F or parylene HT®, alumina and fluorinated parylene, alumina and acrylic, alumina and vapor deposited PTFE, ≪ / RTI > wherein the nano-laminate is a nano-laminate. 28. The method of claim 27, And a third dielectric layer formed on the second protective dielectric layer. 30. The method of claim 29, And the third dielectric layer comprises parylene. 30. The method of claim 29, And the third dielectric layer comprises alumina, tantalum oxide, beryllium oxide, hafnium oxide, or silicon nitride. 24. The method of claim 23, Further comprising an initial layer between the substrate surface and the first protective dielectric layer, Wherein the initial layer is selected from the group consisting of silicon nitride and silicon dioxide. 24. The method of claim 23, Further comprising a thin silicon nitride layer disposed between the first protective dielectric layer and the substrate surface and the electrical component, Wherein the thin silicon nitride layer has a thickness in the range of 25 to 400 angstroms. 24. The method of claim 23, Wherein the at least one electrical component is selected from the group consisting of a transistor and a capacitor. 28. The method of claim 27, Wherein the additional component is an air bridge. 24. The method of claim 23, And an adhesion promoter between the first protective dielectric layer and the second protective dielectric layer. 37. The method of claim 36, Wherein the adhesion promoter is gamma-methacryloxypropyltrimethoxysilane. 24. The method of claim 23, Further comprising an initial layer of silicon nitride or silicon dioxide between the substrate surface and the first protective dielectric layer, Wherein the initial layer of silicon nitride or silicon dioxide has a thickness in the range of 25 to 400 angstroms.

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