KR101449133B1 - Low Dropout Voltage Regulator of having Multiple Error AMPs - Google Patents

Abstract

A low dropout voltage regulator having frequency selectivity for variations in the output signal is disclosed. Two error amplifiers are arranged in the path where the feedback voltage is input and compared with the reference voltage and amplified. Error amplifiers are placed in parallel with each other and have different gains and bandwidths. The gain of the first error amplifier is smaller than that of the second error amplifier, and has a wide bandwidth. Therefore, the first error amplifier mainly performs the fast response characteristic and the amplification action with respect to the high frequency component of the output signal. In addition, the second error amplifier can perform a quick regulation operation of the output signal through a high gain with respect to the low frequency component of the output signal.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a low dropout voltage regulator having a plurality of error amplifiers,

The present invention relates to a voltage regulator, and more particularly to a voltage regulator in which the signal path is divided into at least two.

2. Description of the Related Art Recently, battery-based portable electronic devices such as smart phones and MP3s have been rapidly spreading, and power management circuits have been required to be made more versatile and sophisticated. Therefore, the importance of PMIC (Power Management IC), which is a circuit for managing limited battery power and using it as various types of power sources, is increasing.

The PMIC is essential to reduce the standby power of handheld devices such as cellular phones or PDAs. There are two main types of PMICs. The first is a low dropout voltage regulator that is a linear regulator, and the second is a switching mode power supply (SMPS), a switching regulator. Linear regulators have fast response characteristics and low noise, but have relatively low efficiency. On the other hand, a switching regulator has a high efficiency, but an external device is used and the noise transmitted to the load is large. Therefore, a linear regulator is widely used in an analog system for achieving high performance.

1 is a block diagram illustrating a low dropout voltage regulator in accordance with the prior art.

Referring to FIG. 1, a low dropout voltage regulator has a reference voltage generator 100, an error amplifier 110, a pass element 120, and a voltage divider 130.

The reference voltage Vref generated in the reference voltage generator 100 is applied to the negative input terminal of the error amplifier 110. A feedback voltage Vfb divided by the voltage divider 130 is applied to the positive input terminal of the error amplifier 110. [ The error amplifier 110 amplifies the difference between the voltages applied to the two input terminals and applies the amplified difference to the pass element 120.

The pass element 120 may be a pass transistor and may be a PMOS transistor. For example, the source terminal of the PMOS pass transistor is connected to the positive power supply voltage, and the output terminal of the error amplifier 110 is applied to the gate terminal. Further, an output voltage Vout is generated at the drain terminal, and a voltage divider 130 is connected.

If the output voltage Vout falls due to various factors in the load 140, which is an impedance component of the output stage, the feedback voltage Vfb decreases due to the resistors R1 and R2 provided in the voltage divider 130. [ The reduced feedback voltage Vfb is applied to the error amplifier 110 and the error amplifier 110 controls the pass element to increase the current flowing through the voltage divider 130. [ Therefore, the output voltage Vout rises by the two resistors R1 and R2 provided in the voltage divider 130. [

Similarly, when the output voltage Vout rises due to various factors, the feedback voltage Vfb formed in the voltage divider 130 increases. The error amplifier 110 receiving the feedback voltage Vfb applies the output voltage to the pass element 120 and the pass element 120 reduces the amount of current supplied to the voltage divider 130. [ Thus, the voltage divider 130 drops the output voltage Vout.

Through the above-described operation, the fluctuation of the output voltage Vout is minimized, and the low dropout voltage regulator maintains a constant level of the output voltage Vout.

In order for the above-described regulation operation to be implemented, the error amplifier must have high gain and wide bandwidth. Therefore, depending on the specifications of the error amplifier to be used, the amount of power consumed by the low dropout voltage regulator is relatively high, and various problems arise due to low energy efficiency.

In addition, there arises a problem that the regulation operation can not be performed smoothly due to the noise component generated by the load or the like.

SUMMARY OF THE INVENTION The present invention is directed to a low dropout voltage regulator having a plurality of error amplifiers capable of selectively performing an amplification operation on a variation of an output signal.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a reference voltage generator for forming a reference voltage; A first error amplifier for receiving the reference voltage through a negative input terminal, receiving a feedback voltage via a positive input terminal and amplifying a difference between the feedback voltage and the reference voltage; And a second error amplifier for receiving the reference voltage through a negative input terminal and receiving the feedback voltage through a positive input terminal to amplify the difference between the feedback voltage and the reference voltage, A second error amplifier; A path element for generating a drive current according to an output signal of the first error amplifier and the second error amplifier, to which an output signal of the first error amplifier and the output terminal of the second error amplifier are connected in common; And a voltage divider for forming an output signal according to the drive current and generating the feedback voltage through a resistor connection, wherein the first error amplifier has a voltage gain lower than the second error amplifier, And has a wider bandwidth than the error amplifier.

According to the present invention, two error amplifiers are disposed in the feedback path of the low dropout regulator. Depending on the harmonic components due to variations in the output signal, the two error amplifiers selectively perform the dominant amplification operation. Therefore, the problem of employing only one error amplifier and performing an amplification operation irrespective of the frequency component to increase the consumed power is solved. Thus, the power consumption is reduced through the selective amplification operation.

In addition, a variation in the output signal can be rapidly entered into a steady state through the selective amplification operation according to the bandwidth, thereby enabling an efficient regulation operation to be performed.

1 is a block diagram illustrating a low dropout voltage regulator in accordance with the prior art.
2 is a block diagram illustrating a low dropout voltage regulator in accordance with a preferred embodiment of the present invention.
3 is a circuit diagram showing the first error amplifier of FIG. 2 according to a preferred embodiment of the present invention.
4 is a circuit diagram showing the second error amplifier of FIG. 2 according to a preferred embodiment of the present invention.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example

2 is a block diagram illustrating a low dropout voltage regulator in accordance with a preferred embodiment of the present invention.

Referring to FIG. 2, the low dropout voltage regulator has a reference voltage generator 200, a first error amplifier 210, a second error amplifier 220, a pass element 230, and a voltage divider 240.

The reference voltage generator 200 generates the reference voltage Vref and supplies it to the negative input terminals of the first error amplifier 210 and the second error amplifier 220.

The first error amplifier 210 receives the reference voltage Vref through the negative input terminal and receives the feedback voltage Vfb through the positive input terminal. The output of the first error amplifier 210 is applied to the path element 230. The output signal of the first error amplifier 210 applied to the path element 230 determines the drive current Idr flowing through the path element 230. For example, when the pass element 230 is composed of a PMOS pass transistor, the output signal of the first error amplifier 210 is applied to the gate terminal of the pass transistor. The drive current Idr of the pass element in the pass transistor is determined according to the output signal of the first error amplifier 210 applied to the gate terminal.

The second error amplifier receives the reference voltage Vref of the reference voltage generator 200 through the negative input terminal and receives the feedback voltage Vfb through the positive input terminal. Therefore, the reference voltage Vref is commonly applied to the first error amplifier 210 and the negative input terminal of the second error amplifier 220, and the feedback voltage Vfb is applied to the first error amplifier 210 and the second error amplifier 220 And is commonly applied to positive input terminals. Also, the output signal of the second error amplifier 220 is applied to the path element 230. That is, the output terminals of the first error amplifier 210 and the second error amplifier 220 are commonly connected to each other and applied to the path element 230. For example, when the pass element 230 is formed of a pass transistor, the output signals of the first error amplifier 210 and the second error amplifier 220 are commonly applied to the gate terminal of the pass transistor provided as a PMOS type.

Assuming that the voltage gain of the first error amplifier 210 is A1, the second error amplifier 220 has a voltage gain of A2 greater than A1. Assuming that the bandwidth of the first error amplifier 210 is BW1, the second error amplifier 220 has BW2 smaller than BW1. The second error amplifier 220 having a relatively small bandwidth BW2 has a slower response speed than the first error amplifier 210. [ Therefore, the first error amplifier 210 performs a quick response to the variation of the output signal Vout compared to the second error amplifier 220. [

For example, when the output signal Vout and the reference voltage Vref are in a steady state and the two error amplifiers 210 and 220 operate in the common mode, the reference voltage Vref and the feedback voltage Vfb maintain the same level due to the virtual short. If the output signal Vout rises as compared with the steady state, the first rising state has a high frequency harmonic component. Therefore, the first error amplifier having a wide bandwidth can perform an operation with a predetermined voltage gain. In addition, the voltage gain of the second error amplifier 220 is very low due to the high frequency harmonic components. Therefore, in the rising state of the first output signal Vout, the first error amplifier 210 performs the amplifying operation with the voltage gain of A1. Therefore, the driving current Idr generated in the pass element 230 decreases. As the driving current Idr decreases, the output voltage Vout falls toward the steady state output signal Vout.

Subsequently, in a state in which the output signal Vout falls, the output signal Vout has a harmonic component of a low frequency. The second error amplifier 220 has a higher voltage gain than the first error amplifier 210 in the lower frequency band. Therefore, the feedback voltage Vfb quickly follows the reference voltage Vref by the operation of the second error amplifier 220. [ The phenomenon that the feedback voltage Vfb follows the reference voltage Vref is caused not by the response speed of the second error amplifier 220 but by the second error amplifier 220 having a high voltage gain. That is, when the voltage gain is very high, the voltage of the output terminal facilitates the configuration of the input terminal and the virtual short circuit. Therefore, the feedback voltage Vfb easily follows the reference voltage Vref, and the fluctuation of the output signal Vout is minimized and quickly enters the steady state.

That is, in the initial stage of the fluctuation of the output signal Vout, the first error amplifier 210 performs a main amplifying operation to participate in the regulation operation, and thereafter, the second error amplifier 220 performs an amplifying operation with a high gain And performs a regulating operation.

3 is a circuit diagram showing the first error amplifier of FIG. 2 according to a preferred embodiment of the present invention.

Referring to FIG. 3, the first error amplifier has a first bias portion 211, a second bias portion 212, an input stage 213, and an output stage 214. The first error amplifier has a rail-to-rail structure disposed between a positive power supply voltage VDD and a negative power supply voltage VSS. Also, the negative power supply voltage VSS may be a ground level.

The first bias unit 211 forms a bias current through the reference bias current source Iref. The formed bias current flows through transistors MP1 and MP3. Also, the transistors MP2 and MP4 are copied to the flowing current through the current mirroring operation. The bias voltage of the first node N1 in which the gate terminals of the transistors MP1 and MP2 are commonly connected in the current mirroring process is set and the bias voltage of the second node N2 in which the gate terminals of MP3 and MP4 are commonly connected is also set.

A bias current copied from MP2 and MP4 flows to the transistor MN1 of the second bias unit 212. [ This determines the bias current flowing through the MPX through the transistors MN1 and MN2 having the current mirror configuration, and the voltage at the gate terminal of the transistor MPX is also determined.

The voltage of the gate terminal of the transistor MP5 of the second bias unit 212 is equal to the bias voltage of the first node N1 of the first bias unit 211. [ Whereby the bias current flowing through transistor MP5 is determined. Also, the voltage of the second node N2 is applied to the gate terminal of the transistor MP6. Whereby the voltage at the drain terminal of transistor MP5 or the voltage at the source terminal of MP6 can be determined. Further, the bias current generated in MP5 flows through transistors MN3 and MN4, and the gate voltages of transistors MN3 and MN4 are determined.

The bias current of the input stage 213 is determined by the voltage of the first node N1 of the first bias unit 211 and the voltage of the second node N2. This means that the bias current of the input stage 213 is determined by the voltage generated in the first bias section 211. [ The voltage of the first node N1 is applied to the gate terminal of the transistor MP7 and the voltage of the second node N2 is applied to the gate terminal of the transistor MP8. The current flowing through MP7 is determined by the voltage at the first node N1 applied to the gate terminal of MP7. Further, the voltage of the source terminal of MP8 is determined by the bias current flowing through MP7. The bias current flowing through the formed MP7 and MP8 flows to the transistors MP16 and MP17, respectively, and flows to the transistors MN7 and MN8.

Further, the current flowing through the MN7 of the output stage 214 is equal to the current flowing through the transistor MP16, and the current flowing through the MN8 is equal to the current flowing through the transistor MP17. The gate terminal voltages of the transistors MN7 and MN8 which are commonly connected by the bias current flowing through the respective transistors are determined. The bias current flowing through the transistors MP8, MP10 and MN5 is also determined by the voltage at the gate terminal of the transistor MPX of the second bias section 212 and the voltage at the gate terminals of the transistors MN3 and MN4 of the second bias section 212 . Therefore, the bias current flowing through the transistor MN7 is the sum of the bias current flowing through the transistor MP16 of the input stage 213 and the bias current flowing through the transistor MN5, and the voltage at the gate terminal of the MN7 is determined corresponding to the sum of the currents. This applies equally to the transistors MP11, MP12, MN6 and MN8. As a result, the bias current flowing through the output stage 214 is determined by the gate voltage of the transistors formed in the second bias portion 212.

A positive input signal INP and a negative input signal INN are applied to the input stage 213. A positive input signal INP is applied to the gate terminal of the transistor MP16 and a negative input signal INN is applied to the gate terminal of the transistor MP17. Transistors MP16 and MP17 serve as a common source amplifier. In other words, it acts as a common source amplifier for small signal inputs in differential mode.

The output signal of MP16 is applied to the source terminal of transistor MN5. MN5 takes the configuration of a common gate amplifier. The signal amplified in the common gate amplifier is applied to the gate terminal of the transistor MN8 having the configuration of the common source amplifier, and the signal amplified by the MN8 in the common source amplifier is outputted to the output terminal through the transistor MN6 having the configuration of the common gate amplifier.

The output signal of the MP17 having the configuration of the common source amplifier is applied to the source terminal of the transistor MN6 having the common gate amplifier configuration, amplified and transmitted to the output terminal.

Thus, the positive input signal INP and the negative input signal INN are amplified in the differential mode through the serial configuration of the common source amplifier and the common gate amplifier to form the output signal Vout.

4 is a circuit diagram showing the second error amplifier of FIG. 2 according to a preferred embodiment of the present invention.

4, the second error amplifier has a first bias section 221, a second bias section 222, an input stage 223, a first output stage 224, and a second output stage 225 .

The first bias portion 221, the second bias portion 222, and the input stage 223 are the same as those described in FIG. The first output stage 224 is also the same as the output stage 214 of FIG. 4, the configuration and operation of the second output stage 225 newly added to the configuration of FIG. 3 will be mainly described.

First, the signal at the third node N3, which is the output terminal of the first output stage 224, is applied to the gate terminals of the transistors MP14 and MN9. In particular, transistor MP14 has a common source amplifier configuration in terms of small signal modeling. Therefore, the signal of the third node N3 amplified through the MP14 appears at the drain terminal, which is applied to the gate terminal of the transistor MN12 having the configuration of the common source amplifier. The signal at the gate terminal of MN12, which is the configuration of the common source amplifier, is amplified and appears at the output stage.

Further, the signal at the fourth node N4, which is the gate terminal of the transistor MN8, is applied to the gate terminals of the transistors MN10 and MN11. In particular, MN11 has a configuration of a common source amplifier and amplifies a signal applied to the gate terminal. The amplified signal is formed at the drain terminal, is applied to the gate terminal of the transistor MN12 having the configuration of the common source amplifier, amplified and appears at the output terminal.

Therefore, the signal of the third node N3 and the signal of the fourth node N4 are amplified by the common source amplifiers connected in series in two stages to form the output signal Vout.

The first error amplifier 210 shown in FIG. 3 has a keez code configuration in which a common source amplifier and a common gate amplifier are connected in series in terms of small signals. From the viewpoint of the positive input signal INP, the cascode configuration is characterized in that the common source amplifier has a low output impedance or a low effective load resistance, thereby improving the frequency response characteristic. Therefore, it has a wider bandwidth than the second error amplifier 220.

Particularly in terms of the amount of input signal INP, it is understood that the cascode configuration of MP16 and MN5, the cascode configuration of MN8 and MN6, and the cascade configuration of the second stage are connected in series. Further, from the viewpoint of the negative input signal INN, a one-stage cascode configuration of MP17 and MN6 is formed.

The second error amplifier 220 shown in FIG. 4 shows transistors MP16 and MN5 in a cascode configuration in which a common source and a common gate amplifier are connected in series in terms of a positive input signal INP, and is connected to a cascode configuration, The serial structure of the three-stage common source amplifier composed of MN11 and MN12 is shown. Also, in the cascode configuration, a common source amplifier of MN8 and a secondary cascode arrangement of common gate amplifier of MN6 are shown, and MP14 and MN12 show a serial connection configuration of the two-stage common source amplifier.

Further, from the viewpoint of the negative input signal INN of the second error amplifier 220, the cascode configurations MP17 and MN6 are formed, and transistors MP14 and MN12, which are two-stage common source amplifier configurations connected in series to the cascade, are formed.

As a result, the second error amplifier 220 is formed in a simplistic manner in which at least two stages of common source amplifiers are connected in series in the cascode configuration. Therefore, a higher gain than that of the first error amplifier 210 of FIG. 3 is realized. However, the frequency characteristic is reduced compared to the first error amplifier 210 due to the common source amplifier connected in series with the cascode configuration. Therefore, the second error amplifier 220 has a narrow bandwidth compared to the first error amplifier 210. [

The two error amplifiers are arranged in parallel and provide different voltage gains in different frequency bands. That is, in the high frequency band, the first error amplifier performs a predominant operation and performs an amplification operation to minimize the fluctuation of the output stage quickly. Also, in the low frequency band, the second error amplifier performs a predominant operation, and a regulation operation that minimizes the variation of the output stage through an amplifying operation having a relatively high gain can be performed.

In the present invention described above, two error amplifiers are arranged in the feedback path of the low-dropout regulator. Depending on the harmonic components due to variations in the output signal, the two error amplifiers selectively perform the dominant amplification operation. Therefore, the problem of employing only one error amplifier and performing an amplification operation irrespective of the frequency component to increase the consumed power is solved. Thus, the power consumption is reduced through the selective amplification operation.

In addition, a variation in the output signal can be rapidly entered into a steady state through the selective amplification operation according to the bandwidth, thereby enabling an efficient regulation operation to be performed.

200: reference voltage generator 210: first error amplifier
220: second error amplifier 230: pass element
240: Voltage distribution portion

Claims (5)

A reference voltage generator for forming a reference voltage;
A first error amplifier for receiving the reference voltage through a negative input terminal, receiving a feedback voltage via a positive input terminal and amplifying a difference between the feedback voltage and the reference voltage;
And a second error amplifier for receiving the reference voltage through a negative input terminal and receiving the feedback voltage through a positive input terminal to amplify the difference between the feedback voltage and the reference voltage, A second error amplifier;
A path element for generating a drive current according to an output signal of the first error amplifier and the second error amplifier, to which an output signal of the first error amplifier and the output terminal of the second error amplifier are connected in common; And
And a voltage distributor for forming an output signal according to the drive current and generating the feedback voltage through a resistor connection,
Wherein the first error amplifier has a voltage gain lower than that of the second error amplifier and has a bandwidth greater than that of the second error amplifier and the first error amplifier and the second error amplifier operate simultaneously when the output signal changes, Characterized in that the first error amplifier performs a dominant amplification operation for the high frequency harmonic component at the beginning and the second error amplifier performs the dominant amplification operation for the low frequency harmonic component of the output signal Low dropout voltage regulator. The apparatus of claim 1, wherein the first error amplifier comprises:
A first bias portion for determining a voltage of gate terminals of transistors performing a current mirroring operation by a reference bias current source;
A second bias unit for performing a biasing operation according to a bias current copied from the first bias unit;
An input stage for receiving a positive input signal and a negative input signal, receiving a bias voltage from the first bias portion, and amplifying the positive input signal and the negative input signal through a common source amplifier configuration; And
And an output stage for being biased by a voltage set in the second bias portion and connected to the input stage to amplify the output signal to the input stage through a common gate amplifier configuration to generate an output signal Drop-out voltage regulator. 3. The apparatus of claim 2, wherein the output stage comprises:
A transistor for performing a common gate amplification operation on an output signal of an input stage for common gate amplifying the positive input signal to form first cascodes; And
And a second kece code coupled to the first ke code for performing a common source amplification and a common gate amplification operation on the output of the first ke code. 3. The apparatus of claim 2, wherein the output stage comprises:
And a transistor for performing a common gate amplification operation on an output signal of the input stage for common gate amplifying the negative input signal to form a third keic code. 2. The apparatus of claim 1, wherein the second error amplifier comprises:
A first bias portion for determining a voltage of gate terminals of transistors performing a current mirroring operation by a reference bias current source;
A second bias unit for performing a biasing operation according to a bias current copied from the first bias unit;
An input stage for receiving a positive input signal and a negative input signal, receiving a bias voltage from the first bias portion, and amplifying the positive input signal and the negative input signal through a common source amplifier configuration;
A first output stage biased by a voltage set to the second bias portion and coupled to the input stage to amplify the output signal to the input stage through a common gate amplifier configuration to produce an output signal; And
And a second output stage for receiving the output signal of the first output stage and performing an amplification operation through a common source amplifier arrangement connected in series in at least two stages.

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