CN117148911B - Low-noise LDO circuit - Google Patents
Low-noise LDO circuit Download PDFInfo
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- CN117148911B CN117148911B CN202311441008.7A CN202311441008A CN117148911B CN 117148911 B CN117148911 B CN 117148911B CN 202311441008 A CN202311441008 A CN 202311441008A CN 117148911 B CN117148911 B CN 117148911B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
The invention discloses a low noise LDO circuit, which is externally connected with a power supply and an output voltage control module, and comprises: the low-dropout regulator comprises a pre-filter circuit, an LDO module and a post-noise reduction circuit, wherein the pre-filter circuit filters the output voltage of a power supply to generate positive and negative voltages which are supplied to the LDO module; the LDO module receives the control of the output voltage control module and outputs a first direct-current voltage; the post noise reduction circuit filters the noise of the first direct current voltage and outputs a second direct current voltage after noise reduction. The invention reduces power consumption and has lower noise.
Description
Technical Field
The invention relates to the technical field of integrated chips, in particular to a low-noise LDO (low dropout linear regulator) circuit for an integrated chip.
Background
In integrated chip circuits, power management chips are responsible for the conversion, distribution, detection, etc. of electrical energy, and in power management chips, low dropout regulators are one of the most widely used, and are used in large numbers in portable systems powered by batteries and in communication-related electronic products. With the continuous increase of signal processing frequency and continuous decrease of power supply voltage of portable electronic devices, the influence of power supply noise on the electronic devices is increasing. Since the output noise of the LDO is directly converted into the power noise of the load circuit, designing a low noise LDO is an important development direction of the LDO.
The conventional low dropout voltage regulator has unstable performance when the load current is greatly changed, and meanwhile, the power consumption of a circuit is increased due to the movement of a zero pole. As shown in fig. 2, the low noise LDO of the integrated chip circuit includes a reference voltage generating circuit BG, an error amplifier OPA, voltage division feedback circuits R1 and R2, a power tube PM1, and an external capacitor C0. The output end of the reference voltage generating circuit is connected with the reverse input end of the error amplifier OP1, the forward input end of the error amplifier OPA is connected with the output feedback voltage Vfb of the voltage division feedback circuit, and the output end of the error amplifier OPA is connected with the control end of the power tube, so that the output voltage VOUT is obtained by controlling the power tube. The noise and the power consumption are high.
Disclosure of Invention
The invention aims to provide a low-noise LDO circuit, which reduces power consumption and has lower noise.
The technical scheme for achieving the purpose is as follows:
a low noise LDO circuit, external power supply and output voltage control module, comprising: a pre-filter circuit, an LDO module and a post-noise reduction circuit,
the pre-filter circuit filters the output voltage of the power supply to generate positive and negative voltages to be supplied to the LDO module;
the LDO module receives the control of the output voltage control module and outputs a first direct-current voltage; the post noise reduction circuit filters the noise of the first direct current voltage and outputs a second direct current voltage after noise reduction;
the LDO module includes: an error amplifier circuit, a first resistor, a second resistor, a third resistor and a fourth resistor;
the error amplifier circuit is connected with positive voltage and negative voltage, a first input end of the error amplifier circuit is connected with a first output end of the output voltage control module through the second resistor, and a second input end of the error amplifier circuit is connected with a second output end of the output voltage control module through the fourth resistor;
the first resistor is connected between the output end and the first input end of the error amplifier circuit;
the third resistor is connected between the output end and the second input end of the error amplifier circuit.
Preferably, the error amplifier circuit includes: the bias module, the rail-to-rail input stage module, the folding current mirror, the output stage module and the filter module,
the bias module is connected with the positive voltage and the negative voltage and provides bias current for the rail-to-rail input stage module;
the rail-to-rail input stage module is connected with positive and negative voltages, receives the output of the output voltage control module, amplifies the output of the output voltage control module for the first stage and transmits the amplified output to the folding current mirror;
the folding current mirror performs second-stage amplification on the input and then transmits the second-stage amplification to the output stage module;
and the output stage module performs the complementary push-pull output of the last stage according to the output of the folding current mirror, and the output voltage forms a first direct-current voltage after passing through the filtering module.
Preferably, the output voltage control module further provides an external reference to the error amplifier circuit.
Preferably, the rail-to-rail input stage module comprises first to fourteenth MOS transistors,
the source electrode of the first MOS tube is connected with a positive voltage, the grid electrode of the first MOS tube is connected with the bias module, and the drain electrode of the first MOS tube is connected with the source electrodes of the second MOS tube and the third MOS tube;
the grid electrode of the second MOS tube is connected with an external reference, and the drain electrode of the second MOS tube is connected with the source electrode of the eleventh MOS tube and the drain electrode of the thirteenth MOS tube;
the grid electrode of the third MOS tube is connected with the second resistor, and the drain electrode of the third MOS tube is connected with the source electrode of the twelfth MOS tube and the drain electrode of the fourteenth MOS tube;
the source electrode of the sixth MOS tube is connected with negative voltage, the grid electrode of the sixth MOS tube is connected with the biasing module, and the drain electrode of the sixth MOS tube is connected with the source electrodes of the fourth MOS tube and the fifth MOS tube;
the grid electrode of the fourth MOS tube is connected with an external reference, and the drain electrode of the fourth MOS tube is connected with the drain electrode of the seventh MOS tube and the source electrode of the ninth MOS tube;
the grid electrode of the fifth MOS tube is connected with the fourth resistor, and the drain electrode of the fifth MOS tube is connected with the drain electrode of the eighth MOS tube and the source electrode of the tenth MOS tube;
the source electrode of the seventh MOS tube is connected with a positive voltage, and the grid electrode of the seventh MOS tube is connected with the drain electrode of the seventh MOS tube;
the source electrode of the eighth MOS tube is connected with a positive voltage, and the grid electrode of the eighth MOS tube is connected with the grid electrode of the seventh MOS tube;
the grid electrode and the drain electrode of the ninth MOS tube are connected;
the grid electrode of the tenth MOS tube is connected with the grid electrode of the ninth MOS tube, and the drain electrode of the tenth MOS tube is connected with the drain electrode of the twelfth MOS tube;
the drain electrode of the eleventh MOS tube is connected with the drain electrode of the ninth MOS tube;
the grid electrode and the drain electrode of the eleventh MOS tube are connected;
the grid electrode of the twelfth MOS tube is connected with the grid electrode of the eleventh MOS tube;
the drain electrode of the thirteenth MOS tube is connected with the grid electrode, and the source electrode of the thirteenth MOS tube is connected with negative voltage;
the source electrode of the fourteenth MOS tube is connected with negative voltage, and the grid electrode of the thirteenth MOS tube is connected with the grid electrode;
the folding current mirror comprises fifteenth to eighteenth MOS tubes, the output stage module comprises nineteenth and twentieth MOS tubes,
the sources of the fifteenth MOS tube, the seventeenth MOS tube and the nineteenth MOS tube are connected with positive voltages, and the sources of the sixteenth MOS tube, the eighteenth MOS tube and the twentieth MOS tube are connected with negative voltages;
the grid electrode of the fifteenth MOS tube is connected with the drain electrode of the eighth MOS tube and the source electrode of the tenth MOS tube, and the drain electrode is connected with the drain electrode of the sixteenth MOS tube;
the grid electrode of the sixteenth MOS tube is connected with the source electrode of the twelfth MOS tube and the drain electrode of the fourteenth MOS tube;
the grid electrode of the seventeenth MOS tube is connected with the drain electrode of the eighth MOS tube and the source electrode of the tenth MOS tube, and the drain electrode is connected with the drain electrode of the eighteenth MOS tube;
the grid electrode of the eighteenth MOS tube is connected with the source electrode of the twelfth MOS tube and the drain electrode of the fourteenth MOS tube;
the grid electrode of the nineteenth MOS tube is connected with the drain electrode of the seventeenth MOS tube;
the grid electrode of the twentieth MOS tube is connected with the drain electrode of the sixteenth MOS tube;
and the connection ends of the drain electrodes of the nineteenth MOS tube and the twentieth MOS tube are connected with the filtering module.
Preferably, the bias module comprises a twenty-first MOS tube and a fifth resistor of the twenty-second MOS tube,
the source electrode of the twenty-first MOS tube is connected with a positive voltage, and the connected end of the grid electrode and the drain electrode is connected with the grid electrode of the first MOS tube;
the source electrode of the twelfth MOS tube is connected with negative voltage, and the connected end of the grid electrode and the drain electrode is connected with the grid electrode of the sixth MOS tube;
and the drain electrode of the twenty-first MOS tube is connected with the drain electrode of the twenty-second MOS tube through a fifth resistor.
Preferably, the pre-filter circuit comprises a first capacitor, a second capacitor and first to eighth switches, wherein,
the input end of the pre-filter circuit is connected with a power supply and is used as a positive voltage output end;
the head end of the serial branch of the first switch and the third switch is connected with the input end of the pre-filter circuit, and the tail end of the serial branch of the first switch and the third switch is grounded;
the head end of the serial branch of the second switch and the fourth switch is grounded, and the tail end of the serial branch of the second switch and the fourth switch is connected with the negative voltage output end;
the head end of the serial branch of the fifth switch and the seventh switch is connected with the input end of the pre-filter circuit, and the tail end of the serial branch of the fifth switch and the seventh switch is grounded;
the head end of the serial branch of the sixth switch and the eighth switch is grounded, and the tail end of the serial branch of the sixth switch and the eighth switch is connected with the negative voltage output end;
one end of the first capacitor is connected with the connecting ends of the first switch and the third switch, and the other end of the first capacitor is connected with the connecting ends of the second switch and the fourth switch;
one end of the second capacitor is connected with the connecting end of the fifth switch and the seventh switch, and the other end of the second capacitor is connected with the connecting end of the sixth switch and the eighth switch.
Preferably, the pre-filter circuit further comprises a front-end capacitor, a back-end capacitor and a back-end resistor, wherein,
one end of the front-end capacitor is connected with the input end of the pre-filter circuit, and the other end of the front-end capacitor is grounded;
one end of the rear end capacitor is connected with the negative voltage output end, and the other end of the rear end capacitor is grounded;
the back-end resistor is connected in parallel with the back-end capacitor.
Preferably, the pre-filter circuit further comprises a controller for controlling on-off of the first to eighth switches.
Preferably, the rear noise reduction circuit adopts a bidirectional filter capacitor stuck in the chip, the bidirectional filter capacitor comprises an upper polar plate, a lower polar plate and an intermediate layer positioned between the upper polar plate and the lower polar plate, and the upper polar plate and the intermediate layer are connected through a silicon dioxide oxide layer; the lower polar plate is connected with the middle layer through a silicon dioxide oxide layer; one end of the bidirectional filter capacitor receives the first direct current voltage, and the other end outputs the second direct current voltage.
The beneficial effects of the invention are as follows: the invention improves on the basis of the traditional low dropout linear voltage regulator, generates positive and negative voltages which can be counteracted on the LDO module through the pre-filter circuit, and reduces the power consumption and has lower noise by matching with the structural design of the LDO module and the post-noise reduction circuit.
Drawings
FIG. 1 is a circuit diagram of a low noise LDO circuit of the present invention;
FIG. 2 is a circuit diagram of a conventional low dropout linear regulator of the prior art;
FIG. 3 is a circuit diagram of a pre-filter circuit of the present invention;
FIG. 4 is a schematic diagram of a control waveform of a pre-filter circuit according to the present invention;
FIG. 5 is a circuit diagram of an LDO module of the present invention;
FIG. 6 is a circuit diagram of an error amplifier circuit in the present invention;
FIG. 7 is a top view of a two-way filter capacitor according to the present invention;
FIG. 8 is a block diagram of a conventional on-chip capacitor of the prior art;
FIG. 9 is a diagram of the location of a bi-directional filter capacitor on an integrated chip in accordance with the present invention;
FIG. 10 is a cross-sectional view of a bi-directional filter capacitor according to the present invention;
FIG. 11 is an equivalent circuit diagram of a bi-directional filter capacitor in the present invention;
FIG. 12 is a state diagram of the frequency and impedance of the bi-directional filter capacitor of the present invention;
FIG. 13 is a diagram showing the noise reduction effect of a conventional structure;
fig. 14 is a diagram showing the noise reduction effect of the present invention.
Detailed Description
The invention will be further described with reference to the accompanying drawings.
Referring to fig. 1, the low noise LDO circuit of the present invention is externally connected with a power supply and an output voltage control module, and includes: the LDO module comprises a pre-filter circuit, an LDO module and a post-noise reduction circuit.
The pre-filter circuit filters the power supply, namely filters the output voltage Vdd of the power supply, generates positive and negative voltages, and supplies the positive and negative voltages to the LDO module. Specifically, as shown in fig. 3, the pre-filter circuit includes a first capacitor CFLY1, a second capacitor CFLY2, and first to eighth switches S1 to S8. Wherein,
the input end of the pre-filter circuit is connected with a power supply and is used as a positive voltage output end to output a positive voltage VDDA. The negative voltage output terminal outputs a negative voltage AVSS.
The head end of the serial branch of the first switch S1 and the third switch S3 is connected with the input end of the pre-filter circuit, and the tail end of the serial branch is grounded. The first end of the serial branch of the second switch S2 and the fourth switch S4 is grounded, and the tail end of the serial branch is connected with the negative voltage output end. The head end of the serial branch of the fifth switch S5 and the seventh switch S7 is connected with the input end of the pre-filter circuit, and the tail end of the serial branch is grounded. The head end of the serial branch of the sixth switch S6 and the eighth switch S8 is grounded, and the tail end is connected with the negative voltage output end. One end of the first capacitor CFLY1 is connected to the connected end of the first switch S1 and the third switch S3, and the other end is connected to the connected end of the second switch S3 and the fourth switch S4. One end of the second capacitor CFLY2 is connected to the connection end of the fifth switch S5 and the seventh switch S7, and the other end is connected to the connection end of the sixth switch S6 and the eighth switch S8.
One end of the front-end capacitor CIN is connected with the input end of the pre-filter circuit, and the other end of the front-end capacitor CIN is grounded. One end of the back-end capacitor COUT is connected with the negative voltage output end, and the other end of the back-end capacitor COUT is grounded. The back-end resistor RLOAD is connected in parallel with the back-end capacitor COUT. The first to eighth switches are turned on and off by a controller (Oscillator).
Phase1 and Phase2 are control signals of the switch, and are generated through non-overlapping clocks, and the controller controls the on-off of the switch according to the control signals.
When the Phase1 signal is generated, the switch S1/S2/S7/S8 is closed, the switch S3/S4/S5/S6 is opened, and the first capacitor CFLY1 is charged through VIN; while the second capacitor CFLY2 supplies current to the subsequent load.
When the Phase2 signal is generated, the switch S1/S2/S7/S8 is opened, the switch S3/S4/S5/S6 is closed, and the second capacitor CFLY2 is charged through VIN; while the first capacitor CFLY1 supplies current to the subsequent load.
Referring to fig. 4, a control waveform of the pre-filter circuit is shown, where IFLY is the charge-discharge current on the capacitor. Vout is the output voltage, i.e., by alternately operating the Phase1, phase2 signals, such that Vout eventually slowly changes to-VIN, as opposed to the input voltage VIN. Namely: VIN and VIN are the positive voltage VDDA and the negative voltage AVSS. So that the positive and negative voltages can be offset on the LDO module. In addition, the first capacitor CFLY1, the second capacitor CFLY2, the front-end capacitor CIN and the back-end capacitor COUT can all play a role in filtering ripple waves.
The LDO module receives the control of the output voltage control module and outputs a first direct current voltage Vout1. The magnitude of the first direct current voltage Vout1 is controlled by the output voltage control module. The post noise reduction circuit performs noise filtering on the first direct current voltage Vout1 and outputs a second direct current voltage Vout2 after noise reduction.
As shown in fig. 5, the LDO module includes: error amplifier circuit OPA1, first resistor R1, second resistor R2, third resistor R3, and fourth resistor R4.
The error amplifier circuit OPA1 is connected to the positive and negative voltages. The first input terminal Vn1 of the error amplifier circuit OPA1 is connected to the first output terminal Vin1 of the output voltage control module through the second resistor R2, and the second input terminal Vn2 is connected to the second output terminal Vin2 of the output voltage control module through the fourth resistor R4. The Vp end of the error amplifier circuit OPA1 is also connected with an output end of the output voltage control module for providing an external reference.
A first resistor R1 is connected between the output end of the error amplifier circuit OPA1 and the first input end Vn 1; a third resistor R3 is connected between the output terminal of the error amplifier circuit OPA1 and the second input terminal Vn 2.
The error amplifier circuit OPA1 comprises a bias module, a rail-to-rail input stage module, a folding current mirror, an output stage module and a filter module.
The bias module is connected with the positive voltage and the negative voltage and provides bias current for the rail-to-rail input stage module. The rail-to-rail input stage module is connected with positive and negative voltages, receives the output of the output voltage control module, amplifies the output of the output voltage control module for the first stage and transmits the amplified output to the folding current mirror. The folding current mirror amplifies the input in the second stage and transmits the amplified input to the output stage module. And the output stage module performs the complementary push-pull output of the last stage according to the output of the folding current mirror, and the output voltage of the output stage module forms a first direct-current voltage after passing through the filtering module.
Specifically, referring to fig. 6, the rail-to-rail input stage module includes first to fourteenth MOS transistors M1 to M14. The folding current mirror comprises fifteenth to eighteenth MOS tubes M15-M18, the output stage module comprises nineteenth MOS tube M19 and twenty-fourth MOS tube M20, and the bias module comprises twenty-first to twenty-fourth MOS tubes MB1-MB4.
The source electrode of the first MOS tube M1 is connected with a positive voltage, the grid electrode is connected with the bias module, and the drain electrode is connected with the respective source electrodes of the second MOS tube M2 and the third MOS tube M3. The grid electrode of the second MOS tube M2 is connected with an external reference, and the drain electrode of the second MOS tube M2 is connected with the source electrode of the eleventh MOS tube M11 and the drain electrode of the thirteenth MOS tube M113. The gate of the third MOS transistor M3 is connected to the second resistor R2, and the drain is connected to the source of the twelfth MOS transistor M12 and the drain of the fourteenth MOS transistor 14. The source electrode of the sixth MOS tube M6 is connected with negative voltage, the grid electrode is connected with the bias module, and the drain electrode is connected with the respective source electrodes of the fourth MOS tube M4 and the fifth MOS tube M5. The grid electrode of the fourth MOS tube M4 is connected with an external reference, and the drain electrode of the fourth MOS tube M7 is connected with the drain electrode of the ninth MOS tube M9. The gate of the fifth MOS tube M5 is connected with the fourth resistor R4, and the drain is connected with the drain of the eighth MOS tube M8 and the source of the tenth MOS tube M10. The source electrode of the seventh MOS tube M7 is connected with positive voltage, and the grid electrode is connected with the drain electrode. The source electrode of the eighth MOS tube M8 is connected with positive voltage, and the grid electrode of the eighth MOS tube M7 is connected with the grid electrode. The grid electrode and the drain electrode of the ninth MOS tube M9 are connected. The gate of the tenth MOS transistor M10 is connected with the gate of the ninth MOS transistor M9, and the drain is connected with the drain of the twelfth MOS transistor M12. The drain electrode of the eleventh MOS tube M11 is connected with the drain electrode of the ninth MOS tube M9. The grid electrode and the drain electrode of the eleventh MOS tube M11 are connected. The grid electrode of the twelfth MOS tube M12 is connected with the grid electrode of the eleventh MOS tube M11. The drain electrode of the thirteenth MOS transistor M13 is connected with the grid electrode, and the source electrode is connected with negative voltage. The source electrode of the fourteenth MOS tube M14 is connected with negative voltage, and the grid electrode of the thirteenth MOS tube M13 is connected with the grid electrode.
The first to fourteenth MOS transistors M1 to M14 are divided into two types, namely a PMOS transistor and an NMOS transistor, and may have a mismatch problem. The specific structure of the rail-to-rail input stage module can effectively reduce the problem of mismatch of the MOS tube.
The sources of the fifteenth MOS transistor M15, the seventeenth MOS transistor M17 and the nineteenth MOS transistor M19 are connected with positive voltages, and the sources of the sixteenth MOS transistor M16, the eighteenth MOS transistor M18 and the twentieth MOS transistor M20 are connected with negative voltages. The gate of the fifteenth MOS transistor M15 is connected to the drain of the eighth MOS transistor M8 and the source of the tenth MOS transistor M10, and the drain is connected to the drain of the sixteenth MOS transistor M16. The grid electrode of the sixteenth MOS tube M16 is connected with the source electrode of the twelfth MOS tube M12 and the drain electrode of the fourteenth MOS tube M14. The grid electrode of the seventeenth MOS tube M17 is connected with the drain electrode of the eighth MOS tube M8 and the source electrode of the tenth MOS tube M10, and the drain electrode is connected with the drain electrode of the eighteenth MOS tube M18. The grid electrode of the eighteenth MOS tube M18 is connected with the source electrode of the twelfth MOS tube M12 and the drain electrode of the fourteenth MOS tube M14. The grid electrode of the nineteenth MOS tube M19 is connected with the drain electrode of the seventeenth MOS tube M17. The grid electrode of the twentieth MOS tube M20 is connected with the drain electrode of the sixteenth MOS tube M16. And the connection ends of the drain electrodes of the nineteenth MOS tube M19 and the twentieth MOS tube M20 are connected with a filtering module. The filtering module adopts the existing common structure, for example, the structure is formed by a resistor RC and a capacitor in the figure, and the resistance value of the resistor RC is small. The interface of the resistor RC and the capacitor serves as the output of the error amplifier circuit OPA 1. The resistor RC may be omitted, and the capacitor may be directly implemented, and the non-grounded terminal of the capacitor may be directly used as the output terminal of the error amplifier circuit OPA 1.
The seventh to fourteenth MOS transistors M7 to M14 have 8 MOSFETs as the first stage of folding common-source common-gate. The fifteenth to eighteenth MOS transistors M15 to M18 are second-stage amplification, and the nineteenth and twentieth MOS transistors M19 and M20 are last-stage complementary push-pull outputs.
The source electrode of the twenty-first MOS tube MB1 is connected with the positive voltage VDDA, and the connected end of the grid electrode and the drain electrode is connected with the grid electrode of the first MOS tube M1. The source electrode of the twenty-second MOS tube MB4 is connected with the negative voltage AVSS, and the connected end of the grid electrode and the drain electrode is connected with the grid electrode of the sixth MOS tube M6. The drain electrode of the twenty-first MOS tube MB1 is connected with the drain electrode of the twenty-second MOS tube MB4 through a fifth resistor R.
The post noise reduction circuit may be an existing common noise reduction circuit, which is not described herein.
In this embodiment, the post noise reduction circuit uses a bidirectional filter capacitor. Referring to fig. 7, the bidirectional filter capacitor includes an upper plate m1, a lower plate m3, and an intermediate layer m2 between the upper plate m1 and the lower plate m3, where the upper plate m1 and the intermediate layer m2 are connected by a silicon dioxide oxide layer. The lower electrode plate m3 and the middle layer m2 are connected through a silicon dioxide oxide layer. One end of the bidirectional filter capacitor receives the first direct current voltage Vout1, and the other end of the bidirectional filter capacitor outputs the second direct current voltage Vout2. And a special structural design is adopted to realize the filtration of high frequency.
Compared with the capacitor c1 between the output pin Vout and gnd pin of the conventional chip, as shown in FIG. 8. The point a and the point b are capacitor pins, and parasitic inductance is increased as the capacitor pins are longer. Point C is the capacitance across the output of the chip and the PCB (printed circuit board) output so that high frequency signals may capacitively couple through from C and not short to ground through capacitance C1.
Fig. 9, 7 and 10 show the bidirectional filter capacitor of the present invention, which is a part of an integrated chip (i.e. the region c2 in the figure), and the upper electrode plate m1 and the lower electrode plate m3 have no pins, so that parasitic inductance is not introduced. Fig. 11 is an equivalent circuit diagram of a bidirectional filter capacitor. Compared with the traditional capacitor structure, the invention reduces the pins of the capacitor, and reduces parasitic inductance. The high frequency signal from Vout1 to Vout2 must pass through the bidirectional filter capacitor of the present invention, and the bidirectional filter capacitor is not bypassed.
The following formula is given:
wherein Z is the impedance mode, R is the resistance,is the impedance of the capacitor and is a function of the impedance of the capacitor,is an inductive impedance, along withThe Z is reduced, the impedance to ground is small, the filtering effect is good, and the noise reduction effect is good.
See fig. 12, which is a state diagram of frequency and impedance.
Fig. 13 and 14 are diagrams showing noise reduction effects of the conventional structure and the structure of the present invention. Where F represents the frequency and A represents the amplitude of the component of noise in frequency.
The above embodiments are provided for illustrating the present invention and not for limiting the present invention, and various changes and modifications may be made by one skilled in the relevant art without departing from the spirit and scope of the present invention, and thus all equivalent technical solutions should be defined by the claims.
Claims (5)
1. The utility model provides a low noise LDO circuit, external power supply and output voltage control module, its characterized in that includes: a pre-filter circuit, an LDO module and a post-noise reduction circuit,
the pre-filter circuit filters the output voltage of the power supply to generate positive and negative voltages to be supplied to the LDO module;
the LDO module receives the control of the output voltage control module and outputs a first direct-current voltage; the post noise reduction circuit filters the noise of the first direct current voltage and outputs a second direct current voltage after noise reduction;
the LDO module includes: an error amplifier circuit, a first resistor, a second resistor, a third resistor and a fourth resistor;
the error amplifier circuit is connected with positive voltage and negative voltage, a first input end of the error amplifier circuit is connected with a first output end of the output voltage control module through the second resistor, and a second input end of the error amplifier circuit is connected with a second output end of the output voltage control module through the fourth resistor;
the first resistor is connected between the output end and the first input end of the error amplifier circuit;
the third resistor is connected between the output end and the second input end of the error amplifier circuit;
the error amplifier circuit includes: the bias module, the rail-to-rail input stage module, the folding current mirror, the output stage module and the filter module,
the bias module is connected with the positive voltage and the negative voltage and provides bias current for the rail-to-rail input stage module;
the rail-to-rail input stage module is connected with positive and negative voltages, receives the output of the output voltage control module, amplifies the output of the output voltage control module for the first stage and transmits the amplified output to the folding current mirror;
the folding current mirror performs second-stage amplification on the input and then transmits the second-stage amplification to the output stage module;
the output stage module performs the complementary push-pull output of the last stage according to the output of the folding current mirror, and the output voltage forms a first direct-current voltage after passing through the filtering module;
the output voltage control module also provides an external reference to the error amplifier circuit;
the rail-to-rail input stage module comprises first to fourteenth MOS transistors,
the source electrode of the first MOS tube is connected with a positive voltage, the grid electrode of the first MOS tube is connected with the bias module, and the drain electrode of the first MOS tube is connected with the source electrodes of the second MOS tube and the third MOS tube;
the grid electrode of the second MOS tube is connected with an external reference, and the drain electrode of the second MOS tube is connected with the source electrode of the eleventh MOS tube and the drain electrode of the thirteenth MOS tube;
the grid electrode of the third MOS tube is connected with the second resistor, and the drain electrode of the third MOS tube is connected with the source electrode of the twelfth MOS tube and the drain electrode of the fourteenth MOS tube;
the source electrode of the sixth MOS tube is connected with negative voltage, the grid electrode of the sixth MOS tube is connected with the biasing module, and the drain electrode of the sixth MOS tube is connected with the source electrodes of the fourth MOS tube and the fifth MOS tube;
the grid electrode of the fourth MOS tube is connected with an external reference, and the drain electrode of the fourth MOS tube is connected with the drain electrode of the seventh MOS tube and the source electrode of the ninth MOS tube;
the grid electrode of the fifth MOS tube is connected with the fourth resistor, and the drain electrode of the fifth MOS tube is connected with the drain electrode of the eighth MOS tube and the source electrode of the tenth MOS tube;
the source electrode of the seventh MOS tube is connected with a positive voltage, and the grid electrode of the seventh MOS tube is connected with the drain electrode of the seventh MOS tube;
the source electrode of the eighth MOS tube is connected with a positive voltage, and the grid electrode of the eighth MOS tube is connected with the grid electrode of the seventh MOS tube;
the grid electrode and the drain electrode of the ninth MOS tube are connected;
the grid electrode of the tenth MOS tube is connected with the grid electrode of the ninth MOS tube, and the drain electrode of the tenth MOS tube is connected with the drain electrode of the twelfth MOS tube;
the drain electrode of the eleventh MOS tube is connected with the drain electrode of the ninth MOS tube;
the grid electrode and the drain electrode of the eleventh MOS tube are connected;
the grid electrode of the twelfth MOS tube is connected with the grid electrode of the eleventh MOS tube;
the drain electrode of the thirteenth MOS tube is connected with the grid electrode, and the source electrode of the thirteenth MOS tube is connected with negative voltage;
the source electrode of the fourteenth MOS tube is connected with negative voltage, and the grid electrode of the thirteenth MOS tube is connected with the grid electrode;
the folding current mirror comprises fifteenth to eighteenth MOS tubes, the output stage module comprises nineteenth and twentieth MOS tubes,
the sources of the fifteenth MOS tube, the seventeenth MOS tube and the nineteenth MOS tube are connected with positive voltages, and the sources of the sixteenth MOS tube, the eighteenth MOS tube and the twentieth MOS tube are connected with negative voltages;
the grid electrode of the fifteenth MOS tube is connected with the drain electrode of the eighth MOS tube and the source electrode of the tenth MOS tube, and the drain electrode is connected with the drain electrode of the sixteenth MOS tube;
the grid electrode of the sixteenth MOS tube is connected with the source electrode of the twelfth MOS tube and the drain electrode of the fourteenth MOS tube;
the grid electrode of the seventeenth MOS tube is connected with the drain electrode of the eighth MOS tube and the source electrode of the tenth MOS tube, and the drain electrode is connected with the drain electrode of the eighteenth MOS tube;
the grid electrode of the eighteenth MOS tube is connected with the source electrode of the twelfth MOS tube and the drain electrode of the fourteenth MOS tube;
the grid electrode of the nineteenth MOS tube is connected with the drain electrode of the seventeenth MOS tube;
the grid electrode of the twentieth MOS tube is connected with the drain electrode of the sixteenth MOS tube;
the connection ends of the drain electrodes of the nineteenth MOS tube and the twentieth MOS tube are connected with the filtering module;
the bias module comprises a twenty-first MOS tube and a fifth resistor of the twenty-first MOS tube,
the source electrode of the twenty-first MOS tube is connected with a positive voltage, and the connected end of the grid electrode and the drain electrode is connected with the grid electrode of the first MOS tube;
the source electrode of the twelfth MOS tube is connected with negative voltage, and the connected end of the grid electrode and the drain electrode is connected with the grid electrode of the sixth MOS tube;
and the drain electrode of the twenty-first MOS tube is connected with the drain electrode of the twenty-second MOS tube through a fifth resistor.
2. The low noise LDO circuit of claim 1, wherein the pre-filter circuit comprises a first capacitor, a second capacitor, and first through eighth switches, wherein,
the input end of the pre-filter circuit is connected with a power supply and is used as a positive voltage output end;
the head end of the serial branch of the first switch and the third switch is connected with the input end of the pre-filter circuit, and the tail end of the serial branch of the first switch and the third switch is grounded;
the head end of the serial branch of the second switch and the fourth switch is grounded, and the tail end of the serial branch of the second switch and the fourth switch is connected with the negative voltage output end;
the head end of the serial branch of the fifth switch and the seventh switch is connected with the input end of the pre-filter circuit, and the tail end of the serial branch of the fifth switch and the seventh switch is grounded;
the head end of the serial branch of the sixth switch and the eighth switch is grounded, and the tail end of the serial branch of the sixth switch and the eighth switch is connected with the negative voltage output end;
one end of the first capacitor is connected with the connecting ends of the first switch and the third switch, and the other end of the first capacitor is connected with the connecting ends of the second switch and the fourth switch;
one end of the second capacitor is connected with the connecting end of the fifth switch and the seventh switch, and the other end of the second capacitor is connected with the connecting end of the sixth switch and the eighth switch;
the pre-filter circuit also comprises a front-end capacitor, a back-end capacitor and a back-end resistor, wherein,
one end of the front-end capacitor is connected with the input end of the pre-filter circuit, and the other end of the front-end capacitor is grounded;
one end of the rear end capacitor is connected with the negative voltage output end, and the other end of the rear end capacitor is grounded;
the back-end resistor is connected in parallel with the back-end capacitor.
3. The low noise LDO circuit of claim 2, wherein the pre-filter circuit further comprises a controller for controlling the first through eighth switches to be on-off.
4. The low noise LDO circuit of claim 1, wherein the post noise reduction circuit employs a bidirectional filter capacitor comprising an upper plate, a lower plate and an intermediate layer between the upper plate and the lower plate, the upper plate and the intermediate layer being connected by a silicon dioxide oxide layer; the lower polar plate is connected with the middle layer through a silicon dioxide oxide layer; one end of the bidirectional filter capacitor receives the first direct current voltage, and the other end outputs the second direct current voltage.
5. The low noise LDO circuit of claim 4, wherein the bidirectional filter capacitor is part of an integrated chip, and wherein neither the upper plate nor the lower plate introduces a pin of parasitic inductance.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140047930A (en) * | 2012-10-15 | 2014-04-23 | 단국대학교 산학협력단 | Low dropout voltage regulator of having multiple error amps |
| CN114759890A (en) * | 2022-06-15 | 2022-07-15 | 成都芯翼科技有限公司 | Differential voltage control circuit |
| CN116466785A (en) * | 2023-03-28 | 2023-07-21 | 电子科技大学 | LDO circuit with low noise and high PSR |
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| US8294441B2 (en) * | 2006-11-13 | 2012-10-23 | Decicon, Inc. | Fast low dropout voltage regulator circuit |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140047930A (en) * | 2012-10-15 | 2014-04-23 | 단국대학교 산학협력단 | Low dropout voltage regulator of having multiple error amps |
| CN114759890A (en) * | 2022-06-15 | 2022-07-15 | 成都芯翼科技有限公司 | Differential voltage control circuit |
| CN116466785A (en) * | 2023-03-28 | 2023-07-21 | 电子科技大学 | LDO circuit with low noise and high PSR |
Non-Patent Citations (1)
| Title |
|---|
| 一种响应极快负载变化的无片外电容LDO的研究与设计;李文杰;中国优秀硕士学位论文全文数据库 信息科技辑;全文 * |
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