CN110868159A - Novel audio power amplifier - Google Patents

Abstract

The invention discloses a novel audio frequency power amplifier, which multiplexes a circuit that plays an integral role in a class D power amplifier circuit and a circuit that plays a role of an operational amplifier in a class AB power amplifier circuit in a folded cascode circuit, and then Utilizing the characteristics of high output impedance, high gain and easy compensation of the folded cascode, when the performance is greatly improved, it not only saves the chip area, thereby reducing the chip cost, but also reduces the workload of the layout design of the integrated circuit, and then Save design time.

Description

A New Type of Audio Power Amplifier

technical field

The invention relates to the technical field of integrated circuits, in particular to a novel audio power amplifier.

Background technique

Class D power amplifier circuit is a switch-type power amplifier circuit. Its working principle is based on the PWM mode. It compares the audio signal with the triangular wave, and outputs a PWM waveform whose pulse width is proportional to the amplitude of the audio signal, and then amplifies the amplitude of the PWM waveform. , and then the amplified PWM waveform is restored to an amplified audio signal after filtering. Compared with linear power amplifier circuits, class D power amplifier circuits have the characteristics of high efficiency and less heat generation. Therefore, class D power amplifier circuits are widely used in the field of consumer electronic products such as smart TVs and smart phones.

The class AB power amplifier circuit adopts class AB amplifier, its efficiency is higher than that of class A amplifier, and the distortion is lower than that of class B amplifier. By biasing the two transistors in the circuit, the two transistors are turned on when the signal is close to zero; when the signal is small, the transistors keep working effectively, similar to a class A amplifier; when the signal is large, corresponding to each half cycle of the waveform, Only one transistor remains active, similar to a class B amplifier.

Researchers have found that in order to solve the problem of electromagnetic interference (EMI) in existing audio chips, the class AB power amplifier circuit and the class D power amplifier circuit are usually integrated into one chip. When the chip is in class D mode, it mainly includes the operation of the pre-stage op amp, integrator, comparator and driver. When the chip is in the class AB mode, it mainly includes the operation of the pre-stage operational amplifier and the operational amplifier circuit. That is, in the circuit system of the existing audio chip, the class AB power amplifier circuit and the class D power amplifier circuit are respectively implemented by two operational amplifier circuits. As a result, the size of the chip with these two operational amplifier circuits has to be increased, and the cost of the chip is also increased.

In view of the miniaturization of chips, how to improve the chip design with these two operational amplifier circuits has become a key research project of relevant researchers.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a new type of audio power amplifier, which multiplexes a circuit that plays an integral role in a class D power amplifier circuit and a circuit that plays a role of an operational amplifier in a class AB power amplifier circuit in a folded cascode In the circuit, the characteristics of high output impedance, high gain and easy compensation of the folded cascode are used again, so that the performance is greatly improved, which not only saves the chip area, thereby reducing the chip cost, but also reduces the layout design of the integrated circuit. workload, thereby saving design time.

According to an aspect of the present invention, the present invention provides a novel audio power amplifier, which includes: a first operational amplifier module; a multiplexing module electrically connected to the first operational amplifier module, the multiplexing module It includes a multiplexing circuit, a first group of switches and a second group of switches, the multiplexing circuit is electrically connected to the first group of switches and the second group of switches respectively; a comparison module is electrically connected to the multiplexing module; a a drive module electrically connected to the comparison module; and a load module electrically connected to the drive module; wherein, when the first group of switches is closed and the second group of switches is open, the multiplexing circuit The output terminal of the audio power amplifier is electrically connected to the comparison module, so that the multiplexing module is switched as an integration module, and the new audio power amplifier is operated in the class D power amplifier mode; when the first group of switches is turned off, the second When the two sets of switches are closed, the output terminal of the multiplexing circuit is electrically connected to the load module, so that the multiplexed module is switched as a second operational amplifier module, and the new audio power amplifier operates at AB Class amplifier mode.

On the basis of the above technical solutions, the present invention can be improved as follows.

In an embodiment of the present invention, the first operational amplifier module includes: a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor and a first operational amplifier; the first One end of a capacitor receives the positive input end, and the other end is electrically connected to one end of the first resistor; one end of the second capacitor receives the negative input end, and the other end is electrically connected to one end of the second resistor; The other end of the first resistor is respectively electrically connected to one end of the third resistor and the positive input end of the first operational amplifier; the other end of the second resistor is electrically connected to the fourth resistor respectively one end and the negative input end of the first operational amplifier; the other end of the third resistor is electrically connected to the negative output end of the first operational amplifier, and the other end of the fourth resistor is electrically connected to the The positive output of the first operational amplifier.

In an embodiment of the present invention, the multiplexing circuit includes: a fifth resistor, a sixth resistor, a multiplexing unit, a third capacitor, a fourth capacitor, a seventh resistor, and an eighth resistor; One end is electrically connected to the other end of the third resistor and the negative output end of the first operational amplifier, and the other end is electrically connected to one end of the seventh resistor, one end of the third capacitor and the other end respectively. the positive input end of the multiplexing unit; one end of the sixth resistor is electrically connected to the other end of the fourth resistor and the positive output end of the first operational amplifier, and the other end is electrically connected to the One end of the eighth resistor, one end of the fourth capacitor and the negative input end of the multiplexing unit; the other end of the third capacitor is electrically connected to the ninth switch in the first group of switches, the first The ninth switch is electrically connected to the negative output end of the multiplexing unit; the other end of the fourth capacitor is electrically connected to the tenth switch in the first group of switches, and the tenth switch is electrically connected to the The positive output of the multiplexing unit.

In an embodiment of the present invention, the comparison module includes: a first comparator and a second comparator; a positive input terminal of the first comparator is electrically connected to a negative output terminal of the multiplexing unit, so The positive input terminal of the second comparator is electrically connected to the positive output terminal of the multiplexing unit, and the negative input terminal of the first comparator and the negative input terminal of the second comparator receive a triangular wave signal.

In an embodiment of the present invention, the driving module includes: a first driver, a second driver, a first output pair tube and a second output pair tube; an input end of the first driver is electrically connected to the first driver an output end of a comparator, the input end of the second driver is electrically connected to the output end of the second comparator; the first output pair tube includes a thirty-second field effect transistor, a thirty-second field effect transistor effect transistor; the second output pair tube includes a thirty-third field effect transistor and a thirty-fourth field effect transistor; the source of the thirty-first field effect transistor receives a power supply voltage, the thirty-first field effect transistor The gate of the field effect transistor is electrically connected to the first output terminal of the first driver, and the drain of the thirty-second field effect transistor is electrically connected to the drain of the thirty-second field effect transistor; The gate of the thirty-second field-effect transistor is electrically connected to the second output terminal of the first driver, and the source of the thirty-second field-effect transistor is grounded; the thirty-third field-effect transistor The source of the 33rd FET receives a power supply voltage, the gate of the thirty-third FET is electrically connected to the first output terminal of the second driver, and the drain of the thirty-third FET is electrically connected to the drain of the thirty-fourth field effect transistor; the gate of the thirty-fourth field effect transistor is electrically connected to the second output terminal of the second driver, and the thirty-fourth field effect transistor The source is grounded.

In an embodiment of the present invention, the load module includes a load, and the load is connected to the common node of the thirty-second field effect transistor and the third field effect transistor and the third The common node of the thirteen field effect transistors and the thirty-fourth field effect transistor.

In an embodiment of the present invention, the first group of switches includes a ninth switch and a tenth switch, and the ninth switch is electrically connected to the other end of the third capacitor and the negative terminal of the multiplexing unit, respectively. an output end, the tenth switch is electrically connected to the other end of the fourth capacitor and the positive output end of the multiplexing unit respectively; the second group of switches includes: an eleventh switch, a twelfth switch, The thirteenth switch, the fourteenth switch, the fifteenth switch and the sixteenth switch; the eleventh switch is electrically connected to the multiplexing unit, the ninth switch, and the first comparator respectively. a positive input end, a common node of the twenty-first field effect transistor and the twenty-second field effect transistor; the twelfth switch is electrically connected to the multiplexing unit, the twenty-second field effect transistor, and the the gate of the field effect transistor; the thirteenth switch is respectively electrically connected to the multiplexing unit and the gate of the twenty-second field effect transistor; the fourteenth switch is electrically connected to the the multiplexing unit and the gate of the twenty-third field effect transistor; the fifteenth switch is electrically connected to the multiplexing unit and the gate of the twenty-fourth field effect transistor, respectively; the The sixteenth switch is electrically connected to the multiplexing unit, the tenth switch, the positive input terminal of the second comparator, the twenty-third field effect transistor, and the twenty-fourth field effect transistor, respectively. The public node of the pipe.

In an embodiment of the present invention, the multiplexing unit further includes: a first unit, a second unit and a third unit, the second unit is electrically connected to the first unit, and the third unit is electrically connected connected to the second unit; the first unit includes: a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, and a sixth field effect transistor FET, 7th FET, 8th FET, 9th FET, 10th FET, 11th FET, 12th FET, 13th FET, 14th FET a field effect transistor, a fifteenth field effect transistor, a sixteenth field effect transistor, a first switch, a second switch, a third switch and a fourth switch; the gate of the first field effect transistor is electrically connected to the The negative input terminal of the multiplexing unit, the source of the first field effect transistor is electrically connected to the drain of the sixteenth field effect transistor and the source of the second field effect transistor respectively, the first field effect transistor The drain of the transistor is electrically connected to the drain of the thirteenth field effect transistor and the source of the eleventh field effect transistor respectively; the gate of the second field effect transistor is electrically connected to the positive electrode of the multiplexing unit an input end, the source of the second field effect transistor is electrically connected to the drain of the sixteenth field effect transistor, and the drain of the second field effect transistor is electrically connected to the drain of the fourteenth field effect transistor respectively and the source of the twelfth FET; the source of the fifteenth FET receives a power supply voltage, and the gate of the fifteenth FET is electrically connected to the third FET respectively and the gate of the fourth field effect transistor and receive a first bias voltage, the drain of the fifteenth field effect transistor is electrically connected to the source of the sixteenth field effect transistor; The gates of the sixteenth field effect transistors are respectively electrically connected to the gates of the fifth field effect transistors and the sixth field effect transistors and receive a second bias voltage; the third The source of the field effect transistor receives a power supply voltage, the gate of the third field effect transistor is electrically connected to the gate of the fourth field effect transistor, and the drain of the third field effect transistor is electrically connected to the source of the fifth field effect transistor; the gate of the fifth field effect transistor is electrically connected to the gate of the sixth field effect transistor, and the drains of the fifth field effect transistor are respectively electrically connected the source electrode of the seventh field effect transistor and the drain electrode of the eighth field effect transistor; the source electrode of the seventh field effect transistor is electrically connected to the drain electrode of the eighth field effect transistor, the The gates of the seven field effect transistors are respectively electrically connected to one end of the third switch, one end of the fourth switch, and the drains of the seventh field effect transistors are respectively electrically connected to the eighth field effect transistor. the source, the drain of the eleventh field effect transistor; the gate of the eighth field effect transistor is respectively electrically connected to one end of the first switch, one end of the second switch, the ninth the gate of the field effect transistor, the source of the eighth field effect transistor is electrically connected to the drain of the eleventh field effect transistor; the gate of the eleventh field effect transistor is electrically connected to the tenth field effect transistor The gates of the two field effect transistors receive a third bias voltage, and the source of the eleventh field effect transistor is electrically connected to the drain of the thirteenth field effect transistor; the thirteenth field effect transistor The gate of the tube is electrically connected to the fourteenth field The gate of the effect transistor receives a fourth bias voltage, the source of the thirteenth field effect transistor is grounded; the source of the fourth field effect transistor receives a power supply voltage, and the fourth field effect transistor The gate receives the first bias voltage, the drain of the fourth field effect transistor is electrically connected to the source of the sixth field effect transistor; the gate of the sixth field effect transistor receives the second bias voltage , the drain of the sixth field effect transistor is electrically connected to the drain of the ninth field effect transistor and the source of the tenth field effect transistor respectively; the drain of the ninth field effect transistor is electrically connected connected to the source of the tenth field effect transistor, the gate of the ninth field effect transistor is respectively electrically connected to one end of the first switch and one end of the second switch, and the ninth field effect transistor The source electrodes are respectively electrically connected to the drain electrodes of the tenth field effect transistor and the drain electrodes of the twelfth field effect transistors; the gate electrodes of the tenth field effect transistors are respectively electrically connected to the third switch. one end, one end of the fourth switch, the drain of the tenth field effect transistor is electrically connected to the drain of the twelfth field effect transistor; the gate of the twelfth field effect transistor receives the third bias voltage, the source of the twelfth field effect transistor is electrically connected to the drain of the fourteenth field effect transistor; the gate of the fourteenth field effect transistor receives the fourth bias voltage, so The source of the fourteenth FET is grounded; the other end of the first switch receives a power supply voltage, the other end of the second switch receives a fifth bias voltage, and the other end of the third switch receives the first Six bias voltages, and the other end of the fourth switch is grounded.

In an embodiment of the present invention, the second unit includes: a seventeenth field effect transistor, an eighteenth field effect transistor, a nineteenth field effect transistor, a twentieth field effect transistor, a fifth switch, a sixth a switch, a seventh switch, an eighth switch, a fifth capacitor and a sixth capacitor; wherein the source of the seventeenth field effect transistor receives a power supply voltage, and the gate of the seventeenth field effect transistor is electrically connected respectively To one end of the fifth switch and one end of the sixth switch, the drain of the seventeenth field effect transistor is electrically connected to one end of the fifth capacitor and the one end of the nineteenth field effect transistor, respectively. the drain; the drain of the nineteenth field effect transistor is electrically connected to one end of the fifth capacitor, and the gate of the nineteenth field effect transistor is electrically connected to the other end of the fifth capacitor, The source of the nineteenth FET is grounded; the source of the eighteenth FET receives a power supply voltage, and the gate of the eighteenth FET is electrically connected to the seventh switch respectively one end of the eighteenth switch and one end of the eighth switch, the drain of the eighteenth field effect transistor is electrically connected to one end of the sixth capacitor and the drain of the twentieth field effect transistor, respectively; the first The drain of the twentieth field effect transistor is electrically connected to one end of the sixth capacitor, the gate of the twentieth field effect transistor is electrically connected to the other end of the sixth capacitor, and the twentieth field effect transistor is electrically connected to the other end of the sixth capacitor. The source of the effect transistor is grounded; the other end of the fifth switch is electrically connected to the gate of the fourth field effect transistor, the other end of the sixth switch is electrically connected to the drain of the fifth field effect transistor, and the other end of the seventh switch is electrically connected to the drain of the fifth field effect transistor. One end is electrically connected to the gate of the fourth field effect transistor, the other end of the eighth switch is electrically connected to the drain of the sixth field effect transistor; the gate of the nineteenth field effect transistor is electrically connected to the tenth field effect transistor The drain of the field effect transistor and the gate of the twentieth field effect transistor are electrically connected to the drain of the twelfth field effect transistor.

In an embodiment of the present invention, the third unit includes: a twenty-first field effect transistor, a twenty-second field effect transistor, a twenty-third field effect transistor, a twenty-fourth field effect transistor, a second field effect transistor Fifteen field effect transistors, twenty-sixth field effect transistors, twenty-seventh field effect transistors, twenty-eighth field effect transistors, ninth resistors and tenth resistors; the source of the twenty-first field effect transistor receiving a power supply voltage, the gate of the twenty-first field effect transistor receives a first bias voltage, and the drain of the twenty-first field effect transistor is electrically connected to the drain of the twenty-second field effect transistor a source electrode; the gate of the twenty-second field effect transistor receives a second bias voltage, and the drain of the twenty-second field effect transistor is respectively electrically connected to the source of the twenty-third field effect transistor and the source of the twenty-fourth field effect transistor; the gate of the twenty-third field effect transistor is electrically connected to one end of the ninth resistor and one end of the tenth resistor, respectively, and the The drain of the twenty-third field effect transistor is electrically connected to the drain of the twenty-fifth field effect transistor and the gate of the twenty-seventh field effect transistor respectively; the twenty-fifth field effect transistor The gate of the FET receives a third bias voltage, the source of the twenty-fifth FET is electrically connected to the drain of the twenty-seventh FET; the gate of the twenty-seventh FET is electrically connected The electrode receives the fourth bias voltage, and the source electrode of the twenty-seventh field effect transistor is grounded; the source electrode of the twenty-fourth field effect transistor is electrically connected to the source electrode of the twenty-third field effect transistor , the gate of the twenty-fourth field effect transistor receives a reference voltage, the drain of the twenty-fourth field effect transistor is electrically connected to the drain of the twenty-sixth field effect transistor, the The gate of the twenty-eighth field effect transistor; the gate of the twenty-sixth field effect transistor receives a third bias voltage, and the source of the twenty-sixth field effect transistor is electrically connected to the twenty-sixth field effect transistor The drains of the eight field effect transistors; the source of the twenty-eighth field effect transistor is grounded.

The advantage of the present invention is that the novel audio power amplifier of the present invention multiplexes the circuit that plays an integral role in the class D power amplifier circuit and the circuit that plays the role of an operational amplifier in the class AB power amplifier circuit in a folded cascode circuit In addition, the characteristics of high output impedance, high gain and easy compensation of the folded cascode are used, so that the performance is greatly improved, which not only saves the chip area, thereby reducing the chip cost, but also reduces the work of integrated circuit layout design. This saves design time.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained from these drawings without creative effort.

FIG. 1 is a schematic structural diagram of a novel audio power amplifier in an embodiment of the present invention.

FIG. 2 is a schematic diagram of circuit connection of the novel audio power amplifier in the embodiment of the present invention.

FIG. 3 is a schematic diagram of circuit connection of the first unit inside the multiplexing unit shown in FIG. 2 .

FIG. 4 is a schematic diagram of circuit connection of the second unit inside the multiplexing unit shown in FIG. 2 .

FIG. 5 is a schematic diagram of circuit connection of a third unit inside the multiplexing unit shown in FIG. 2 .

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present invention.

The terms "first", "second", "third", etc. (if present) in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It is to be understood that the objects so described are interchangeable under appropriate circumstances. Furthermore, the terms "comprising" and "having", and any variations thereof, are intended to cover non-exclusive inclusion.

In this patent document, the drawings discussed below and the embodiments used to describe the principles of the present disclosure are by way of illustration only and should not be construed as limiting the scope of the present disclosure. Those skilled in the art will understand that the principles of the invention may be implemented in any suitably arranged system. Exemplary embodiments will be described in detail, examples of which are illustrated in the accompanying drawings. Also, a terminal according to an exemplary embodiment will be described in detail with reference to the accompanying drawings. The same reference numbers in the figures refer to the same elements.

The terms used in the present specification are only used to describe specific embodiments, and are not intended to illustrate the concepts of the present invention. Expressions used in the singular cover expressions in the plural unless the context clearly indicates a different meaning. In the present specification, it should be understood that terms such as "including", "having" and "comprising" are intended to indicate the presence of the possibility of the features, numbers, steps, actions or combinations thereof disclosed in the present specification, and are not intended to be The possibility that one or more other features, numbers, steps, actions, or combinations thereof may be present or may be added is excluded. The same reference numbers in the drawings refer to the same parts.

Embodiments of the present invention provide a novel audio power amplifier. The detailed descriptions will be given below.

Referring to FIG. 1 , the present invention provides a novel audio power amplifier, which includes: a first operational amplifier module 110 , a multiplexing module 120 , a comparison module 130 , a driving module 140 and a load module 150 .

The multiplexing module 120 is electrically connected to the first operational amplifier module 110, and the multiplexing module 120 includes a multiplexing circuit, a first group of switches (SW1, SW4, SW5, SW7, SW9, SW10) and The second group of switches ( SW2 , SW3 , SW6 , SW8 , SW11 ˜ SW16 ), the multiplexing circuit 121 is electrically connected to the first group of switches and the second group of switches, respectively.

The comparison module 130 is electrically connected to the multiplexing module 120 .

The driving module 140 is electrically connected to the comparing module 130 .

The load module 150 is electrically connected to the driving module 140 .

When the first group of switches is closed and the second group of switches is open, the output terminal of the multiplexing circuit is electrically connected to the comparison module 130, so that the multiplexing module 120 is switched as an integrating module, so The output of the comparison module 130 is electrically connected to the driving module 140, and the first driver 141 and the second driver 142 in the driving module 140 are respectively electrically connected to the thirty-first power transistor M31, and the thirty-second power The gates of the tube M32, the thirty-third power tube M33, and the thirty-fourth power tube M34, and at this time, the novel audio power amplifier is made to operate in a class D power amplifier mode.

When the first group of switches is open and the second group of switches is closed, the output terminal of the multiplexing circuit is electrically connected to the load module 150 and is also electrically connected to the first group of the driving module 140 respectively. The gates of the thirty-first power transistor M31, the thirty-second power transistor M32, the thirty-third power transistor M33, and the thirty-fourth power transistor M34, so that the multiplexed module 120 is switched as a second operational amplifier module, And make the novel audio power amplifier operate in the class AB power amplifier mode.

When the D-class and AB-class modes work, the four power tubes are the grids of the thirty-first power tube M31, the thirty-second power tube M32, the thirty-third power tube M33, and the thirty-fourth power tube M34. The way of driving is different. In the class D working mode, the switching signals output by the first driver 141 and the second driver 142 drive the thirty-first power transistor M31, the thirty-second power transistor M32, and the thirty-third power transistor M33 respectively. , the gate of the thirty-fourth power tube M34. In the class AB working mode, the outputs of the multiplexing unit 121, namely node 4, node 2, node 3, and node 1, respectively, when SW12, SW13, SW14, and SW15 in the second group of switches are closed, drive the third switch. The grids of the eleventh power tube M31, the thirty-second power tube M32, the thirty-third power tube M33, and the thirty-fourth power tube M34.

Therefore, through the opening or closing of the first group of switches and the second group of switches, the output ends of the multiplexing circuit are connected to different devices, so that the multiplexing module 120 can be used as the integration module and the second operational amplifier module. Switch between the multiplexing module 120 to achieve that the audio power amplifier with the multiplexing module 120 operates in the class D power amplifier mode or the class AB power amplifier mode. Such a design not only saves the chip area, thereby reducing the cost of the chip, but also reduces the workload of the layout design of the integrated circuit, thereby saving the design time.

The specific structure of each module in the audio power amplifier will be further described below.

2, in an embodiment of the present invention, the first operational amplifier module 110 includes: a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, a third resistor R3, The fourth resistor R4 and the first operational amplifier 111 . One end of the first capacitor C1 receives the positive input end, and the other end is electrically connected to one end of the first resistor R1 . One end of the second capacitor C2 receives the negative input end, and the other end is electrically connected to one end of the second resistor R2. The other end of the first resistor R1 is electrically connected to one end of the third resistor R3 and the positive input end of the first operational amplifier 111 respectively. The other end of the second resistor R2 is electrically connected to one end of the fourth resistor R4 and the negative input end of the first operational amplifier 111 respectively. The other end of the third resistor R3 is electrically connected to the negative output end of the first operational amplifier 111 , and the other end of the fourth resistor R4 is electrically connected to the positive output end of the first operational amplifier 111 .

Continuing with reference to FIG. 2 , in this embodiment, the multiplexing circuit includes: a fifth resistor R5 , a sixth resistor R6 , a multiplexing unit 121 , a third capacitor C3 , a fourth capacitor C4 , a seventh resistor R7 and The eighth resistor R8. One end of the fifth resistor R5 is electrically connected to the other end of the third resistor R3 and the negative output end of the first operational amplifier 111 respectively, and the other end is electrically connected to one end of the seventh resistor R7 respectively , one end of the third capacitor C3 and the positive input end of the multiplexing unit 121 . One end of the sixth resistor R6 is electrically connected to the other end of the fourth resistor R4 and the positive output end of the first operational amplifier 111 respectively, and the other end is electrically connected to one end of the eighth resistor R8 respectively , one end of the fourth capacitor C4 and the negative input end of the multiplexing unit 121 . The other end of the third capacitor C3 is electrically connected to the ninth switch SW9 in the first group of switches, and the ninth switch SW9 is electrically connected to the negative output terminal of the multiplexing unit 121 . The other end of the fourth capacitor C4 is electrically connected to the tenth switch SW10 in the first group of switches, and the tenth switch SW10 is electrically connected to the positive output terminal of the multiplexing unit 121 .

In this embodiment, the comparison module 130 includes: a first comparator 131 and a second comparator 132 . The positive input terminal of the first comparator 131 is electrically connected to the negative output terminal of the multiplexing unit 121 , and the positive input terminal of the second comparator 132 is electrically connected to the positive output terminal of the multiplexing unit 121 . terminal, the negative input terminal of the first comparator 131 and the negative input terminal of the second comparator 132 receive a triangular wave signal.

In this embodiment, the driving module 140 includes: a first driver 141 , a second driver 142 , a first output pair tube and a second output pair tube. The input terminal of the first driver 141 is electrically connected to the output terminal of the first comparator 131 , and the input terminal of the second driver 142 is electrically connected to the output terminal of the second comparator 132 . The first output pair tube includes a thirty-first field effect transistor M31 and a thirty-second field effect transistor M32. The second output pair tube includes a thirty-third field effect transistor M33 and a thirty-fourth field effect transistor M34. The source of the thirty field effect transistor M31 receives a power supply voltage, the gate of the thirty field effect transistor M31 is electrically connected to the first output end of the first driver 141, the The drain of the thirty-second field effect transistor M31 is electrically connected to the drain of the thirty-second field effect transistor M32. The gate of the thirty-second field effect transistor M32 is electrically connected to the second output terminal of the first driver 141, and the source of the thirty-second field effect transistor M32 is grounded. The source of the thirty-third field effect transistor M33 receives a power supply voltage, the gate of the thirty-third field effect transistor M33 is electrically connected to the first output terminal of the second driver 142, and the first The drain of the thirty-third FET M33 is electrically connected to the drain of the thirty-fourth FET M34; the gate of the thirty-fourth FET M34 is electrically connected to the second driver The second output terminal of 142, the source of the thirty-fourth field effect transistor M34 is grounded.

In this embodiment, the load module 150 includes a load. The load is connected to the common node of the thirty-second field effect transistor M31 and the thirty-second field effect transistor M32 and the thirty-third field effect transistor M33 and the thirty-fourth field effect transistor Manage the common node of M34.

In this embodiment, the first group of switches includes a ninth switch SW9 and a tenth switch SW10, and the ninth switch SW9 is electrically connected to the other end of the third capacitor C3 and the multiplexing unit 121, respectively. The negative output terminal of the tenth switch SW10 is respectively electrically connected to the other terminal of the fourth capacitor C4 and the positive output terminal of the multiplexing unit 121 . The second group of switches includes an eleventh switch SW11 , a twelfth switch SW12 , a thirteenth switch SW13 , a fourteenth switch SW14 , a fifteenth switch SW15 and a sixteenth switch SW16 . The eleventh switch SW11 is electrically connected to the multiplexing unit 121, the ninth switch SW9, the positive input terminal of the first comparator 131, the thirty FET M31, and the The common node of the thirty-second field effect transistor M32 is described. The twelfth switch SW12 is electrically connected to the multiplexing unit 121 and the gate of the thirty FET M31 respectively. The thirteenth switch SW13 is electrically connected to the multiplexing unit 121 and the gate of the thirty-second field effect transistor M32, respectively; the fourteenth switch SW14 is electrically connected to the multiplexing unit, respectively 121. The gate of the thirty-third field effect transistor M33; the fifteenth switch SW15 is electrically connected to the multiplexing unit 121 and the gate of the thirty-fourth field effect transistor M34, respectively. The sixteenth switch SW16 is electrically connected to the multiplexing unit 121, the tenth switch SW10, the positive input terminal of the second comparator 132, the thirty-third field effect transistor M33 and all The common node of the thirty-fourth FET M34 is described.

As shown in FIGS. 1 and 2 , when the ninth switch SW9 and the tenth switch SW10 in the first group of switches are in a closed state, the eleventh switch SW11 , the twelfth switch SW12 , and the thirteenth switch SW12 in the second group of switches When the switch SW13, the fourteenth switch SW14, the fifteenth switch SW15 and the sixteenth switch SW16 are in the off state, the output terminal of the multiplexing circuit is electrically connected to the comparison module 130, so that the multiplexing circuit is Module 120 switches as an integration module. At this time, since the novel audio power amplifier has a first operational amplifier module 110 and an integration module, the condition of the class D power amplifier circuit is satisfied. Therefore, the novel audio power amplifier can operate in a class D power amplifier mode.

When the ninth switch SW9 and the tenth switch SW10 in the first group of switches are in the off state, the eleventh switch SW11 , the twelfth switch SW12 , the thirteenth switch SW13 , and the fourteenth switch SW14 in the second group of switches When the fifteenth switch SW15 and the sixteenth switch SW16 are in the closed state, the output terminal of the multiplexing circuit is electrically connected to the load, so that the multiplexed module 120 is switched as a second operational amplifier module. At this time, since the novel audio power amplifier has a first operational amplifier module 110 and a second operational amplifier module, the condition of the class AB power amplifier circuit is satisfied. Therefore, the novel audio power amplifier is made to operate in a class AB power amplifier mode.

The specific structure of the multiplexing unit 121 will be further described below.

Referring to FIG. 3 , the multiplexing unit 121 may include: a first unit, a second unit and a third unit, the second unit is electrically connected to the first unit, and the third unit is electrically connected to the the second unit.

The first unit includes: a first field effect transistor M1, a second field effect transistor M2, a third field effect transistor M3, a fourth field effect transistor M4, a fifth field effect transistor M5, a sixth field effect transistor M6, and a sixth field effect transistor M6. The seventh field effect transistor M7, the eighth field effect transistor M8, the ninth field effect transistor M9, the tenth field effect transistor M10, the eleventh field effect transistor M11, the twelfth field effect transistor M12, the thirteenth field effect transistor M13 , a fourteenth field effect transistor M14, a fifteenth field effect transistor M15, a sixteenth field effect transistor M16, a first switch SW1, a second switch SW2, a third switch SW3 and a fourth switch SW4. The gate of the first field effect transistor M1 is electrically connected to the negative input terminal of the multiplexing unit 121 (ie, INN in FIG. 3 ), and the sources of the first field effect transistor M1 are electrically connected to The drain of the sixteenth field effect transistor M16 and the source of the second field effect transistor M2, and the drain of the first field effect transistor M1 are electrically connected to the drain and the drain of the thirteenth field effect transistor M13, respectively. The source of the eleventh field effect transistor M11. The gate of the second field effect transistor M2 is electrically connected to the positive input terminal of the multiplexing unit 121 (ie, the INP in FIG. 3 ), and the source of the second field effect transistor M2 is electrically connected to the tenth The drains of the six field effect transistors M16 and the drains of the second field effect transistors M2 are respectively electrically connected to the drain electrodes of the fourteenth field effect transistor M14 and the source electrode of the twelfth field effect transistor M12. The source of the fifteenth field effect transistor M15 receives a power supply voltage, and the gate of the fifteenth field effect transistor M15 is electrically connected to the gate of the third field effect transistor M3 and the fourth field effect transistor M3 respectively. The gate of the field effect transistor M4 receives a first bias voltage VBIAS1, and the drain of the fifteenth field effect transistor M15 is electrically connected to the source of the sixteenth field effect transistor M16. The gate of the sixteenth field effect transistor M16 is electrically connected to the gate of the fifth field effect transistor M5 and the gate of the sixth field effect transistor M6 and receives a second bias voltage VBIAS2. The source of the third field effect transistor M3 receives a power supply voltage, the gate of the third field effect transistor M3 is electrically connected to the gate of the fourth field effect transistor M4, and the third field effect transistor M4 The drain of M3 is electrically connected to the source of the fifth field effect transistor M5. The gate of the fifth field effect transistor M5 is electrically connected to the gate of the sixth field effect transistor M6, and the drains of the fifth field effect transistor M5 are electrically connected to the seventh field effect transistor M7 respectively. the source and the drain of the eighth field effect transistor M8. The source of the seventh field effect transistor M7 is electrically connected to the drain of the eighth field effect transistor M8, and the gate of the seventh field effect transistor M7 is electrically connected to the third switch SW3 respectively. At one end, the drain of the seventh field effect transistor M7 is electrically connected to the source of the eighth field effect transistor M8 and the drain of the eleventh field effect transistor M11 respectively. The gate of the eighth field effect transistor M8 is electrically connected to one end of the first switch SW1, one end of the second switch SW2, and the gate of the ninth field effect transistor M9, respectively. The source of the field effect transistor M8 is electrically connected to the drain of the eleventh field effect transistor M11. The gate of the eleventh field effect transistor M11 is electrically connected to the gate of the twelfth field effect transistor M12 and receives a third bias voltage VBIAS3, and the source of the eleventh field effect transistor M11 is electrically connected connected to the drain of the thirteenth field effect transistor M13. The gate of the thirteenth field effect transistor M13 is electrically connected to the gate of the fourteenth field effect transistor M14 and receives a fourth bias voltage VBIAS4, and the source of the thirteenth field effect transistor M13 is grounded. The source of the fourth field effect transistor M4 receives a power supply voltage, the gate of the fourth field effect transistor M4 receives the first bias voltage VBIAS1, and the drain of the fourth field effect transistor M4 is electrically connected to The source of the sixth field effect transistor M6. The gate of the sixth field effect transistor M6 receives the second bias voltage VBIAS2, and the drain of the sixth field effect transistor M6 is electrically connected to the drain of the ninth field effect transistor M9 and the drain of the ninth field effect transistor M9, respectively. Ten FETs M10 source. The drain of the ninth field effect transistor M9 is electrically connected to the source of the tenth field effect transistor M10, and the gate of the ninth field effect transistor M9 is electrically connected to the first switch SW1 respectively. One end and one end of the second switch SW2, the source of the ninth field effect transistor M9 is electrically connected to the drain of the tenth field effect transistor M10 and the drain of the twelfth field effect transistor M12, respectively. The gate of the tenth field effect transistor M10 is electrically connected to one end of the third switch SW3 and the one end of the fourth switch SW4 respectively, and the drain of the tenth field effect transistor M10 is electrically connected to all the The drain of the twelfth field effect transistor M12 is described. The gate of the twelfth FET M12 receives the third bias voltage VBIAS3, and the source of the twelfth FET M12 is electrically connected to the drain of the fourteenth FET M14. The gate of the fourteenth field effect transistor M14 receives the fourth bias voltage VBIAS4, and the source of the fourteenth field effect transistor M14 is grounded. The other end of the first switch SW1 receives a power supply voltage, the other end of the second switch SW2 receives a fifth bias voltage VBIAS5, the other end of the third switch SW3 receives a sixth bias voltage VBIAS6, and the other end of the third switch SW3 receives a sixth bias voltage VBIAS6. The other end of the fourth switch SW4 is grounded.

Referring to FIG. 4 , the second unit includes: a seventeenth field effect transistor M17, an eighteenth field effect transistor M18, a nineteenth field effect transistor M19, a twentieth field effect transistor M20, a fifth switch SW5, a sixth Switch SW6, seventh switch SW7, eighth switch SW8, fifth capacitor C5 and sixth capacitor C6. The source of the seventeenth field effect transistor M17 receives a power supply voltage, and the gate of the seventeenth field effect transistor M17 is electrically connected to one end of the fifth switch SW5 and the sixth switch SW6 respectively. One end of the seventeenth FET M17 is electrically connected to one end of the fifth capacitor C5 and the drain of the nineteenth FET M19, respectively. The drain of the nineteenth field effect transistor M19 is electrically connected to one end of the fifth capacitor C5, and the gate of the nineteenth field effect transistor M19 is electrically connected to the other end of the fifth capacitor C5 , the source of the nineteenth field effect transistor M19 is grounded. The source of the eighteenth field effect transistor M18 receives a power supply voltage, and the gate of the eighteenth field effect transistor M18 is electrically connected to one end of the seventh switch SW7 and the eighth switch SW8 respectively. At one end, the drain of the eighteenth field effect transistor M18 is electrically connected to one end of the sixth capacitor C6 and the drain of the twentieth field effect transistor M20, respectively. The drain of the twentieth FET M20 is electrically connected to one end of the sixth capacitor C6, and the gate of the twentieth FET M20 is electrically connected to the other end of the sixth capacitor C6 , the source of the twentieth FET M20 is grounded. The other end of the fifth switch SW5 is electrically connected to the gate of the fourth field effect transistor M4, the other end of the sixth switch SW6 is electrically connected to the drain of the fifth field effect transistor M5, and the other end of the seventh switch SW7 is electrically connected. is electrically connected to the gate of the fourth field effect transistor M4, the other end of the eighth switch SW8 is electrically connected to the drain of the sixth field effect transistor M6; the gate of the nineteenth field effect transistor M19 is electrically connected to the The drain of the eleventh field effect transistor M11 and the gate of the twentieth field effect transistor M20 are electrically connected to the drain of the twelfth field effect transistor M12.

The third unit includes: a twenty-first field effect transistor M21, a twenty-second field effect transistor M22, a twenty-third field effect transistor M23, a twenty-fourth field effect transistor M24, and a twenty-fifth field effect transistor M25, the twenty-sixth field effect transistor M26, the twenty-seventh field effect transistor M27, the twenty-eighth field effect transistor M28, the ninth resistor R9 and the tenth resistor R10. The source of the twenty-first field effect transistor M21 receives a power supply voltage, the gate of the twenty-first field effect transistor M21 receives the first bias voltage VBIAS1, and the twenty-first field effect transistor M21 The drain is electrically connected to the source of the twenty-second field effect transistor M22. The gate of the twenty-second field effect transistor M22 receives the second bias voltage VBIAS2, and the drain of the twenty-second field effect transistor M22 is electrically connected to the twenty-third field effect transistor M23 respectively. The source electrode and the source electrode of the twenty-fourth field effect transistor M24. The gate of the twenty-third field effect transistor M23 is electrically connected to one end of the ninth resistor R9 and one end of the tenth resistor R10, respectively, and the drain of the twenty-third field effect transistor M23 is respectively It is electrically connected to the drain of the twenty-fifth field effect transistor M25 and the gate of the twenty-seventh field effect transistor M27. The gate of the twenty-fifth field effect transistor M25 receives the third bias voltage VBIAS3, and the source of the twenty-fifth field effect transistor M25 is electrically connected to the drain of the twenty-seventh field effect transistor M27 pole. The gate of the twenty-seventh field effect transistor M27 receives the fourth bias voltage VBIAS4, and the source of the twenty-seventh field effect transistor M27 is grounded. The source of the twenty-fourth FET M24 is electrically connected to the source of the twenty-third FET M23, the gate of the twenty-fourth FET M24 receives a reference voltage, and the The drain of the twenty-fourth field effect transistor M24 is electrically connected to the drain of the twenty-sixth field effect transistor M26 and the gate of the twenty-eighth field effect transistor M28, respectively. The gate of the twenty-sixth FET M26 receives the third bias voltage VBIAS3, and the source of the twenty-sixth FET M26 is electrically connected to the drain of the twenty-eighth FET M28 pole. The source of the twenty-eighth field effect transistor M28 is grounded.

According to the above design of the multiplexing unit 121, the first unit can be regarded as a folded cascode structure with differential input, which is a gain stage and provides an amplification function; the second unit is regarded as an output stage with bias current, which is a The common source stage amplifier provides amplification function and driving ability; the third unit is regarded as a common mode feedback circuit, which provides the bias function, so that the differential output voltage of the second unit is equal to the reference voltage through the common mode voltage of node 6 and node 7.

The operation of the novel audio power amplifier of the present invention will be described below.

When the ninth switch SW9 and the tenth switch SW10 in the first group of switches are closed, the multiplexing unit 121 plays an integral role. When the eleventh switch SW11, the twelfth switch SW12, the thirteenth switch SW13, the fourteenth switch SW14, the fifteenth switch SW15 and the sixteenth switch SW16 in the second group of switches are in the off state, the The first switch SW1 and the fourth switch SW4 in the unit 121 are in the closed state, the second switch SW2 and the third switch SW3 are in the open state, the fifth switch SW5 and the seventh switch SW7 are in the closed state, and the sixth switch SW6 and The eighth switch SW8 is in an off state. Therefore, the seventh field effect transistor M7, the eighth field effect transistor M8, the ninth field effect transistor M9 and the tenth field effect transistor M10 work in the linear region. Therefore, the seventh field effect transistor M7, the eighth field effect transistor M8, The ninth field effect transistor M9 and the tenth field effect transistor M10 can be used as fully conducting switching transistors. At this time, the gates of the seventeenth field effect transistor M17 and the eighteenth field effect transistor M18 are biased by the first bias voltage VBIAS1 through the node 5 . The multiplexing unit 121 is a typical folded cascode operational amplifier with an output stage. This cascode op amp can provide a very high gain stage. As defined by the cascode structure, it converts the input voltage into a current, which is then used as the input to the cascode stage. A cascade of cascode and cascode stages is called a cascode structure. Among them, the common source stage converts the input voltage into current, and the common gate stage receives the input at the source and produces the output at the drain. In this embodiment, the first field effect transistor M1 and the second field effect transistor M2 are common source stages, which convert the input voltage (gate signal) into a current, and this current is input to the eleventh field effect transistor M11 and the tenth field effect transistor M11 The sources of the two field effect transistors M12 are then output from the drains of the eleventh field effect transistor M11 and the twelfth field effect transistor M12, and the eleventh field effect transistor M11 and the twelfth field effect transistor M12 are common gates. . At this time, the thirteenth field effect transistor M13 and the fourteenth field effect transistor M14 are current bias transistors. The multiplexing unit 121 is further configured to integrate the feedback signal. The output of the multiplexing unit 121 is compared with the triangular wave to generate a PWM modulation signal, which is then output by the driving circuit of the driving module 140 to drive the load (here, the speaker). In this way, the novel audio power amplifier of the present invention can operate in the class D power amplifier mode.

In addition, it should be noted that when the fifth switch SW5 and the seventh switch SW7 are closed, and the sixth switch SW6 and the eighth switch SW8 are open, the seventeenth field effect transistor M17, the eighteenth field effect transistor M18, the tenth The five field effect transistors M15, the third field effect transistor M3, the fourth field effect transistor M4, and the twenty-first field effect transistor M21 are a group of current mirrors, and their gate voltages are the voltages at node 5, that is, the first Bias voltage VBIAS1. Node 6 and node 7 are the positive and negative output stages of the folded cascode operational amplifier respectively. At this time, the seventeenth field effect transistor M17 and the eighteenth field effect transistor M18 are used as current mirrors to provide the output stage bias current, The nineteenth field effect transistor M19 and the twentieth field effect transistor M20 are common source amplifying transistors, which provide an amplification function.

When the ninth switch SW9 and the tenth switch SW10 in the first group of switches are turned off, the multiplexing unit 121 functions as an operational amplifier. When the eleventh switch SW11, the twelfth switch SW12, the thirteenth switch SW13, the fourteenth switch SW14, the fifteenth switch SW15 and the sixteenth switch SW16 in the second group of switches are in the closed state, the multiplexing The first switch SW1 and the fourth switch SW4 in the unit 121 are in the open state, the second switch SW2 and the third switch SW3 are in the closed state, the fifth switch SW5 and the seventh switch SW7 are in the open state, and the sixth switch SW6 and the seventh switch SW7 are in the open state. The eighth switch SW8 is in a closed state. Therefore, the seventh field effect transistor M7, the eighth field effect transistor M8, the ninth field effect transistor M9 and the tenth field effect transistor M10 work in the saturation region. Therefore, the seventh field effect transistor M7, the eighth field effect transistor M8, The ninth field effect transistor M9 and the tenth field effect transistor M10 can be used as intermediate bias transistors of class AB. At this time, the gate voltages of the seventeenth field effect transistor M17 and the eighteenth field effect transistor M18 are the voltages of the nodes 3 and 4, and the voltages there have a biasing effect. The multiplexing unit 121 is a class AB operational amplifier with a folded cascode. The third capacitor C3 and the fourth capacitor C4 electrically connected to the multiplexing unit 121 do not work, the first comparator 131 and the second comparator 132 are off, and the first driver 141 and the second driver 142 are off state. The seventeenth field effect transistor M17 and the nineteenth field effect transistor M19 in the internal output tubes of the multiplexing unit 121 that play the role of an operational amplifier are respectively the thirty-third field effect transistor M33 and the thirty-fourth field effect transistor. Tube M34 in parallel. The eighteenth field effect transistor M18 and the twentieth field effect transistor M20 in the internal output transistors of the multiplexing unit 121 that function as operational amplifiers are respectively the thirtieth field effect transistor M31 and the thirty second field effect transistor M31 and the thirty-second field effect transistor. Tube M32 is connected in parallel. At this time, the thirty-third FET M33, the thirty-fourth FET M34, the thirty-third FET M31, and the thirty-second FET M32 are respectively connected to the nodes 3 and 1 shown in FIG. 3 . , node 4 and node 2 bias to achieve the drive to the load speaker. In this way, the novel audio power amplifier of the present invention can operate in the class AB power amplifier mode.

In addition, it should be noted that when the fifth switch SW5 and the seventh switch SW7 are turned off, and the sixth switch SW6 and the eighth switch SW8 are turned on, the gates of the seventeenth field effect transistor M17 and the eighteenth field effect transistor M18 The voltage is not the first bias voltage VBIAS1, but the bias provided by the node 3 and node 4 position voltages. Cooperating with the first switch SW1 to the fourth switch SW4, at this time, the second switch SW2 and the third switch SW3 are closed, and when the first switch SW1 and the fourth switch SW4 are opened, the seventeenth field effect transistor M17 and the eighteenth field effect transistor M17 and the eighteenth field effect transistor are closed. Tube M18 is not used as a current mirror, but as an upper output tube of class AB.

The present invention adds a first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4, a fifth switch SW5, a sixth switch SW6, a seventh switch The switch SW7, the eighth switch SW8, the seventh field effect transistor M7, the eighth field effect transistor M8, the ninth field effect transistor M9, the tenth field effect transistor M10, and the ninth switch SW9 to the tenth field effect transistor shown in FIG. The switching function of the six switches SW16 changes the gate bias voltage of the seventh field effect transistor M7, the eighth field effect transistor M8, the ninth field effect transistor M9, and the tenth field effect transistor M10, so as to realize the folding type with output stage The cascode two-stage operational amplifier is converted into a class AB operational amplifier with a folded cascode structure.

Further, by setting the seventh field effect transistor M7, the eighth field effect transistor M8, the ninth field effect transistor M9, and the tenth field effect transistor M10, the voltages at node 3, node 4, node 1, and node 2 are The seventeenth field effect transistor M17, the eighteenth field effect transistor M18, the nineteenth field effect transistor M19, and the twentieth field effect transistor M20 can be biased respectively, so that the seventeenth field effect transistor M17 and the eighteenth field effect transistor M17 and the eighteenth field effect transistor can be biased respectively. The tube M18, the nineteenth field effect tube M19, and the twentieth field effect tube M20 work in the state of class AB operational amplifiers. When the state of the class D operational amplifier is switched to the state of the class AB operational amplifier, the output stage of the second unit is not a common source stage amplifier, but a class AB amplifier. When the D-type working mode is used before switching, the gate voltages of the seventh field effect transistor M7, the eighth field effect transistor M8, the ninth field effect transistor M9, and the tenth field effect transistor M10 are the power supply voltage or the ground level. The voltage at node 3 is approximately equal to the voltage at node 1, and the voltage at node 4 is approximately equal to the voltage at node 2. When the switching is in the class AB working mode, the gate voltages of the seventh field effect transistor M7, the eighth field effect transistor M8, the ninth field effect transistor M9, and the tenth field effect transistor M10 need to be adjusted to the fifth bias voltage respectively VBIAS5 and the sixth bias voltage VBIAS6. At this time, the voltage of node 3 is not equal to the voltage of node 1, and the voltage of node 4 is not equal to the voltage of node 2, so that the seventeenth field effect transistor M17, the eighteenth field effect transistor M18, and the nineteenth field effect transistor M19 can be , The twentieth FET M20 works in the state of class AB amplification.

Therefore, the novel audio power amplifier of the present invention multiplexes the integrator in the class D power amplifier circuit and the operational amplifier in the class AB power amplifier circuit in a folded cascode circuit. Further, when the folded cascode features high output impedance, high gain, and easy compensation, and the performance is greatly improved, it not only saves the chip area, thereby reducing the chip cost, but also reduces the workload of integrated circuit layout design. , thereby saving design time.

The above are only the preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, without departing from the principles of the present invention, several improvements and modifications can also be made, and these improvements and modifications should also be regarded as It is the protection scope of the present invention.

Claims (10)

1. a novel audio frequency power amplifier, is characterized in that, comprises: a first operational amplifier module; a multiplexing module electrically connected to the first operational amplifier module, the multiplexing module includes a multiplexing circuit, a first group of switches and a second group of switches, the multiplexing circuit is respectively connected to the first group of switches and the second group of switches Two groups of switches are electrically connected; a comparison module, electrically connected with the multiplexing module; a driving module, electrically connected with the comparison module; and a load module electrically connected to the drive module; wherein, When the first group of switches is closed and the second group of switches is open, the output terminal of the multiplexing circuit is electrically connected to the comparison module, so that the multiplexing module is switched as an integrating module, and all The new audio power amplifier operates in a Class D power amplifier mode; When the first group of switches is open and the second group of switches is closed, the output end of the multiplexing circuit is electrically connected to the load module, so that the multiplexed module is switched as a second operational amplifier module, and The novel audio power amplifier is made to operate in a class AB power amplifier mode. 2. The novel audio power amplifier according to claim 1, wherein the first operational amplifier module comprises: a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor, and a fourth resistor and the first operational amplifier; one end of the first capacitor receives the positive input, and the other end is electrically connected to one end of the first resistor; one end of the second capacitor receives the negative input, and the other end is connected to the first One end of the two resistors is electrically connected; the other end of the first resistor is electrically connected to one end of the third resistor and the positive input end of the first operational amplifier, respectively; the other end of the second resistor is electrically connected to is electrically connected to one end of the fourth resistor and the negative input end of the first operational amplifier; the other end of the third resistor is electrically connected to the negative output end of the first operational amplifier, and the fourth resistor is electrically connected to the negative output end of the first operational amplifier. The other end of the is electrically connected to the positive output end of the first operational amplifier. 3. The novel audio power amplifier according to claim 2, wherein the multiplexing circuit comprises: a fifth resistor, a sixth resistor, a multiplexing unit, a third capacitor, a fourth capacitor, a seventh resistor and a Eight resistors; one end of the fifth resistor is electrically connected to the other end of the third resistor and the negative output end of the first operational amplifier, and the other end is electrically connected to one end of the seventh resistor, one end of the third capacitor and the positive input end of the multiplexing unit; one end of the sixth resistor is electrically connected to the other end of the fourth resistor and the positive output end of the first operational amplifier, respectively, The other end is respectively electrically connected to one end of the eighth resistor, one end of the fourth capacitor and the negative input end of the multiplexing unit; the other end of the third capacitor is electrically connected to the first group of switches The ninth switch in the switch, the ninth switch is electrically connected to the negative output terminal of the multiplexing unit; the other end of the fourth capacitor is electrically connected to the tenth switch in the first group of switches, the The tenth switch is electrically connected to the positive output terminal of the multiplexing unit. 4 . The novel audio power amplifier according to claim 3 , wherein the comparison module comprises: a first comparator and a second comparator; the positive input terminal of the first comparator is electrically connected to the The negative output terminal of the multiplexing unit, the positive input terminal of the second comparator is electrically connected to the positive output terminal of the multiplexing unit, the negative input terminal of the first comparator and the negative input terminal of the second comparator The negative input terminal receives a triangular wave signal. 5 . The new audio power amplifier according to claim 4 , wherein the driving module comprises: a first driver, a second driver, a first output pair tube and a second output pair tube; The input terminal is electrically connected to the output terminal of the first comparator, and the input terminal of the second driver is electrically connected to the output terminal of the second comparator; the first output pair tube includes a thirty-first Field effect transistor, thirty-second field effect transistor; the second output pair tube includes a thirty-third field effect transistor and a thirty-fourth field effect transistor; the source of the thirty field effect transistor receives a the power supply voltage, the gate of the thirty FET is electrically connected to the first output terminal of the first driver, and the drain of the thirty FET is electrically connected to the third the drains of twelve FETs; the gates of the thirty-second FETs are electrically connected to the second output terminal of the first driver, and the sources of the thirty-second FETs are grounded; The source of the thirty-third FET receives a power supply voltage, the gate of the thirty-third FET is electrically connected to the first output end of the second driver, and the thirty-third The drain of the FET is electrically connected to the drain of the thirty-fourth FET; the gate of the thirty-fourth FET is electrically connected to the second output terminal of the second driver, The source of the thirty-fourth field effect transistor is grounded. 6 . The novel audio power amplifier according to claim 5 , wherein the load module comprises a load, and the load is connected to the thirty-second field effect transistor and the thirty-second field effect transistor. 7 . and the common node of the thirty-third field effect transistor and the thirty-fourth field effect transistor. 7 . The novel audio power amplifier according to claim 6 , wherein the first group of switches comprises a ninth switch and a tenth switch, and the ninth switches are respectively electrically connected to the other ends of the third capacitor. 8 . one end and the negative output end of the multiplexing unit, the tenth switch is electrically connected to the other end of the fourth capacitor and the positive output end of the multiplexing unit, respectively; the second group of switches includes: a first An eleventh switch, a twelfth switch, a thirteenth switch, a fourteenth switch, a fifteenth switch and a sixteenth switch; the eleventh switch is electrically connected to the multiplexing unit, the ninth switch and the a switch, the positive input terminal of the first comparator, the common node of the thirty-second field effect transistor and the thirty-second field effect transistor; the twelfth switch is electrically connected to the a multiplexing unit, the gate of the thirty-second field effect transistor; the thirteenth switch is electrically connected to the multiplexing unit and the gate of the thirty-second field effect transistor, respectively; the The fourteen switches are respectively electrically connected to the multiplexing unit and the gate of the thirty-third field effect transistor; the fifteenth switch is electrically connected to the multiplexing unit, the thirty-fourth FET, respectively. the gate of the field effect transistor; the sixteenth switch is respectively electrically connected to the multiplexing unit, the tenth switch, the positive input terminal of the second comparator, and the thirty-third field effect transistor and the common node of the thirty-fourth FET. 8. The novel audio power amplifier according to claim 3, wherein the multiplexing unit further comprises: a first unit, a second unit and a third unit, the second unit is electrically connected to the first unit A unit, the third unit is electrically connected to the second unit; the first unit includes: a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a third Five field effect transistors, sixth field effect transistors, seventh field effect transistors, eighth field effect transistors, ninth field effect transistors, tenth field effect transistors, eleventh field effect transistors, twelfth field effect transistors, Thirteen field effect transistors, fourteenth field effect transistors, fifteenth field effect transistors, sixteenth field effect transistors, a first switch, a second switch, a third switch and a fourth switch; the first field effect transistor The gate of the multiplexing unit is electrically connected to the negative input terminal of the multiplexing unit, and the source of the first field effect transistor is electrically connected to the drain of the sixteenth field effect transistor and the second field effect transistor respectively. a source electrode, the drain electrode of the first field effect transistor is electrically connected to the drain electrode of the thirteenth field effect transistor and the source electrode of the eleventh field effect transistor respectively; the gate electrode of the second field effect transistor is electrically connected connected to the positive input terminal of the multiplexing unit, the source of the second field effect transistor is electrically connected to the drain of the sixteenth field effect transistor, and the drain of the second field effect transistor is electrically connected to The drain electrode of the fourteenth field effect transistor and the source electrode of the twelfth field effect transistor; the source electrode of the fifteenth field effect transistor receives a power supply voltage, and the gate electrode of the fifteenth field effect transistor is electrically is connected to the gate of the third field effect transistor and the gate of the fourth field effect transistor and receives a first bias voltage, and the drain of the fifteenth field effect transistor is electrically connected to the fourth field effect transistor the source electrodes of sixteen field effect transistors; the gate electrodes of the sixteenth field effect transistors are respectively electrically connected to the gate electrodes of the fifth field effect transistors and the gate electrodes of the sixth field effect transistors and receive a first Two bias voltages; the source of the third field effect transistor receives a power supply voltage, the gate of the third field effect transistor is electrically connected to the gate of the fourth field effect transistor, and the third field effect transistor is electrically connected to the gate of the fourth field effect transistor. The drain of the effect transistor is electrically connected to the source of the fifth field effect transistor; the gate of the fifth field effect transistor is electrically connected to the gate of the sixth field effect transistor, and the fifth field effect transistor is electrically connected to the gate of the sixth field effect transistor. The drain of the effect transistor is electrically connected to the source of the seventh field effect transistor and the drain of the eighth field effect transistor respectively; the source of the seventh field effect transistor is electrically connected to the eighth field the drain of the effect transistor, the gate of the seventh field effect transistor is electrically connected to one end of the third switch and the one end of the fourth switch, respectively, the drain of the seventh field effect transistor is electrically connected to connected to the source of the eighth field effect transistor and the drain of the eleventh field effect transistor; the gate of the eighth field effect transistor is electrically connected to one end of the first switch, the One end of the second switch, the gate of the ninth field effect transistor, the source of the eighth field effect transistor is electrically connected to the drain of the eleventh field effect transistor; the eleventh field effect transistor The gate of the twelfth FET is electrically connected to the gate of the twelfth FET and receives a third bias voltage, and the source of the eleventh FET is electrically connected to the drain of the thirteenth FET pole; the tenth The gates of the three field effect transistors are electrically connected to the gates of the fourteenth field effect transistor and receive a fourth bias voltage, and the source of the thirteenth field effect transistor is grounded; The source electrode receives a power supply voltage, the gate electrode of the fourth field effect transistor receives a first bias voltage, and the drain electrode of the fourth field effect transistor is electrically connected to the source electrode of the sixth field effect transistor; The gate of the sixth field effect transistor receives a second bias voltage, and the drain of the sixth field effect transistor is electrically connected to the drain of the ninth field effect transistor and the drain of the tenth field effect transistor respectively. a source electrode; the drain electrode of the ninth field effect transistor is electrically connected to the source electrode of the tenth field effect transistor, and the gate electrode of the ninth field effect transistor is electrically connected to one end of the first switch respectively and one end of the second switch, the source of the ninth field effect transistor is electrically connected to the drain of the tenth field effect transistor and the drain of the twelfth field effect transistor respectively; the tenth field effect transistor The gate of the transistor is electrically connected to one end of the third switch and one end of the fourth switch, respectively, and the drain of the tenth field effect transistor is electrically connected to the drain of the twelfth field effect transistor ; the gate of the twelfth FET receives a third bias voltage, and the source of the twelfth FET is electrically connected to the drain of the fourteenth FET; the tenth The gates of the four field effect transistors receive a fourth bias voltage, and the source of the fourteenth field effect transistor is grounded; the other end of the first switch receives a power supply voltage, and the other end of the second switch receives the first Five bias voltages, the other end of the third switch receives a sixth bias voltage, and the other end of the fourth switch is grounded. 9 . The novel audio power amplifier according to claim 8 , wherein the second unit comprises: a seventeenth field effect transistor, an eighteenth field effect transistor, a nineteenth field effect transistor, and a twentieth field effect transistor. 10 . an effect transistor, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a fifth capacitor and a sixth capacitor; wherein the source of the seventeenth field effect transistor receives a power supply voltage, and the seventeenth field effect transistor A gate of the effect transistor is electrically connected to one end of the fifth switch and one end of the sixth switch, respectively, and a drain of the seventeenth field effect transistor is electrically connected to one end of the fifth capacitor and one end of the sixth switch, respectively. the drain of the nineteenth field effect transistor; the drain of the nineteenth field effect transistor is electrically connected to one end of the fifth capacitor, and the gate of the nineteenth field effect transistor is electrically connected to At the other end of the fifth capacitor, the source of the nineteenth field effect transistor is grounded; the source of the eighteenth field effect transistor receives a power supply voltage, and the gate of the eighteenth field effect transistor is respectively is electrically connected to one end of the seventh switch and one end of the eighth switch, and the drain of the eighteenth field effect transistor is electrically connected to one end of the sixth capacitor and the twentieth field, respectively the drain of the effect transistor; the drain of the twentieth field effect transistor is electrically connected to one end of the sixth capacitor, and the gate of the twentieth field effect transistor is electrically connected to the sixth capacitor At the other end, the source of the twentieth field effect transistor is grounded; the other end of the fifth switch is electrically connected to the gate of the fourth field effect transistor, and the other end of the sixth switch is electrically connected to the fifth field effect transistor drain, the other end of the seventh switch is electrically connected to the gate of the fourth field effect transistor, the other end of the eighth switch is electrically connected to the drain of the sixth field effect transistor; the gate of the nineteenth field effect transistor The electrode is electrically connected to the drain of the eleventh field effect transistor, and the gate of the twentieth field effect transistor is electrically connected to the drain of the twelfth field effect transistor. 10. The novel audio power amplifier according to claim 8, wherein the third unit comprises: a twenty-first field effect transistor, a twenty-second field effect transistor, a twenty-third field effect transistor, a Twenty-four field effect transistors, twenty-fifth field effect transistors, twenty-sixth field effect transistors, twenty-seventh field effect transistors, twenty-eighth field effect transistors, ninth resistors and tenth resistors; the first The source of the twenty-first field effect transistor receives a power supply voltage, the gate of the twenty-first field effect transistor receives a first bias voltage, and the drain of the twenty-first field effect transistor is electrically connected to the the source of the twenty-second field effect transistor; the gate of the twenty-second field effect transistor receives a second bias voltage, and the drain of the twenty-second field effect transistor is electrically connected to the The source of the twenty-third field effect transistor and the source of the twenty-fourth field effect transistor; the gate of the twenty-third field effect transistor is electrically connected to one end of the ninth resistor and all the one end of the tenth resistor, the drain of the twenty-third field effect transistor is electrically connected to the drain of the twenty-fifth field effect transistor and the gate of the twenty-seventh field effect transistor, respectively; The gate of the twenty-fifth field effect transistor receives a third bias voltage, and the source of the twenty-fifth field effect transistor is electrically connected to the drain of the twenty-seventh field effect transistor; The gate of the twenty-seventh field-effect transistor receives a fourth bias voltage, the source of the twenty-seventh field-effect transistor is grounded; the source of the twenty-fourth field-effect transistor is electrically connected to the The source of the twenty-third field effect transistor, the gate of the twenty-fourth field effect transistor receives a reference voltage, and the drain of the twenty-fourth field effect transistor is electrically connected to the twenty-fourth field effect transistor respectively. The drain of the six field effect transistors, the grid of the twenty-eighth field effect transistor; the gate of the twenty-sixth field effect transistor receives a third bias voltage, and the gate of the twenty-sixth field effect transistor The source is electrically connected to the drain of the twenty-eighth field effect transistor; the source of the twenty-eighth field effect transistor is grounded.

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