CN110868159A

CN110868159A - Novel audio power amplifier

Info

Publication number: CN110868159A
Application number: CN201911281018.2A
Authority: CN
Inventors: 樊大伟
Original assignee: Haimen Microelectronics Co Ltd
Current assignee: Haimen Microelectronics Co Ltd
Priority date: 2019-12-13
Filing date: 2019-12-13
Publication date: 2020-03-06

Abstract

The invention discloses a novel audio power amplifier, which multiplexes a circuit playing a role of integration in a D-type power amplifier circuit and a circuit playing a role of operational amplification in an AB-type power amplifier circuit into a folding cascode circuit, and then utilizes the characteristics of high output impedance, high gain and easy compensation of the folding cascode circuit to greatly improve the performance, thereby not only saving the area of a chip and further reducing the cost of the chip, but also reducing the workload of integrated circuit layout design and further saving the design time.

Description

Novel audio power amplifier

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a novel audio power amplifier.

Background

The class-D power amplifier circuit is a switch-type power amplifier circuit, and the working principle of the switch-type power amplifier circuit is based on a PWM mode, an audio signal is compared with a triangular wave, a PWM waveform with the pulse width in direct proportion to the amplitude of the audio signal is output, then the amplitude of the PWM waveform is amplified, and the amplified PWM waveform is restored into an amplified audio signal after being filtered. Compared with a linear power amplifier circuit, the D-type power amplifier circuit has the characteristics of high efficiency and less heat generation, so that the D-type power amplifier circuit is widely applied to the fields of consumer electronics products such as smart televisions and smart phones.

The AB class power amplifier circuit adopts an AB class amplifier, the efficiency of the AB class power amplifier circuit is higher than that of an A class amplifier, and the distortion of the AB class power amplifier circuit is lower than that of a B class amplifier. Two transistors in the circuit are biased to be conducted when a signal is close to zero; at small signals, the transistors all keep working effectively, similar to a class A amplifier; for large signals, only one transistor remains active, corresponding to each half cycle of the waveform, similar to a class B amplifier.

Researchers have found that, in order to solve the problem of electromagnetic interference (EMI), an AB class power amplifier circuit and a D class power amplifier circuit are usually integrated into one chip in the conventional audio chip. When the chip is in a D-type mode, the chip mainly comprises a front-end operational amplifier, an integrator, a comparator and a driver. When the chip is in the AB mode, the operation of the front-stage operational amplifier and the operational amplifier circuit is mainly included. That is, in the circuit system of the existing audio chip, the class AB power amplifier circuit and the class D power amplifier circuit are implemented by two operational amplifier circuits, respectively. This results in a chip size having both operational amplifier circuits having to be increased, which also increases the chip cost.

In view of the development of miniaturization of chips, how to improve the chip design with these two op-amp circuits becomes an important research project for relevant researchers.

Disclosure of Invention

The invention aims to provide a novel audio power amplifier, which multiplexes a circuit playing an integral role in a D-type power amplifier circuit and a circuit playing an operational amplification role in an AB-type power amplifier circuit into a folding cascode circuit, and then utilizes the characteristics of high output impedance, high gain and easiness in compensation of the folding cascode circuit, so that under the condition of greatly improving the performance, the area of a chip is saved, the cost of the chip is reduced, the workload of the layout design of an integrated circuit can be reduced, and the design time is saved.

According to an aspect of the present invention, there is provided a novel audio power amplifier, comprising: a first operational amplifier module; the multiplexing module is electrically connected with the first operational amplifier module and comprises a multiplexing circuit, a first group of switches and a second group of switches, and the multiplexing circuit is electrically connected with the first group of switches and the second group of switches respectively; the comparison module is electrically connected with the multiplexing module; the driving module is electrically connected with the comparison module; the load module is electrically connected with the driving module; when the first group of switches is closed and the second group of switches is open, the output end of the multiplexing circuit is electrically connected to the comparison module, so that the multiplexing module is switched to be an integration module, and the novel audio power amplifier operates in a class D power amplifier mode; when the first group of switches is off and the second group of switches is on, the output end of the multiplexing circuit is electrically connected to the load module, so that the multiplexing module is switched to be used as a second operational amplifier module, and the novel audio power amplifier operates in an AB type power amplification mode.

On the basis of the above technical solution, the present invention may be improved as follows.

In an embodiment of the present invention, the first operational amplifier module includes: the circuit comprises a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor and a first operational amplifier; one end of the first capacitor receives the positive input end, and the other end of the first capacitor is electrically connected with one end of the first resistor; one end of the second capacitor receives the negative input end, and the other end of the second capacitor is electrically connected with one end of the second resistor; the other end of the first resistor is electrically connected to one end of the third resistor and the positive input end of the first operational amplifier respectively; the other end of the second resistor is electrically connected to one end of the fourth resistor and the negative input end of the first operational amplifier respectively; the other end of the third resistor is electrically connected to the negative output end of the first operational amplifier, and the other end of the fourth resistor is electrically connected to the positive output end of the first operational amplifier.

In an embodiment of the present invention, the multiplexing circuit includes: the first resistor, the second resistor, the third resistor, the fourth resistor, the seventh resistor and the eighth resistor are connected in series; one end of the fifth resistor is electrically connected to the other end of the third resistor and the negative output end of the first operational amplifier, and the other end of the fifth resistor is electrically connected to one end of the seventh resistor, one end of the third capacitor, and the positive input end of the multiplexing unit; one end of the sixth resistor is electrically connected to the other end of the fourth resistor and the positive output end of the first operational amplifier, and the other end of the sixth resistor is electrically connected to one end of the eighth resistor, one end of the fourth capacitor and the negative input end of the multiplexing unit; the other end of the third capacitor is electrically connected to a ninth switch in the first group of switches, and the ninth switch is electrically connected to the negative output end of the multiplexing unit; the other end of the fourth capacitor is electrically connected to a tenth switch in the first group of switches, and the tenth switch is electrically connected to the positive output end of the multiplexing unit.

In an embodiment of the present invention, the comparing module includes: a first comparator and a second comparator; the positive input end of the first comparator is electrically connected to the negative output end of the multiplexing unit, the positive input end of the second comparator is electrically connected to the positive output end of the multiplexing unit, and the negative input end of the first comparator and the negative input end of the second comparator receive a triangular wave signal.

In an embodiment of the present invention, the driving module includes: the first driver, the second driver, the first output pair of tubes and the second output pair of tubes; the input end of the first driver is electrically connected to the output end of the first comparator, and the input end of the second driver is electrically connected to the output end of the second comparator; the first output pair transistors comprise a thirty-first field effect transistor and a thirty-second field effect transistor; the second output pair transistor comprises a thirty-third field effect transistor and a thirty-fourth field effect transistor; a source electrode of the thirty-first field effect transistor receives a power supply voltage, a grid electrode of the thirty-first field effect transistor is electrically connected to the first output end of the first driver, and a drain electrode of the thirty-first field effect transistor is electrically connected to a drain electrode of the thirty-second field effect transistor; the grid electrode of the thirty-second field effect transistor is electrically connected to the second output end of the first driver, and the source electrode of the thirty-second field effect transistor is grounded; a source electrode of the thirty-third field effect transistor receives a power supply voltage, a grid electrode of the thirty-third field effect transistor is electrically connected to the first output end of the second driver, and a drain electrode of the thirty-third field effect transistor is electrically connected to a drain electrode of the thirty-fourth field effect transistor; the gate of the thirty-fourth field effect transistor is electrically connected to the second output end of the second driver, and the source of the thirty-fourth field effect transistor is grounded.

In an embodiment of the invention, the load module comprises a load connected to a common node of the thirty-first and thirty-second fets and a common node of the thirty-third and thirty-fourth fets.

In an embodiment of the invention, the first group of switches includes a ninth switch and a tenth switch, the ninth switch is electrically connected to the other end of the third capacitor and the negative output terminal of the multiplexing unit, respectively, and the tenth switch is electrically connected to the other end of the fourth capacitor and the positive output terminal of the multiplexing unit, respectively; the second set of switches comprises: an eleventh switch, a twelfth switch, a thirteenth switch, a fourteenth switch, a fifteenth switch, and a sixteenth switch; the eleventh switch is electrically connected to the multiplexing unit, the ninth switch, the positive input terminal of the first comparator, and a common node of the twenty-first field effect transistor and the twenty-second field effect transistor, respectively; the twelfth switch is electrically connected to the multiplexing unit and the grid electrode of the twenty-first field effect transistor respectively; the thirteenth switch is electrically connected to the multiplexing unit and the grid electrode of the twenty-second field effect transistor respectively; the fourteenth switch is electrically connected to the multiplexing unit and the grid electrode of the twenty-third field effect transistor respectively; the fifteenth switch is electrically connected to the multiplexing unit and the grid electrode of the twenty-fourth field effect transistor respectively; the sixteenth switch is electrically connected to the multiplexing unit, the tenth switch, the positive input end of the second comparator, and the common node of the twenty-third fet and the twenty-fourth fet, respectively.

In an embodiment of the present invention, the multiplexing unit further includes: the device comprises a first unit, a second unit and a third unit, wherein the second unit is electrically connected to the first unit, and the third unit is electrically connected to the second unit; the first unit includes: the first field effect transistor, the second field effect transistor, the third field effect transistor, the fourth field effect transistor, the fifth field effect transistor, the sixth field effect transistor, the seventh field effect transistor, the eighth field effect transistor, the ninth field effect transistor, the tenth field effect transistor, the eleventh field effect transistor, the twelfth field effect transistor, the thirteenth field effect transistor, the fourteenth field effect transistor, the fifteenth field effect transistor, the sixteenth field effect transistor, the first switch, the second switch, the third switch and the fourth switch; the grid electrode of the first field effect tube is electrically connected to the negative input end of the multiplexing unit, the source electrode of the first field effect tube is electrically connected to the drain electrode of the sixteenth field effect tube and the source electrode of the second field effect tube respectively, and the drain electrode of the first field effect tube is electrically connected to the drain electrode of the thirteenth field effect tube and the source electrode of the eleventh field effect tube respectively; a grid electrode of the second field effect transistor is electrically connected to the positive input end of the multiplexing unit, a source electrode of the second field effect transistor is electrically connected to a drain electrode of the sixteenth field effect transistor, and drain electrodes of the second field effect transistor are respectively and electrically connected to a drain electrode of the fourteenth field effect transistor and a source electrode of the twelfth field effect transistor; a source electrode of the fifteenth field effect transistor receives a power supply voltage, a grid electrode of the fifteenth field effect transistor is respectively and electrically connected to a grid electrode of the third field effect transistor and a grid electrode of the fourth field effect transistor and receives a first bias voltage, and a drain electrode of the fifteenth field effect transistor is electrically connected to a source electrode of the sixteenth field effect transistor; the grid electrode of the sixteenth field effect transistor is respectively and electrically connected to the grid electrode of the fifth field effect transistor and the grid electrode of the sixth field effect transistor and receives a second bias voltage; the source electrode of the third field effect transistor receives a power supply voltage, the grid electrode of the third field effect transistor is electrically connected to the grid electrode of the fourth field effect transistor, and the drain electrode of the third field effect transistor is electrically connected to the source electrode of the fifth field effect transistor; a grid electrode of the fifth field effect transistor is electrically connected to a grid electrode of the sixth field effect transistor, and a drain electrode of the fifth field effect transistor is respectively and electrically connected with a source electrode of the seventh field effect transistor and a drain electrode of the eighth field effect transistor; a source electrode of the seventh field effect transistor is electrically connected to a drain electrode of the eighth field effect transistor, a gate electrode of the seventh field effect transistor is electrically connected to one end of the third switch and one end of the fourth switch respectively, and a drain electrode of the seventh field effect transistor is electrically connected to a source electrode of the eighth field effect transistor and a drain electrode of the eleventh field effect transistor respectively; a grid electrode of the eighth field effect transistor is electrically connected to one end of the first switch, one end of the second switch and a grid electrode of the ninth field effect transistor respectively, and a source electrode of the eighth field effect transistor is electrically connected to a drain electrode of the eleventh field effect transistor; the grid electrode of the eleventh field effect transistor is electrically connected to the grid electrode of the twelfth field effect transistor and receives a third bias voltage, and the source electrode of the eleventh field effect transistor is electrically connected to the drain electrode of the thirteenth field effect transistor; the grid electrode of the thirteenth field effect transistor is electrically connected to the grid electrode of the fourteenth field effect transistor and receives a fourth bias voltage, and the source electrode of the thirteenth field effect transistor is grounded; a source electrode of the fourth field effect transistor receives a power supply voltage, a grid electrode of the fourth field effect transistor receives a first bias voltage, and a drain electrode of the fourth field effect transistor is electrically connected to a source electrode of the sixth field effect transistor; a grid electrode of the sixth field effect transistor receives a second bias voltage, and a drain electrode of the sixth field effect transistor is electrically connected to a drain electrode of the ninth field effect transistor and a source electrode of the tenth field effect transistor respectively; a drain electrode of the ninth field effect transistor is electrically connected to a source electrode of the tenth field effect transistor, a gate electrode of the ninth field effect transistor is electrically connected to one end of the first switch and one end of the second switch respectively, and a source electrode of the ninth field effect transistor is electrically connected to a drain electrode of the tenth field effect transistor and a drain electrode of the twelfth field effect transistor respectively; a grid electrode of the tenth field effect transistor is electrically connected to one end of the third switch and one end of the fourth switch respectively, and a drain electrode of the tenth field effect transistor is electrically connected to a drain electrode of the twelfth field effect transistor; a grid electrode of the twelfth field effect transistor receives a third bias voltage, and a source electrode of the twelfth field effect transistor is electrically connected to a drain electrode of the fourteenth field effect transistor; a grid electrode of the fourteenth field effect transistor receives a fourth bias voltage, and a source electrode of the fourteenth field effect transistor is grounded; the other end of the first switch receives a power supply voltage, the other end of the second switch receives a fifth bias voltage, the other end of the third switch receives a sixth bias voltage, and the other end of the fourth switch is grounded.

In an embodiment of the present invention, the second unit includes: a seventeenth field effect transistor, an eighteenth field effect transistor, a nineteenth field effect transistor, a twentieth field effect transistor, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a fifth capacitor and a sixth capacitor; a source electrode of the seventeenth field-effect transistor receives a power supply voltage, a gate electrode of the seventeenth field-effect transistor is electrically connected to one end of the fifth switch and one end of the sixth switch respectively, and a drain electrode of the seventeenth field-effect transistor is electrically connected to one end of the fifth capacitor and a drain electrode of the nineteenth field-effect transistor respectively; the drain electrode of the nineteenth field effect transistor is electrically connected to one end of the fifth capacitor, the gate electrode of the nineteenth field effect transistor is electrically connected to the other end of the fifth capacitor, and the source electrode of the nineteenth field effect transistor is grounded; a source electrode of the eighteenth field effect transistor receives a power supply voltage, a grid electrode of the eighteenth field effect transistor is electrically connected to one end of the seventh switch and one end of the eighth switch respectively, and a drain electrode of the eighteenth field effect transistor is electrically connected to one end of the sixth capacitor and the drain electrode of the twentieth field effect transistor respectively; the drain of the twentieth field effect transistor is electrically connected to one end of the sixth capacitor, the gate of the twentieth field effect transistor is electrically connected to the other end of the sixth capacitor, and the source of the twentieth field effect transistor is grounded; the other end of the fifth switch is electrically connected to the grid electrode of the fourth field effect transistor, the other end of the sixth switch is electrically connected to the drain electrode of the fifth field effect transistor, the other end of the seventh switch is electrically connected to the grid electrode of the fourth field effect transistor, and the other end of the eighth switch is electrically connected to the drain electrode of the sixth field effect transistor; the grid electrode of the nineteenth field effect transistor is electrically connected to the drain electrode of the eleventh field effect transistor, and the grid electrode of the twentieth field effect transistor is electrically connected to the drain electrode of the twelfth field effect transistor.

In an embodiment of the present invention, the third unit includes: a twenty-first field effect transistor, a twenty-second field effect transistor, a twenty-third field effect transistor, a twenty-fourth field effect transistor, a twenty-fifth field effect transistor, a twenty-sixth field effect transistor, a twenty-seventh field effect transistor, a twenty-eighth field effect transistor, a ninth resistor and a tenth resistor; a source electrode of the twenty-first field effect transistor receives a power supply voltage, a grid electrode of the twenty-first field effect transistor receives a first bias voltage, and a drain electrode of the twenty-first field effect transistor is electrically connected to a source electrode of the twenty-second field effect transistor; a grid electrode of the twenty-second field effect transistor receives a second bias voltage, and a drain electrode of the twenty-second field effect transistor is electrically connected to a source electrode of the twenty-third field effect transistor and a source electrode of the twenty-fourth field effect transistor respectively; a grid electrode of the twenty-third field effect transistor is electrically connected to one end of the ninth resistor and one end of the tenth resistor respectively, and a drain electrode of the twenty-third field effect transistor is electrically connected to a drain electrode of the twenty-fifth field effect transistor and a grid electrode of the twenty-seventh field effect transistor respectively; a grid electrode of the twenty-fifth field effect transistor receives a third bias voltage, and a source electrode of the twenty-fifth field effect transistor is electrically connected to a drain electrode of the twenty-seventh field effect transistor; a grid electrode of the twenty-seventh field effect transistor receives a fourth bias voltage, and a source electrode of the twenty-seventh field effect transistor is grounded; a source electrode of the twenty-fourth field effect transistor is electrically connected to a source electrode of the twenty-third field effect transistor, a gate electrode of the twenty-fourth field effect transistor receives a reference voltage, and a drain electrode of the twenty-fourth field effect transistor is electrically connected to a drain electrode of the twenty-sixth field effect transistor and a gate electrode of the twenty-eighth field effect transistor respectively; a grid electrode of the twenty-sixth field effect transistor receives a third bias voltage, and a source electrode of the twenty-sixth field effect transistor is electrically connected to a drain electrode of the twenty-eighth field effect transistor; and the source electrode of the twenty-eighth field effect transistor is grounded.

The novel audio power amplifier has the advantages that the circuit playing the integrating role in the D-class power amplifier circuit and the circuit playing the operational amplifying role in the AB-class power amplifier circuit are multiplexed in the folding cascode circuit, and the characteristics of high output impedance, high gain and easiness in compensation of the folding cascode are utilized, so that under the condition of greatly improving the performance, the area of a chip is saved, the cost of the chip is reduced, the workload of the layout design of an integrated circuit can be reduced, and the design time is saved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic diagram of a novel audio power amplifier according to an embodiment of the present invention.

Fig. 2 is a schematic circuit connection diagram of the novel audio power amplifier in the embodiment of the invention.

Fig. 3 is a schematic circuit connection diagram of the first unit inside the multiplexing unit shown in fig. 2.

Fig. 4 is a schematic circuit connection diagram of a second unit inside the multiplexing unit shown in fig. 2.

Fig. 5 is a schematic circuit connection diagram of a third unit inside the multiplexing unit shown in fig. 2.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terms "first," "second," "third," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the objects so described are interchangeable under appropriate circumstances. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover a non-exclusive inclusion.

In this patent document, the drawings discussed below and the embodiments used to describe the principles of the present disclosure are by way of illustration only and should not be construed in any way to limit the scope of the present disclosure. Those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged system. Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. Further, a terminal according to an exemplary embodiment will be described in detail with reference to the accompanying drawings. Like reference symbols in the various drawings indicate like elements.

The terms used in the description of the present invention are only used to describe specific embodiments, and are not intended to show the concept of the present invention. Unless the context clearly dictates otherwise, expressions used in the singular form encompass expressions in the plural form. In the present specification, it is to be understood that terms such as "comprising," "having," and "containing" are intended to specify the presence of stated features, integers, steps, acts, or combinations thereof, as taught in the present specification, and are not intended to preclude the presence or addition of one or more other features, integers, steps, acts, or combinations thereof. Like reference symbols in the various drawings indicate like elements.

The embodiment of the invention provides a novel audio power amplifier. The details will be described below separately.

Referring to fig. 1, the present invention provides a novel audio power amplifier, which includes: the operational amplifier comprises a first operational amplifier module 110, a multiplexing module 120, a comparison module 130, a driving module 140 and a load module 150.

The multiplexing module 120 is electrically connected to the first operational amplifier module 110, the multiplexing module 120 includes a multiplexing circuit, a first group of switches (SW1, SW4, SW5, SW7, SW9, SW10), and a second group of switches (SW2, SW3, SW6, SW8, SW11 to SW16), and the multiplexing circuit 121 is electrically connected to the first group of switches and the second group of switches, respectively.

The comparing module 130 is electrically connected to the multiplexing module 120.

The driving module 140 is electrically connected to the comparing module 130.

The load module 150 is electrically connected to the driving module 140.

When the first group of switches is closed and the second group of switches is open, the output end of the multiplexing circuit is electrically connected to the comparison module 130, so that the multiplexing module 120 is switched to be an integration module, the output of the comparison module 130 is electrically connected to the driving module 140, the first driver 141 and the second driver 142 in the driving module 140 are electrically connected to the gates of the thirty-first power transistor M31, the thirty-second power transistor M32, the thirty-third power transistor M33 and the thirty-fourth power transistor M34, respectively, and at this time, the novel audio power amplifier is operated in the class D power amplifier mode.

When the first set of switches is open and the second set of switches is closed, the output terminal of the multiplexing circuit is electrically connected to the load module 150, and is also electrically connected to the gates of the thirty-first power transistor M31, the thirty-second power transistor M32, the thirty-third power transistor M33, and the thirty-fourth power transistor M34 in the driving module 140, respectively, so that the multiplexing module 120 is switched to be a second operational amplifier module, and the novel audio power amplifier operates in the class AB power amplifier mode.

When the two modes of the D type and the AB type work, the grid driving modes of the four power tubes, namely the thirty-first power tube M31, the thirty-second power tube M32, the thirty-third power tube M33 and the thirty-fourth power tube M34 are different. In the class D operation mode, the switching signals output by the first driver 141 and the second driver 142 drive the gates of the thirty-first power transistor M31, the thirty-second power transistor M32, the thirty-third power transistor M33, and the thirty-fourth power transistor M34, respectively. In the class AB operation mode, the outputs of the multiplexing unit 121, i.e., node 4, node 2, node 3, and node 1, respectively drive the gates of the thirty-first power transistor M31, the thirty-second power transistor M32, the thirty-third power transistor M33, and the thirty-fourth power transistor M34 when the switches SW12, SW13, SW14, and SW15 in the second set of switches are closed.

Therefore, the output end of the multiplexing circuit is connected to different devices by opening or closing the first group of switches and the second group of switches, so that the multiplexing module 120 can be switched between the integrating module and the second operational amplifier module, and the audio power amplifier with the multiplexing module 120 operates in a class D power amplifier mode or a class AB power amplifier mode. By the design, the area of the chip is saved, the cost of the chip is reduced, the workload of the integrated circuit layout design can be reduced, and the design time is saved.

The specific structure of each module in the audio power amplifier will be further described below.

Referring to fig. 2, in an embodiment of the present invention, the first operational amplifier module 110 includes: the circuit comprises a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a first operational amplifier 111. One end of the first capacitor C1 receives the positive input end, and the other end is electrically connected to one end of the first resistor R1. One end of the second capacitor C2 receives the negative input end, and the other end is electrically connected to one end of the second resistor R2. The other end of the first resistor R1 is electrically connected to one end of the third resistor R3 and the positive input end of the first operational amplifier 111, respectively. The other end of the second resistor R2 is electrically connected to one end of the fourth resistor R4 and the negative input terminal of the first operational amplifier 111, respectively. The other end of the third resistor R3 is electrically connected to the negative output terminal of the first operational amplifier 111, and the other end of the fourth resistor R4 is electrically connected to the positive output terminal of the first operational amplifier 111.

With continuing reference to fig. 2, in this embodiment, the multiplexing circuit includes: the circuit comprises a fifth resistor R5, a sixth resistor R6, a multiplexing unit 121, a third capacitor C3, a fourth capacitor C4, a seventh resistor R7 and an eighth resistor R8. One end of the fifth resistor R5 is electrically connected to the other end of the third resistor R3 and the negative output terminal of the first operational amplifier 111, and the other end is electrically connected to one end of the seventh resistor R7, one end of the third capacitor C3 and the positive input terminal of the multiplexing unit 121. One end of the sixth resistor R6 is electrically connected to the other end of the fourth resistor R4 and the positive output terminal of the first operational amplifier 111, and the other end is electrically connected to one end of the eighth resistor R8, one end of the fourth capacitor C4 and the negative input terminal of the multiplexing unit 121. The other end of the third capacitor C3 is electrically connected to a ninth switch SW9 of the first set of switches, and the ninth switch SW9 is electrically connected to the negative output terminal of the multiplexing unit 121. The other end of the fourth capacitor C4 is electrically connected to a tenth switch SW10 of the first set of switches, and the tenth switch SW10 is electrically connected to the positive output terminal of the multiplexing unit 121.

In this embodiment, the comparing module 130 includes: a first comparator 131 and a second comparator 132. A positive input terminal of the first comparator 131 is electrically connected to the negative output terminal of the multiplexing unit 121, a positive input terminal of the second comparator 132 is electrically connected to the positive output terminal of the multiplexing unit 121, and the negative input terminal of the first comparator 131 and the negative input terminal of the second comparator 132 receive a triangular wave signal.

In this embodiment, the driving module 140 includes: a first driver 141, a second driver 142, a first pair of output transistors, and a second pair of output transistors. An input terminal of the first driver 141 is electrically connected to an output terminal of the first comparator 131, and an input terminal of the second driver 142 is electrically connected to an output terminal of the second comparator 132. The first output pair of transistors comprises a thirty-first field effect transistor M31 and a thirty-second field effect transistor M32. The second output pair of transistors comprises a thirty-third field effect transistor M33 and a thirty-fourth field effect transistor M34. The source of the thirty-first fet M31 receives a power voltage, the gate of the thirty-first fet M31 is electrically connected to the first output terminal of the first driver 141, and the drain of the thirty-first fet M31 is electrically connected to the drain of the thirty-second fet M32. The gate of the thirty-second fet M32 is electrically connected to the second output terminal of the first driver 141, and the source of the thirty-second fet M32 is grounded. The source of the thirty-third fet M33 receives a power voltage, the gate of the thirty-third fet M33 is electrically connected to the first output terminal of the second driver 142, and the drain of the thirty-third fet M33 is electrically connected to the drain of the thirty-fourth fet M34; the gate of the thirty-fourth fet M34 is electrically connected to the second output terminal of the second driver 142, and the source of the thirty-fourth fet M34 is grounded.

In this embodiment, the load module 150 includes a load. The load is connected to a common node of the thirty-first and thirty-second fets M31, M32 and a common node of the thirty-third and thirty-fourth fets M33, M34.

In this embodiment, the first set of switches includes a ninth switch SW9 and a tenth switch SW10, the ninth switch SW9 is electrically connected to the other end of the third capacitor C3 and the negative output terminal of the multiplexing unit 121, respectively, and the tenth switch SW10 is electrically connected to the other end of the fourth capacitor C4 and the positive output terminal of the multiplexing unit 121, respectively. The second set of switches comprises: an eleventh switch SW11, a twelfth switch SW12, a thirteenth switch SW13, a fourteenth switch SW14, a fifteenth switch SW15 and a sixteenth switch SW 16. The eleventh switch SW11 is electrically connected to a common node of the multiplexing unit 121, the ninth switch SW9, the positive input terminal of the first comparator 131, the thirty-first fet M31 and the thirty-second fet M32, respectively. The twelfth switch SW12 is electrically connected to the multiplexing unit 121 and the gate of the thirty-first fet M31, respectively. The thirteenth switch SW13 is electrically connected to the multiplexing unit 121 and the gate of the thirty-second fet M32, respectively; the fourteenth switch SW14 is electrically connected to the multiplexing unit 121 and the gate of the thirty-third fet M33, respectively; the fifteenth switch SW15 is electrically connected to the multiplexing unit 121 and the gate of the thirty-fourth fet M34, respectively. The sixteenth switch SW16 is electrically connected to a common node of the multiplexing unit 121, the tenth switch SW10, the positive input terminal of the second comparator 132, the thirty-third fet M33 and the thirty-fourth fet M34, respectively.

As shown in fig. 1 and 2, when the ninth switch SW9 and the tenth switch SW10 in the first set of switches are in a closed state and the eleventh switch SW11, the twelfth switch SW12, the thirteenth switch SW13, the fourteenth switch SW14, the fifteenth switch SW15 and the sixteenth switch SW16 in the second set of switches are in an open state, the output end of the multiplexing circuit is electrically connected to the comparing module 130, so that the multiplexing module 120 is switched to be an integrating module. At this time, since the novel audio power amplifier has a first operational amplifier module 110 and an integration module, the condition of the class D power amplifier circuit is satisfied. Therefore, the novel audio power amplifier can operate in a class D power amplifier mode.

When the ninth switch SW9 and the tenth switch SW10 in the first set of switches are in an open state and the eleventh switch SW11, the twelfth switch SW12, the thirteenth switch SW13, the fourteenth switch SW14, the fifteenth switch SW15 and the sixteenth switch SW16 in the second set of switches are in a closed state, the output end of the multiplexing circuit is electrically connected to the load, so that the multiplexing module 120 is switched to be a second operational amplifier module. At this time, the novel audio power amplifier has a first operational amplifier module 110 and a second operational amplifier module, which satisfies the conditions of the class AB power amplifier circuit. Therefore, the novel audio power amplifier is enabled to operate in a class AB power amplifier mode.

The specific structure of the multiplexing unit 121 will be further described below.

Referring to fig. 3, the multiplexing unit 121 may include: the device comprises a first unit, a second unit and a third unit, wherein the second unit is electrically connected to the first unit, and the third unit is electrically connected to the second unit.

The first unit includes: a first fet M1, a second fet M2, a third fet M3, a fourth fet M4, a fifth fet M5, a sixth fet M6, a seventh fet M7, an eighth fet M8, a ninth fet M9, a tenth fet M10, an eleventh fet M11, a twelfth fet M12, a thirteenth fet M13, a fourteenth fet M14, a fifteenth fet M15, a sixteenth fet M16, a first switch SW1, a second switch SW2, a third switch SW3 and a fourth switch SW 4. The gate of the first fet M1 is electrically connected to the negative input terminal (i.e., INN in fig. 3) of the multiplexing unit 121, the source of the first fet M1 is electrically connected to the drain of the sixteenth fet M16 and the source of the second fet M2, respectively, and the drain of the first fet M1 is electrically connected to the drain of the thirteenth fet M13 and the source of the eleventh fet M11, respectively. The gate of the second fet M2 is electrically connected to the positive input terminal (i.e., INP in fig. 3) of the multiplexing unit 121, the source of the second fet M2 is electrically connected to the drain of the sixteenth fet M16, and the drains of the second fet M2 are electrically connected to the drain of the fourteenth fet M14 and the source of the twelfth fet M12, respectively. The source of the fifteenth fet M15 receives a power voltage, the gate of the fifteenth fet M15 is electrically connected to the gate of the third fet M3 and the gate of the fourth fet M4 respectively and receives a first bias voltage VBIAS1, and the drain of the fifteenth fet M15 is electrically connected to the source of the sixteenth fet M16. The gate of the sixteenth fet M16 is electrically connected to the gate of the fifth fet M5 and the gate of the sixth fet M6, respectively, and receives a second bias voltage VBIAS 2. The source of the third fet M3 receives a power voltage, the gate of the third fet M3 is electrically connected to the gate of the fourth fet M4, and the drain of the third fet M3 is electrically connected to the source of the fifth fet M5. The gate of the fifth fet M5 is electrically connected to the gate of the sixth fet M6, and the drain of the fifth fet M5 is electrically connected to the source of the seventh fet M7 and the drain of the eighth fet M8, respectively. A source of the seventh fet M7 is electrically connected to a drain of the eighth fet M8, gates of the seventh fet M7 are respectively electrically connected to one end of the third switch SW3, and a drain of the seventh fet M7 is respectively electrically connected to a source of the eighth fet M8 and a drain of the eleventh fet M11. A gate of the eighth fet M8 is electrically connected to one end of the first switch SW1, one end of the second switch SW2, and a gate of the ninth fet M9, respectively, and a source of the eighth fet M8 is electrically connected to a drain of the eleventh fet M11. The gate of the eleventh fet M11 is electrically connected to the gate of the twelfth fet M12 and receives a third bias voltage VBIAS3, and the source of the eleventh fet M11 is electrically connected to the drain of the thirteenth fet M13. The gate of the thirteenth fet M13 is electrically connected to the gate of the fourteenth fet M14 and receives a fourth bias voltage VBIAS4, and the source of the thirteenth fet M13 is grounded. The source of the fourth fet M4 receives a power voltage, the gate of the fourth fet M4 receives a first bias voltage VBIAS1, and the drain of the fourth fet M4 is electrically connected to the source of the sixth fet M6. The gate of the sixth fet M6 receives a second bias voltage VBIAS2, and the drain of the sixth fet M6 is electrically connected to the drain of the ninth fet M9 and the source of the tenth fet M10, respectively. The drain of the ninth fet M9 is electrically connected to the source of the tenth fet M10, the gate of the ninth fet M9 is electrically connected to one end of the first switch SW1 and one end of the second switch SW2, respectively, and the source of the ninth fet M9 is electrically connected to the drain of the tenth fet M10 and the drain of the twelfth fet M12, respectively. A gate of the tenth fet M10 is electrically connected to one end of the third switch SW3 and one end of the fourth switch SW4, respectively, and a drain of the tenth fet M10 is electrically connected to a drain of the twelfth fet M12. The gate of the twelfth fet M12 receives a third bias voltage VBIAS3, and the source of the twelfth fet M12 is electrically connected to the drain of the fourteenth fet M14. The gate of the fourteenth fet M14 receives the fourth bias voltage VBIAS4, and the source of the fourteenth fet M14 is grounded. The other end of the first switch SW1 receives a power voltage, the other end of the second switch SW2 receives a fifth bias voltage VBIAS5, the other end of the third switch SW3 receives a sixth bias voltage VBIAS6, and the other end of the fourth switch SW4 is grounded.

Referring to fig. 4, the second unit includes: a seventeenth fet M17, an eighteenth fet M18, a nineteenth fet M19, a twentieth fet M20, a fifth switch SW5, a sixth switch SW6, a seventh switch SW7, an eighth switch SW8, a fifth capacitor C5 and a sixth capacitor C6. The source of the seventeenth fet M17 receives a power voltage, the gate of the seventeenth fet M17 is electrically connected to one end of the fifth switch SW5 and one end of the sixth switch SW6, respectively, and the drain of the seventeenth fet M17 is electrically connected to one end of the fifth capacitor C5 and the drain of the nineteenth fet M19, respectively. The drain of the nineteenth fet M19 is electrically connected to one end of the fifth capacitor C5, the gate of the nineteenth fet M19 is electrically connected to the other end of the fifth capacitor C5, and the source of the nineteenth fet M19 is grounded. A source of the eighteenth fet M18 receives a power voltage, a gate of the eighteenth fet M18 is electrically connected to one end of the seventh switch SW7 and one end of the eighth switch SW8, respectively, and a drain of the eighteenth fet M18 is electrically connected to one end of the sixth capacitor C6 and a drain of the twentieth fet M20, respectively. The drain of the twentieth fet M20 is electrically connected to one end of the sixth capacitor C6, the gate of the twentieth fet M20 is electrically connected to the other end of the sixth capacitor C6, and the source of the twentieth fet M20 is grounded. The other end of the fifth switch SW5 is electrically connected to the gate of the fourth fet M4, the other end of the sixth switch SW6 is electrically connected to the drain of the fifth fet M5, the other end of the seventh switch SW7 is electrically connected to the gate of the fourth fet M4, and the other end of the eighth switch SW8 is electrically connected to the drain of the sixth fet M6; the gate of the nineteenth fet M19 is electrically connected to the drain of the eleventh fet M11, and the gate of the twentieth fet M20 is electrically connected to the drain of the twelfth fet M12.

The third unit includes: a twenty-first field effect transistor M21, a twenty-second field effect transistor M22, a twenty-third field effect transistor M23, a twenty-fourth field effect transistor M24, a twenty-fifth field effect transistor M25, a twenty-sixth field effect transistor M26, a twenty-seventh field effect transistor M27, a twenty-eighth field effect transistor M28, a ninth resistor R9 and a tenth resistor R10. The source of the twenty-first fet M21 receives a power voltage, the gate of the twenty-first fet M21 receives a first bias voltage VBIAS1, and the drain of the twenty-first fet M21 is electrically connected to the source of the twenty-second fet M22. The gate of the twenty-second fet M22 receives a second bias voltage VBIAS2, and the drain of the twenty-second fet M22 is electrically connected to the source of the twenty-third fet M23 and the source of the twenty-fourth fet M24, respectively. A gate of the twenty-third fet M23 is electrically connected to one end of the ninth resistor R9 and one end of the tenth resistor R10, respectively, and a drain of the twenty-third fet M23 is electrically connected to a drain of the twenty-fifth fet M25 and a gate of the twenty-seventh fet M27, respectively. The gate of the twenty-fifth fet M25 receives a third bias voltage VBIAS3, and the source of the twenty-fifth fet M25 is electrically connected to the drain of the twenty-seventh fet M27. The gate of the twenty-seventh fet M27 receives the fourth bias voltage VBIAS4, and the source of the twenty-seventh fet M27 is grounded. A source of the twenty-fourth fet M24 is electrically connected to a source of the twenty-third fet M23, a gate of the twenty-fourth fet M24 receives a reference voltage, and a drain of the twenty-fourth fet M24 is electrically connected to a drain of the twenty-sixth fet M26 and a gate of the twenty-eighth fet M28, respectively. The gate of the twenty-sixth fet M26 receives a third bias voltage VBIAS3, and the source of the twenty-sixth fet M26 is electrically connected to the drain of the twenty-eighth fet M28. The source of the twenty-eighth fet M28 is grounded.

According to the design of the multiplexing unit 121, the first unit can be regarded as a folded cascode structure with differential input, and is a gain stage, which provides an amplification function; the second unit is an output stage with bias current, is a common source stage amplifier and provides an amplification function and driving capability; the third unit is regarded as a common-mode feedback circuit and provides a biasing function, so that the differential output voltage of the second unit is equal to the reference voltage through the common-mode voltage of the node 6 and the node 7.

The operation of the novel audio power amplifier of the present invention will be described below.

When the ninth switch SW9 and the tenth switch SW10 in the first group of switches are closed, the multiplexing unit 121 performs an integration function. When the eleventh switch SW11, the twelfth switch SW12, the thirteenth switch SW13, the fourteenth switch SW14, the fifteenth switch SW15 and the sixteenth switch SW16 in the second group of switches are in an open state, the first switch SW1 and the fourth switch SW4 in the multiplexing unit 121 are in a closed state, the second switch SW2 and the third switch SW3 are in an open state, the fifth switch SW5 and the seventh switch SW7 are in a closed state, and the sixth switch SW6 and the eighth switch SW8 are in an open state. Accordingly, the seventh fet M7, the eighth fet M8, the ninth fet M9, and the tenth fet M10 operate in a linear region, and thus the seventh fet M7, the eighth fet M8, the ninth fet M9, and the tenth fet M10 can be used as fully-conductive switching transistors. At this time, the gates of the seventeenth fet M17 and the eighteenth fet M18 are biased by the first bias voltage VBIAS1 through the node 5. The multiplexing unit 121 is a typical folded cascode operational amplifier with an output stage. The cascode operational amplifier may provide a very high gain stage. It is able to convert an input voltage into a current, which is then used as an input to the common-gate stage, as defined by the cascode structure. The cascade of a common-source and a common-gate is called a cascode structure. The common source stage converts an input voltage into a current, and the common gate stage receives an input at a source and generates an output at a drain. In this embodiment, the first fet M1 and the second fet M2 are common source stages, convert an input voltage (gate signal) into a current, which is input to the sources of the eleventh fet M11 and the twelfth fet M12 and then output from the drains of the eleventh fet M11 and the twelfth fet M12, and the eleventh fet M11 and the twelfth fet M12 are common gate stages. At this time, the thirteenth field effect transistor M13 and the fourteenth field effect transistor M14 are current bias transistors. The multiplexing unit 121 is further configured to integrate the fed back signal. The output of the multiplexing unit 121 is compared with the triangular wave to generate a PWM modulation signal, and the PWM modulation signal is output after being acted by the driving circuit of the driving module 140 to drive a load (here, a horn). Therefore, the novel audio power amplifier can operate in a class D power amplifier mode.

In addition, when the fifth switch SW5 and the seventh switch SW7 are closed and the sixth switch SW6 and the eighth switch SW8 are opened, the seventeenth fet M17, the eighteenth fet M18, the fifteenth fet M15, the third fet M3, the fourth fet M4, and the twenty-first fet M21 are a set of current mirrors, and the gate voltages of the current mirrors are the voltage at the node 5, i.e., the first bias voltage VBIAS 1. The node 6 and the node 7 are respectively a positive output stage and a negative output stage of the folded cascode operational amplifier, at this time, the seventeenth field-effect transistor M17 and the eighteenth field-effect transistor M18 are used as current mirrors to provide an output stage bias current, and the nineteenth field-effect transistor M19 and the twentieth field-effect transistor M20 are cascode transistors to provide an amplification function.

When the ninth switch SW9 and the tenth switch SW10 in the first group of switches are turned off, the multiplexing unit 121 functions as an operational amplifier. When the eleventh switch SW11, the twelfth switch SW12, the thirteenth switch SW13, the fourteenth switch SW14, the fifteenth switch SW15 and the sixteenth switch SW16 in the second group of switches are in the closed state, the first switch SW1 and the fourth switch SW4 in the multiplexing unit 121 are in the open state, the second switch SW2 and the third switch SW3 are in the closed state, the fifth switch SW5 and the seventh switch SW7 are in the open state, and the sixth switch SW6 and the eighth switch SW8 are in the closed state. Accordingly, the seventh fet M7, the eighth fet M8, the ninth fet M9, and the tenth fet M10 operate in the saturation region, and therefore the seventh fet M7, the eighth fet M8, the ninth fet M9, and the tenth fet M10 can be used as the class AB intermediate bias transistors. At this time, the gate voltages of the seventeenth fet M17 and the eighteenth fet M18 are the voltages of the node 3 and the node 4, and the voltages are biased. The multiplexing unit 121 is a class AB operational amplifier with a folded cascode. The third capacitor C3 and the fourth capacitor C4 electrically connected to the multiplexing unit 121 are inactive, the first comparator 131 and the second comparator 132 are in an off state, and the first driver 141 and the second driver 142 are in an off state. The seventeenth fet M17 and the nineteenth fet M19 in the internal output tube of the multiplexing unit 121 functioning as an operational amplifier are connected in parallel to the thirty-third fet M33 and the thirty-fourth fet M34, respectively. The eighteenth fet M18 and the twentieth fet M20 in the internal output tube of the multiplexing unit 121 functioning as an operational amplifier are connected in parallel with the thirty-first fet M31 and the thirty-second fet M32, respectively. At this time, the thirty-third fet M33, the thirty-fourth fet M34, the thirty-first fet M31, and the thirty-second fet M32 are biased by the node 3, the node 1, the node 4, and the node 2 shown in fig. 3, respectively, so as to drive the load horn. Therefore, the novel audio power amplifier can operate in an AB type power amplification mode.

In addition, when the fifth switch SW5 and the seventh switch SW7 are turned off and the sixth switch SW6 and the eighth switch SW8 are turned on, the gate voltages of the seventeenth fet M17 and the eighteenth fet M18 are not the first bias voltage VBIAS1, but are biased by the voltages at the node 3 and the node 4 positions. When the first switch SW1 to the fourth switch SW4 are matched, the second switch SW2 and the third switch SW3 are closed, and the first switch SW1 and the fourth switch SW4 are opened, the seventeenth fet M17 and the eighteenth fet M18 are not used as current mirrors, but used as class AB upper output tubes.

The invention realizes that the folded cascade two-stage operational amplifier with the output stage is converted into the AB operational amplifier with the folded cascade structure by additionally arranging a first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4, a fifth switch SW5, a sixth switch SW6, a seventh switch SW7, an eighth switch SW8, a seventh field effect transistor M7, an eighth field effect transistor M8, a ninth field effect transistor M9 and a tenth field effect transistor M10 in the existing folded cascade operational amplifier and changing the gate bias voltages of the seventh field effect transistor M7, the eighth field effect transistor M8, the ninth field effect transistor M9 and the tenth field effect transistor M10 through the switching action of the ninth switch SW9 to the sixteenth switch SW16 shown in the figure 2.

Further, by providing the seventh fet M7, the eighth fet M8, the ninth fet M9, and the tenth fet M10, voltages at the

nodes

3, 4, 1, and 2 can bias the seventeenth fet M17, the eighteenth fet M18, the nineteenth fet M19, and the twentieth fet M20, respectively, so that the seventeenth fet M17, the eighteenth fet M18, the nineteenth fet M19, and the twentieth fet M20 operate in the AB class operational amplifier state. When the state of the D-class operational amplifier is switched to the state of the AB-class operational amplifier, the output stage of the second unit is not a common source stage amplifier, but a AB-class amplifier. When the D-type operation mode is performed before switching, the gate voltages of the seventh fet M7, the eighth fet M8, the ninth fet M9, and the tenth fet M10 are the power supply voltage or the ground level. The voltage at node 3 is approximately equal to the voltage at node 1 and the voltage at node 4 is approximately equal to the voltage at node 2. When the switched mode is the class AB operating mode, the gate voltages of the seventh fet M7, the eighth fet M8, the ninth fet M9, and the tenth fet M10 need to be adjusted to the fifth bias voltage VBIAS5 and the sixth bias voltage VBIAS6, respectively. The voltage at the node 3 is not equal to the voltage at the node 1, and the voltage at the node 4 is not equal to the voltage at the node 2, so that the seventeenth fet M17, the eighteenth fet M18, the nineteenth fet M19 and the twentieth fet M20 can operate in the class AB amplification state.

Therefore, the novel audio power amplifier multiplexes the integrator in the class D power amplifier circuit and the operational amplifier in the class AB power amplifier circuit into a folding cascode circuit. Furthermore, under the condition of utilizing the characteristics of high output impedance, high gain and easy compensation of the folding cascade and greatly improving the performance, the area of the chip is saved, the cost of the chip is reduced, the workload of the layout design of the integrated circuit can be reduced, and the design time is saved.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A novel audio power amplifier, comprising:

a first operational amplifier module;

the multiplexing module is electrically connected with the first operational amplifier module and comprises a multiplexing circuit, a first group of switches and a second group of switches, and the multiplexing circuit is electrically connected with the first group of switches and the second group of switches respectively;

the comparison module is electrically connected with the multiplexing module;

the driving module is electrically connected with the comparison module; and

the load module is electrically connected with the driving module; wherein,

when the first group of switches is closed and the second group of switches is open, the output end of the multiplexing circuit is electrically connected to the comparison module, so that the multiplexing module is switched to be an integration module, and the novel audio power amplifier operates in a class D power amplifier mode;

when the first group of switches is off and the second group of switches is on, the output end of the multiplexing circuit is electrically connected to the load module, so that the multiplexing module is switched to be used as a second operational amplifier module, and the novel audio power amplifier operates in an AB type power amplification mode.

2. The novel audio power amplifier of claim 1, wherein the first operational amplifier module comprises: the circuit comprises a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor and a first operational amplifier; one end of the first capacitor receives the positive input end, and the other end of the first capacitor is electrically connected with one end of the first resistor; one end of the second capacitor receives the negative input end, and the other end of the second capacitor is electrically connected with one end of the second resistor; the other end of the first resistor is electrically connected to one end of the third resistor and the positive input end of the first operational amplifier respectively; the other end of the second resistor is electrically connected to one end of the fourth resistor and the negative input end of the first operational amplifier respectively; the other end of the third resistor is electrically connected to the negative output end of the first operational amplifier, and the other end of the fourth resistor is electrically connected to the positive output end of the first operational amplifier.

3. The novel audio power amplifier of claim 2, wherein the multiplexing circuit comprises: the first resistor, the second resistor, the third resistor, the fourth resistor, the seventh resistor and the eighth resistor are connected in series; one end of the fifth resistor is electrically connected to the other end of the third resistor and the negative output end of the first operational amplifier, and the other end of the fifth resistor is electrically connected to one end of the seventh resistor, one end of the third capacitor, and the positive input end of the multiplexing unit; one end of the sixth resistor is electrically connected to the other end of the fourth resistor and the positive output end of the first operational amplifier, and the other end of the sixth resistor is electrically connected to one end of the eighth resistor, one end of the fourth capacitor and the negative input end of the multiplexing unit; the other end of the third capacitor is electrically connected to a ninth switch in the first group of switches, and the ninth switch is electrically connected to the negative output end of the multiplexing unit; the other end of the fourth capacitor is electrically connected to a tenth switch in the first group of switches, and the tenth switch is electrically connected to the positive output end of the multiplexing unit.

4. The novel audio power amplifier of claim 3, wherein the comparison module comprises: a first comparator and a second comparator; the positive input end of the first comparator is electrically connected to the negative output end of the multiplexing unit, the positive input end of the second comparator is electrically connected to the positive output end of the multiplexing unit, and the negative input end of the first comparator and the negative input end of the second comparator receive a triangular wave signal.

5. The novel audio power amplifier of claim 4, wherein the driver module comprises: the first driver, the second driver, the first output pair of tubes and the second output pair of tubes; the input end of the first driver is electrically connected to the output end of the first comparator, and the input end of the second driver is electrically connected to the output end of the second comparator; the first output pair transistors comprise a thirty-first field effect transistor and a thirty-second field effect transistor; the second output pair transistor comprises a thirty-third field effect transistor and a thirty-fourth field effect transistor; a source electrode of the thirty-first field effect transistor receives a power supply voltage, a grid electrode of the thirty-first field effect transistor is electrically connected to the first output end of the first driver, and a drain electrode of the thirty-first field effect transistor is electrically connected to a drain electrode of the thirty-second field effect transistor; the grid electrode of the thirty-second field effect transistor is electrically connected to the second output end of the first driver, and the source electrode of the thirty-second field effect transistor is grounded; a source electrode of the thirty-third field effect transistor receives a power supply voltage, a grid electrode of the thirty-third field effect transistor is electrically connected to the first output end of the second driver, and a drain electrode of the thirty-third field effect transistor is electrically connected to a drain electrode of the thirty-fourth field effect transistor; the gate of the thirty-fourth field effect transistor is electrically connected to the second output end of the second driver, and the source of the thirty-fourth field effect transistor is grounded.

6. The novel audio power amplifier of claim 5, wherein the load module comprises a load connected to a common node of the thirty-first and thirty-second fets and a common node of the thirty-third and thirty-fourth fets.

7. The novel audio power amplifier of claim 6, wherein the first set of switches comprises a ninth switch and a tenth switch, the ninth switch is electrically connected to the other end of the third capacitor and the negative output terminal of the multiplexing unit, respectively, and the tenth switch is electrically connected to the other end of the fourth capacitor and the positive output terminal of the multiplexing unit, respectively; the second set of switches comprises: an eleventh switch, a twelfth switch, a thirteenth switch, a fourteenth switch, a fifteenth switch, and a sixteenth switch; the eleventh switch is electrically connected to a common node of the multiplexing unit, the ninth switch, the positive input terminal of the first comparator, the thirty-first field effect transistor, and the thirty-second field effect transistor, respectively; the twelfth switch is electrically connected to the multiplexing unit and the grid electrode of the thirty-first field effect transistor respectively; the thirteenth switch is electrically connected to the multiplexing unit and the grid of the thirty-second field effect transistor respectively; the fourteenth switch is electrically connected to the multiplexing unit and the gate of the thirty-third field effect transistor respectively; the fifteenth switch is electrically connected to the multiplexing unit and the grid electrode of the thirty-fourth field effect transistor respectively; the sixteenth switch is electrically connected to the multiplexing unit, the tenth switch, the positive input end of the second comparator, and a common node of the thirty-third and thirty-fourth field effect transistors, respectively.

8. The novel audio power amplifier of claim 3, wherein the multiplexing unit further comprises: the device comprises a first unit, a second unit and a third unit, wherein the second unit is electrically connected to the first unit, and the third unit is electrically connected to the second unit; the first unit includes: the first field effect transistor, the second field effect transistor, the third field effect transistor, the fourth field effect transistor, the fifth field effect transistor, the sixth field effect transistor, the seventh field effect transistor, the eighth field effect transistor, the ninth field effect transistor, the tenth field effect transistor, the eleventh field effect transistor, the twelfth field effect transistor, the thirteenth field effect transistor, the fourteenth field effect transistor, the fifteenth field effect transistor, the sixteenth field effect transistor, the first switch, the second switch, the third switch and the fourth switch; the grid electrode of the first field effect tube is electrically connected to the negative input end of the multiplexing unit, the source electrode of the first field effect tube is electrically connected to the drain electrode of the sixteenth field effect tube and the source electrode of the second field effect tube respectively, and the drain electrode of the first field effect tube is electrically connected to the drain electrode of the thirteenth field effect tube and the source electrode of the eleventh field effect tube respectively; a grid electrode of the second field effect transistor is electrically connected to the positive input end of the multiplexing unit, a source electrode of the second field effect transistor is electrically connected to a drain electrode of the sixteenth field effect transistor, and drain electrodes of the second field effect transistor are respectively and electrically connected to a drain electrode of the fourteenth field effect transistor and a source electrode of the twelfth field effect transistor; a source electrode of the fifteenth field effect transistor receives a power supply voltage, a grid electrode of the fifteenth field effect transistor is respectively and electrically connected to a grid electrode of the third field effect transistor and a grid electrode of the fourth field effect transistor and receives a first bias voltage, and a drain electrode of the fifteenth field effect transistor is electrically connected to a source electrode of the sixteenth field effect transistor; the grid electrode of the sixteenth field effect transistor is respectively and electrically connected to the grid electrode of the fifth field effect transistor and the grid electrode of the sixth field effect transistor and receives a second bias voltage; the source electrode of the third field effect transistor receives a power supply voltage, the grid electrode of the third field effect transistor is electrically connected to the grid electrode of the fourth field effect transistor, and the drain electrode of the third field effect transistor is electrically connected to the source electrode of the fifth field effect transistor; a grid electrode of the fifth field effect transistor is electrically connected to a grid electrode of the sixth field effect transistor, and a drain electrode of the fifth field effect transistor is respectively and electrically connected with a source electrode of the seventh field effect transistor and a drain electrode of the eighth field effect transistor; a source electrode of the seventh field effect transistor is electrically connected to a drain electrode of the eighth field effect transistor, a gate electrode of the seventh field effect transistor is electrically connected to one end of the third switch and one end of the fourth switch respectively, and a drain electrode of the seventh field effect transistor is electrically connected to a source electrode of the eighth field effect transistor and a drain electrode of the eleventh field effect transistor respectively; a grid electrode of the eighth field effect transistor is electrically connected to one end of the first switch, one end of the second switch and a grid electrode of the ninth field effect transistor respectively, and a source electrode of the eighth field effect transistor is electrically connected to a drain electrode of the eleventh field effect transistor; the grid electrode of the eleventh field effect transistor is electrically connected to the grid electrode of the twelfth field effect transistor and receives a third bias voltage, and the source electrode of the eleventh field effect transistor is electrically connected to the drain electrode of the thirteenth field effect transistor; the grid electrode of the thirteenth field effect transistor is electrically connected to the grid electrode of the fourteenth field effect transistor and receives a fourth bias voltage, and the source electrode of the thirteenth field effect transistor is grounded; a source electrode of the fourth field effect transistor receives a power supply voltage, a grid electrode of the fourth field effect transistor receives a first bias voltage, and a drain electrode of the fourth field effect transistor is electrically connected to a source electrode of the sixth field effect transistor; a grid electrode of the sixth field effect transistor receives a second bias voltage, and a drain electrode of the sixth field effect transistor is electrically connected to a drain electrode of the ninth field effect transistor and a source electrode of the tenth field effect transistor respectively; a drain electrode of the ninth field effect transistor is electrically connected to a source electrode of the tenth field effect transistor, a gate electrode of the ninth field effect transistor is electrically connected to one end of the first switch and one end of the second switch respectively, and a source electrode of the ninth field effect transistor is electrically connected to a drain electrode of the tenth field effect transistor and a drain electrode of the twelfth field effect transistor respectively; a grid electrode of the tenth field effect transistor is electrically connected to one end of the third switch and one end of the fourth switch respectively, and a drain electrode of the tenth field effect transistor is electrically connected to a drain electrode of the twelfth field effect transistor; a grid electrode of the twelfth field effect transistor receives a third bias voltage, and a source electrode of the twelfth field effect transistor is electrically connected to a drain electrode of the fourteenth field effect transistor; a grid electrode of the fourteenth field effect transistor receives a fourth bias voltage, and a source electrode of the fourteenth field effect transistor is grounded; the other end of the first switch receives a power supply voltage, the other end of the second switch receives a fifth bias voltage, the other end of the third switch receives a sixth bias voltage, and the other end of the fourth switch is grounded.

9. The novel audio power amplifier of claim 8, wherein the second unit comprises: a seventeenth field effect transistor, an eighteenth field effect transistor, a nineteenth field effect transistor, a twentieth field effect transistor, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a fifth capacitor and a sixth capacitor; a source electrode of the seventeenth field-effect transistor receives a power supply voltage, a gate electrode of the seventeenth field-effect transistor is electrically connected to one end of the fifth switch and one end of the sixth switch respectively, and a drain electrode of the seventeenth field-effect transistor is electrically connected to one end of the fifth capacitor and a drain electrode of the nineteenth field-effect transistor respectively; the drain electrode of the nineteenth field effect transistor is electrically connected to one end of the fifth capacitor, the gate electrode of the nineteenth field effect transistor is electrically connected to the other end of the fifth capacitor, and the source electrode of the nineteenth field effect transistor is grounded; a source electrode of the eighteenth field effect transistor receives a power supply voltage, a grid electrode of the eighteenth field effect transistor is electrically connected to one end of the seventh switch and one end of the eighth switch respectively, and a drain electrode of the eighteenth field effect transistor is electrically connected to one end of the sixth capacitor and the drain electrode of the twentieth field effect transistor respectively; the drain of the twentieth field effect transistor is electrically connected to one end of the sixth capacitor, the gate of the twentieth field effect transistor is electrically connected to the other end of the sixth capacitor, and the source of the twentieth field effect transistor is grounded; the other end of the fifth switch is electrically connected to the grid electrode of the fourth field effect transistor, the other end of the sixth switch is electrically connected to the drain electrode of the fifth field effect transistor, the other end of the seventh switch is electrically connected to the grid electrode of the fourth field effect transistor, and the other end of the eighth switch is electrically connected to the drain electrode of the sixth field effect transistor; the grid electrode of the nineteenth field effect transistor is electrically connected to the drain electrode of the eleventh field effect transistor, and the grid electrode of the twentieth field effect transistor is electrically connected to the drain electrode of the twelfth field effect transistor.

10. The novel audio power amplifier of claim 8, wherein the third unit comprises: a twenty-first field effect transistor, a twenty-second field effect transistor, a twenty-third field effect transistor, a twenty-fourth field effect transistor, a twenty-fifth field effect transistor, a twenty-sixth field effect transistor, a twenty-seventh field effect transistor, a twenty-eighth field effect transistor, a ninth resistor and a tenth resistor; a source electrode of the twenty-first field effect transistor receives a power supply voltage, a grid electrode of the twenty-first field effect transistor receives a first bias voltage, and a drain electrode of the twenty-first field effect transistor is electrically connected to a source electrode of the twenty-second field effect transistor; a grid electrode of the twenty-second field effect transistor receives a second bias voltage, and a drain electrode of the twenty-second field effect transistor is electrically connected to a source electrode of the twenty-third field effect transistor and a source electrode of the twenty-fourth field effect transistor respectively; a grid electrode of the twenty-third field effect transistor is electrically connected to one end of the ninth resistor and one end of the tenth resistor respectively, and a drain electrode of the twenty-third field effect transistor is electrically connected to a drain electrode of the twenty-fifth field effect transistor and a grid electrode of the twenty-seventh field effect transistor respectively; a grid electrode of the twenty-fifth field effect transistor receives a third bias voltage, and a source electrode of the twenty-fifth field effect transistor is electrically connected to a drain electrode of the twenty-seventh field effect transistor;

a grid electrode of the twenty-seventh field effect transistor receives a fourth bias voltage, and a source electrode of the twenty-seventh field effect transistor is grounded; a source electrode of the twenty-fourth field effect transistor is electrically connected to a source electrode of the twenty-third field effect transistor, a gate electrode of the twenty-fourth field effect transistor receives a reference voltage, and a drain electrode of the twenty-fourth field effect transistor is electrically connected to a drain electrode of the twenty-sixth field effect transistor and a gate electrode of the twenty-eighth field effect transistor respectively; a grid electrode of the twenty-sixth field effect transistor receives a third bias voltage, and a source electrode of the twenty-sixth field effect transistor is electrically connected to a drain electrode of the twenty-eighth field effect transistor; and the source electrode of the twenty-eighth field effect transistor is grounded.