KR20160137803A

KR20160137803A - Low Drop Out Voltage Regulator

Info

Publication number: KR20160137803A
Application number: KR1020150071413A
Authority: KR
Inventors: 구용서
Original assignee: 단국대학교 산학협력단
Priority date: 2015-05-22
Filing date: 2015-05-22
Publication date: 2016-12-01

Abstract

A low dropout voltage regulator is disclosed that effectively prevents overshoot and undershoot of an output signal and enables stable regulation operation. A low dropout voltage regulator capable of improving the driving ability of the pass transistor by forming an additional feedback loop in the feedback path of the voltage regulator and controlling the gate voltage of the pass transistor when overshoot and undershoot of the output signal occur.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a low dropout voltage regulator,

The present invention relates to a voltage regulator, and more particularly, to a low dropout voltage regulator that senses a feedback voltage using a feedback voltage detector.

In general, the size and weight of a battery have been decreasing in accordance with the recent trend of compact and lightweight portable devices. However, portable devices are continuously required to be multifunctional and highly functional, which complicates the internal system and also demands various power supply voltages. If each chip is used according to the power supply voltage required by each system, it takes up a lot of area, which makes it difficult to miniaturize and lighten the portable device. Accordingly, the importance of PMIC (Power Management IC), which is a circuit for managing limited battery power, is increasing. In addition to basic functions such as control function and power conversion function to distribute to the system according to the system, the PMIC is implemented as a single chip on the power source monitor and management functions, various kinds of output power supply function of the system, and high efficiency power conversion efficiency management function And it is expanding to play a role to control energy efficiency and system stability and reliability in the role of simply regulating and delivering power. In addition, PMIC technology has been solving the voltage required for each application with each discrete. It is becoming a key component in the battery-based portable information terminal due to the advantages of space saving obtained by dividing each device into one chip and cost reduction.

Recently, studies have been made to reduce the area of the printed circuit board (PCB) by removing the output capacitor of the LDO (Low Drop Out) regulator. Particularly, a transient response of a capacitor-free LDO regulator Various methods for improving the response characteristics have been proposed. However, existing methods for mitigating the overshoot and undershoot of the output voltage are complicated in configuration and have many additional circuits.

Korean Patent No. 10-1432494

The present invention relates to a low dropout voltage regulator capable of improving regulation performance by using a feedback voltage detector. That is, a further object of the present invention is to provide a low dropout voltage regulator that does not use an external capacitor by adding an additional feedback path to the feedback path of the regulator to control the gate voltage of the pass transistor and temporally change the bandwidth of the error amplifier.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a reference voltage generator for forming a reference voltage; An error amplifier for receiving the reference voltage through a negative input terminal and receiving a feedback voltage via a positive input terminal to amplify a difference between the feedback voltage and the reference voltage; A pass transistor for generating a drive current according to an output signal of the error amplifier; And a voltage distributor for forming an output signal according to the drive current and generating the feedback voltage through a resistor connection, wherein the overshoot and undershoot of the output stage are detected by the feedback voltage, And a feedback voltage sensing unit for controlling the gate voltage.

Wherein the feedback voltage sensing unit comprises: an overshoot sensing unit for sensing an overshoot of the output stage and controlling a gate voltage of the pass transistor; And an undershoot sensing unit for sensing an undershoot of the output stage and controlling a gate voltage of the pass transistor.

The overshoot sensing unit may include: a first inverter sensing the overshoot; And a first transistor for controlling the gate voltage of the pass transistor by the first inverter signal.

The undershoot sensing unit may include: a second inverter sensing the undershoot; And a second transistor for controlling the gate voltage of the pass transistor by the second inverter signal.

The first transistor may be a PMOS transistor.

The second transistor may be an NMOS transistor.

The source of the first transistor may be coupled to the reference voltage generator.

The source of the second transistor may be coupled to ground.

The overshoot sensing unit may turn on the first transistor to receive a current through the reference voltage generator when the overshoot occurs and increase the gate voltage of the pass transistor by applying the supplied current to the gate of the pass transistor have.

The undershoot sensing unit may turn on the second transistor to reduce the current flowing through the pass transistor through the ground to reduce the gate voltage of the pass transistor when the undershoot occurs.

The overshoot sensing unit and the undershoot sensing unit may operate independently of each other when the overshoot or the undershoot is generated.

According to the present invention, by adding a feedback path in which a feedback voltage detector is formed in a feedback path of a low dropout regulator, overshoot and undershoot of the output voltage can be effectively prevented, and an improved regulation performance can be obtained.

In addition, since the external capacitor is not used by temporarily changing the bandwidth of the error amplifier, the size of the PCB can be reduced.

The technical effects of the present invention are not limited to those mentioned above, and other technical effects not mentioned can be clearly understood by those skilled in the art from the following description.

1 is a block diagram illustrating a low dropout voltage regulator in accordance with a preferred embodiment of the present invention.
2 is a circuit diagram showing a feedback voltage sensing unit according to a preferred embodiment of the present invention.
3 is a circuit diagram for explaining the operation of the overshoot sensing unit according to the preferred embodiment of the present invention.
4 is a circuit diagram illustrating an operation of the undershoot sensing unit according to the preferred embodiment of the present invention.
5 is a detailed circuit diagram of a low dropout voltage regulator of the present invention.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and similarities. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Referring to the accompanying drawings, the same or corresponding components are denoted by the same reference numerals, .

Example

1 is a block diagram illustrating a low dropout voltage regulator in accordance with a preferred embodiment of the present invention.

1, the low dropout voltage regulator according to the present invention includes a reference voltage generator 100, an error amplifier 110, a pass transistor Mpass, a voltage distributor 120, and a feedback voltage detector 130 .

The reference voltage generator 100 generates a reference voltage Vref of a predetermined level and supplies the reference voltage Vref to the negative input terminal of the error amplifier 110.

The error amplifier 110 receives the reference voltage Vref through the negative input terminal and receives the feedback voltage FB through the positive input terminal to output the difference between the feedback voltage FB and the reference voltage Vref Compare. The error amplifier 110 amplifies the compared voltage difference, applies the amplified signal to the input terminal of the pass transistor Mpass, and the output signal of the error amplifier 110 applied to the pass transistor Mpass passes through the pass transistor Mpass. (Mpass). Since the output signal of the error amplifier 110 is applied to the gate terminal of the pass transistor Mpass, the output signal of the error amplifier 110 applied to the gate terminal of the error amplifier 110 The driving current is determined.

The pass transistor Mpass serves to keep the output voltage of the voltage regulator constant. An input terminal of the pass transistor Mpass is connected to an output terminal of the error amplifier 110 and is supplied with an output voltage outputted from the error amplifier 110. Therefore, the output signal of the error amplifier 110 applied to the pass transistor Mpass determines the drive current flowing through the pass transistor Mpass. Preferably, the pass transistor Mpass may be a PMOS transistor. When the pass transistor Mpass is composed of a PMOS transistor, the output signal of the error amplifier 110 is applied to the gate terminal of the pass transistor Mpass. The drive current of the pass transistor Mpass which is the pass transistor Mpass is determined according to the output signal of the error amplifier 110 applied to the gate terminal. That is, the driving current flowing through the pass transistor Mpass is adjusted according to the output voltage of the error amplifier 110, and the voltage difference between the output voltage and the reference voltage Vref is reduced. Accordingly, the voltage regulators can have the output voltage having the same voltage magnitude and the reference voltage Vref.

The voltage divider 120 may include a first resistor R1 and a second resistor R2. The first resistor R1 and the second resistor R2 are connected between the output terminal Vout of the voltage regulator and the ground terminal to form an output signal according to the driving current and control the magnitude of the output signal. The positive input terminal of the error amplifier 110 is connected between the first resistor R1 and the second resistor R2 of the voltage divider 120 and is connected to the feedback voltage FB generated by the voltage divider 120 ).

The feedback voltage sensing unit 130 receives the feedback voltage FB generated by the voltage divider 120 and senses an overshoot and an undershoot of the feedback voltage FB, And applies a signal to the gate of the pass transistor Mpass to control the gate voltage of the pass transistor Mpass.

The detailed construction and operation of the feedback voltage sensing unit 130 will be described in detail with reference to FIGS. 2 to 4 below.

2 is a circuit diagram showing a feedback voltage sensing unit according to a preferred embodiment of the present invention.

2, the feedback voltage sensing unit 130 according to the preferred embodiment of the present invention includes an overshoot sensing unit 131 for sensing an overshoot of the output stage Vout and controlling a gate voltage of the pass transistor Mpass, And an undershoot sensing unit 132 for sensing the undershoot of the output stage Vout and controlling the gate voltage of the pass transistor Mpass.

The overshoot sensing unit 131 may include a first inverter INV1 for sensing an overshoot and a first transistor M1 for controlling a gate voltage of the pass transistor Mpass by a first inverter INV1 signal. have.

The first inverter INV1 of the overshoot sensing unit 131 receives the feedback voltage FB and senses when an overshoot occurs in the feedback voltage FB to output a signal to the gate of the first transistor M1 .

The source of the first transistor M1 is connected to the reference voltage generator 100 and the drain of the first transistor M1 is connected to the first node N1 connected to the gate Pgate of the pass transistor Mpass, INV1). The first transistor M1 may preferably be a PMOS transistor. The first transistor M1 receives a signal from the first inverter INV1 to the gate depending on whether overshoot occurs or not, and controls the gate voltage of the pass transistor Mpass through on / off operation of the transistor.

The undershoot sensing unit 132 may include a second inverter INV1 for sensing an undershoot and a second transistor M2 for controlling a gate voltage of the pass transistor Mpass by a second inverter INV1 signal. have.

The second inverter INV1 of the undershoot sensing unit 132 receives the feedback voltage FB and senses an undershoot when the feedback voltage FB is generated so as to output a signal to the gate of the second transistor M2 . The source of the second transistor M2 is connected to the ground, the drain of the second transistor M2 is connected to the first node N1 connected to the gate of the pass transistor Mpass, and the gate thereof is connected to the second inverter INV1. The second transistor M2 may be an NMOS transistor. The second transistor M2 receives a sense signal from the second inverter INV1 to the gate according to whether undershoot occurs or not, and controls the gate voltage of the pass transistor Mpass through on / off operation of the transistor.

FIG. 3 is a circuit diagram for explaining the operation of the overshoot sensing unit according to the preferred embodiment of the present invention, and FIG. 4 is a circuit diagram for explaining the operation of the undershoot sensing unit according to the preferred embodiment of the present invention.

3 and 4, the overshoot sensing unit 131 according to the preferred embodiment of the present invention generates a high signal by the first inverter INV1 during normal operation as shown in FIG. 3, M1) in the turn-off state. However, when an overshoot occurs in the output stage Vout, the first inverter INV1 senses an overshoot of the output stage Vout through the feedback voltage FB and generates a low signal. The Low signal of the first inverter INV1 is applied to the gate of the first transistor M1, and the first transistor M1 receiving the Low signal is turned on. When the first transistor M1 is turned on, an additional current is supplied to the first node N1 connected to the gate Pgate of the pass transistor Mpass by the source of the first transistor M1 connected to the reference voltage generator 100 Thereby temporarily raising the gate (Pgate) voltage of the pass transistor Mpass. The pass transistor (Mpass) whose gate voltage is increased can stabilize the output voltage by reducing the amount of current flowing to the output terminal (Vout).

The undershoot sensing unit 132 generates a low signal by the second inverter INV1 to maintain the second transistor M2 in a turned off state in a normal operating state as shown in FIG. However, when an undershoot occurs in the output stage Vout, the second inverter INV1 detects the undershoot of the output stage Vout through the feedback voltage FB and generates a high signal. The high signal of the second inverter INV1 is applied to the gate of the second transistor M2, and the second transistor M2 receiving the high signal is turned on. When the second transistor M2 is turned on, the current of the first node N1 connected to the gate Pgate of the pass transistor Mpass is grounded by the source of the second transistor M2 connected to the ground, (Pgate) voltage of the transistor Mpass temporarily decreases. The pass transistor (Mpass) whose gate voltage is reduced can stabilize the output voltage by increasing the amount of current flowing to the output terminal (Vout).

As described above, the additional feedback path is further formed through the overshoot sensing unit 131 and the undershoot sensing unit 132 of the feedback voltage sensing unit 130 according to the present invention, so that the stable regulation operation of the voltage regulator It is possible. When the voltage regulator is operating normally, the inverter of the overshoot sensing unit 131 generates a high signal and the inverter of the undershoot sensing unit 132 generates a low signal. , The feedback sensing circuit is turned off to reduce additional current consumption, and when the overshoot or undershoot occurs, the overshoot sensing unit 131 and the undershoot sensing unit 132 operate independently and the voltage regulator stably operates can do.

5 is a detailed circuit diagram of a low dropout voltage regulator of the present invention.

5, the low dropout voltage regulator according to the present invention includes a first bias unit 111, a second bias unit 112, an input stage 113, an output stage 114, and a feedback voltage sensing unit 130 ). Also, the error amplifier 110 according to the present invention may be formed with a folded cascode structure. The folded cords structure is suitable for fast settling times and high gain, and can achieve high voltage gain and frequency characteristics at the same time.

The first bias unit 111 forms a bias current through the reference bias current source Iref. The formed bias current flows through the third transistor M3 and the fourth transistor M4. In addition, the current mirroring operation is performed to replicate the current flowing through the fifth transistor M5 and the sixth transistor M6. In the current mirroring process, the bias voltage of the second node N2, to which the gate terminals of the third transistor M3 and the fifth transistor M5 are commonly connected, is set, and the fourth transistor M4 and the sixth transistor M5 The bias voltage of the third node N3, to which the gate terminals of the transistors M6 and M6 are commonly connected, is also set.

A bias current copied from the fifth transistor M5 and the sixth transistor M6 flows to the seventh transistor M7 of the transistors of the second bias unit 112. [ The bias current flowing through the ninth transistor M9 through the seventh transistor M7 and the eighth transistor M8 having the current mirror configuration is determined and the voltage at the gate terminal of the ninth transistor M9 is also determined.

The voltage of the gate terminal of the tenth transistor M10 of the second bias unit 112 is equal to the bias voltage of the second node N2 of the first bias unit 111. [ Whereby the bias current flowing through the tenth transistor M10 is determined. Also, the voltage of the third node N3 is applied to the gate terminal of the eleventh transistor M11. The voltage at the drain terminal of the tenth transistor M10 or the voltage at the source terminal of the eleventh transistor M11 may be determined. The bias current generated in the tenth transistor M10 flows through the twelfth transistor M12 and the thirteenth transistor M13 and the gate voltages of the twelfth transistor M12 and the thirteenth transistor M13 are determined.

The bias current of the input stage 113 is determined by the voltage of the second node N2 of the first bias unit 111 and the voltage of the third node N3. This means that the bias current of the input stage 113 is determined by the voltage generated in the first bias portion 111. [ The voltage of the second node N2 is applied to the gate terminal of the fourteenth transistor M14 and the voltage of the third node N3 is applied to the gate terminal of the fifteenth transistor M15. The current flowing through the fourteenth transistor (M14) is determined by the voltage of the second node (N2) applied to the gate terminal of the fourteenth transistor (M14). The voltage of the source terminal of the fifteenth transistor M15 is determined by the bias current flowing through the fourteenth transistor M14. The bias current flowing through the formed fourteenth transistor M14 and the fifteenth transistor M15 branches to the sixteenth transistor M16 and the seventeenth transistor M17 and flows through the eighteenth transistor M18 and the nineteenth transistor M19 ).

The current flowing through the eighteenth transistor M18 of the output stage 114 is equal to the current flowing through the sixteenth transistor M16 and the current flowing through the nineteenth transistor M19 is equal to the current flowing through the seventeenth transistor M17 . The gate terminal voltages of the seventeenth transistor M19 and the seventeenth transistor M19 commonly connected by the bias current flowing through the respective transistors are determined. The voltage of the gate terminal of the ninth transistor M9 of the second bias section 112 and the voltage of the gate terminal of the twelfth transistor M12 and the thirteenth transistor M13 of the second bias section 112 The bias current flowing through the twentieth transistor M20, the twenty-first transistor M21, and the twenty-second transistor M22 is also determined. Therefore, the bias current flowing through the eighteenth transistor M18 is the sum of the bias current flowing through the sixteenth transistor M16 of the input stage and the bias current flowing through the twenty second transistor M22, The voltage of the gate terminal of the transistor M18 is determined. This applies equally to the 23rd transistor M23, the 24th transistor M24, the 25th transistor M25 and the 19th transistor M19. As a result, the bias current flowing through the output stage 114 is determined by the gate voltage of the transistors formed in the second bias portion 112.

A positive input signal INP and a negative input signal INN are applied to the input stage 113. The positive input signal INP is applied to the gate terminal of the sixteenth transistor M16 and the negative input signal INN is applied to the gate terminal of the seventeenth transistor M17. The positive input signal INP may be the feedback voltage FB generated by the voltage divider 120 and the negative input signal INN may be the reference voltage Vref of the reference voltage generator 100 . In addition, the sixteenth transistor M16 and the seventeenth transistor M17 function as a common source amplifier. In other words, it acts as a common source amplifier for small signal inputs in differential mode.

The output signal of the sixteenth transistor M16 is applied to the source terminal of the twenty-second transistor M22. The twenty-second transistor M22 takes the configuration of a common gate amplifier. The signal amplified in the common gate amplifier is applied to the gate terminal of the nineteenth transistor M19 having the configuration of the common source amplifier and the signal amplified in the common source amplifier of the nineteenth transistor M19 is applied to the gate terminal of the common gate amplifier And is output to the output terminal Vout through the twenty-fifth transistor M25.

The output signal of the seventeenth transistor M17 having the configuration of the common source amplifier is applied to the source terminal of the twenty-fifth transistor M25 having the common gate amplifier configuration, amplified and transmitted to the output terminal Vout.

Thus, the positive input signal INP and the negative input signal INN are amplified in the differential mode through the serial configuration of the common source amplifier and the common gate amplifier to form the output signal.

The feedback voltage sensing unit 130 may include an overshoot sensing unit 131 and an undershoot sensing unit 132.

The overshoot sensing unit 131 may include a first inverter INV1 for sensing an overshoot and a first transistor M1 for controlling a gate voltage of the pass transistor Mpass by a first inverter INV1 signal. And detects the overshoot of the output stage to control the gate voltage of the pass transistor Mpass. In other words, the first inverter INV1 of the overshoot sensing unit 131 receives the feedback voltage FB and senses when an overshoot occurs in the feedback voltage FB and outputs it to the gate of the first transistor M1 Signal. The first transistor M1 receiving the overshoot signal is turned on and supplies an additional current to the first node N1 connected to the gate of the pass transistor Mpass to temporarily raise the gate voltage of the pass transistor Mpass. The pass transistor (Mpass) whose gate voltage is increased can stabilize the output voltage by reducing the amount of current flowing to the output terminal (Vout).

The undershoot sensing unit 132 may include a second inverter INV1 for sensing an undershoot and a second transistor M2 for controlling a gate voltage of the pass transistor Mpass by a second inverter INV1 signal. And detects the undershoot of the output terminal Vout to control the gate voltage of the pass transistor Mpass. That is, the second inverter INV1 of the undershoot sensing unit 132 receives the feedback voltage FB and senses when an undershoot occurs in the feedback voltage FB to be supplied to the gate of the second transistor M2 Signal. The second transistor M2 receiving the undershoot signal is turned on to flow the current of the first node N1 connected to the gate of the pass transistor Mpass to the ground to temporarily decrease the gate voltage of the pass transistor Mpass . The pass transistor Mpass having a reduced gate voltage can stabilize the output voltage by increasing the amount of current flowing to the output terminal Vout.

Also, when an undershoot or overshoot occurs in the output voltage and is fed back, the first transistor (M1) or the second transistor (M2) is temporarily turned on to lower the output impedance of the error amplifier (110). Therefore, the bandwidth of the error amplifier 110 can be temporarily extended while the first transistor M1 or the second transistor M2 is kept turned on to prevent the oscillation of the output voltage, and the overshoot or undershoot can be prevented The generated output voltage can be more stably controlled.

As described above, the low dropout voltage regulator according to the present invention effectively prevents the overshoot and undershoot of the output voltage by adding the feedback path in which the feedback voltage sensing unit 130 is formed in the feedback path of the regulator, Can be obtained.

In addition, since the bandwidth of the error amplifier 110 is temporarily expanded by the operation of the feedback voltage sensing unit 130, oscillation of the output voltage can be prevented. Therefore, a stable low dropout voltage Regulators can be implemented.

It should be noted that the embodiments of the present invention disclosed in the present specification and drawings are only illustrative of specific examples for the purpose of understanding and are not intended to limit the scope of the present invention. It will be apparent to those skilled in the art that other modifications based on the technical idea of the present invention are possible in addition to the embodiments disclosed herein.

100: Reference voltage generator 110: Error amplifier
120: Voltage distribution unit 130: Feedback voltage sensing unit
131: overshoot sensing unit 132: undershoot sensing unit
Mpass: pass transistor

Claims

A reference voltage generator for forming a reference voltage;
An error amplifier for receiving the reference voltage through a negative input terminal and receiving a feedback voltage via a positive input terminal to amplify a difference between the feedback voltage and the reference voltage;
A pass transistor for generating a drive current according to an output signal of the error amplifier; And
And a voltage distributor for forming an output signal according to the drive current and generating the feedback voltage through a resistor connection,
And a feedback voltage sensing unit for sensing an overshoot and an undershoot of an output terminal by the feedback voltage and controlling a gate voltage of the pass transistor.

The apparatus of claim 1, wherein the feedback voltage sensing unit comprises:
An overshoot sensing unit for sensing an overshoot of the output stage and controlling a gate voltage of the pass transistor; And
And an undershoot sensing unit for sensing an undershoot of the output stage and controlling a gate voltage of the pass transistor.

The apparatus of claim 2, wherein the overshoot sensing unit comprises:
A first inverter for sensing the overshoot; And
And a first transistor for controlling the gate voltage of the pass transistor by the first inverter signal.

3. The apparatus of claim 2, wherein the under-
A second inverter for sensing the undershoot; And
And a second transistor for controlling the gate voltage of the pass transistor by the second inverter signal.

The method of claim 3,
Wherein the first transistor is a PMOS transistor.

5. The method of claim 4,
And the second transistor is an NMOS transistor.

The method of claim 3,
Wherein the source of the first transistor is coupled to the reference voltage generator.

5. The method of claim 4,
And a source of the second transistor is connected to a ground.

8. The method of claim 7,
The overshoot sensing unit may turn on the first transistor to receive a current through the reference voltage generator when the overshoot occurs and increase the gate voltage of the pass transistor by applying the supplied current to the gate of the pass transistor Features a low dropout voltage regulator.

9. The method of claim 8,
Wherein the undershoot sensing unit turns on the second transistor to reduce a current flowing through the pass transistor through the ground to reduce a gate voltage of the pass transistor when the undershoot occurs.

3. The method of claim 2,
Wherein the overshoot sensing unit and the undershoot sensing unit operate independently of each other when the overshoot or the undershoot is generated.