KR101433243B1 - Display device - Google Patents

Abstract

A plurality of unit pixels arranged in a matrix form, a plurality of gate lines extending in the row direction and connected to the respective pixels, a plurality of first and second data lines extending in the column direction and connected to the pixels, A display device comprising a plurality of charge control lines extended and connected to respective pixels, a plurality of gate connection lines each connecting at least two gate lines adjacent thereto, and a plurality of charge connection lines each connecting at least two charge control lines Lt; / RTI > Thus, the present invention can improve afterimage and visibility of a display device.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to a liquid crystal display device capable of improving afterimage and visibility.

2. Description of the Related Art Generally, a liquid crystal display device (LCD) has advantages of miniaturization, light weight, and large screen size compared to a conventional CRT (Cathode Ray Tube), and its development has been vigorously developed. A liquid crystal display device displays an image using a plurality of unit pixels including a thin film transistor and a pixel capacitor.

The pixel capacitor includes a pixel electrode, a common electrode, and a liquid crystal provided between the pixel electrode and the common electrode. The liquid crystal display device supplies an external charge (that is, a gradation signal) to the pixel electrode through the thin film transistor, thereby changing the electric field between the pixel electrode and the common electrode. The movement of the liquid crystal molecules is changed through the change of the electric field, and the amount of light transmitted through the liquid crystal molecules is changed by the movement of the liquid crystal molecules. Such a liquid crystal display device has a problem that visibility is low due to inherent characteristics of a liquid crystal, and after-image is generated.

The resolution of the liquid crystal display device is proportional to the number of unit pixels formed in the unit area. That is, as the number of unit pixels formed in the unit area increases, the resolution increases. However, as the resolution increases, the number of scanning lines (i.e., gate lines) increases, and the time to charge external charges (i.e., gray scale signals) to one pixel electrode is reduced. This causes a problem that the display device can not perform smooth image display.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above problems, and it is an object of the present invention to provide a liquid crystal display device capable of simultaneously charging two pixel lines by connecting a plurality of gate line pairs to a plurality of external gate lines, And a sufficient time for charge filling can be ensured.

In addition, the present invention provides a display device capable of improving the visibility by separating a unit pixel into a plurality of sub-pixels and making different amounts of charges charged in the sub-pixels.

A plurality of unit pixels arranged in a matrix form according to the present invention; a plurality of gate lines extending in the row direction and connected to the respective pixels; a plurality of first and second data lines extending in the column direction and connected to the pixels; A plurality of charge control lines extending in the row direction and connected to the respective pixels, a plurality of gate connection lines each connecting at least two gate lines, and a plurality of charge connection lines connecting each of the at least two charge control lines And a display device including the display device.

It is preferable that an insulating film is provided on the plurality of gate lines, the plurality of charge control lines and the plurality of gate connecting lines, and the plurality of charge connecting lines are located on the insulating film.

It is effective that the plurality of charge connection lines are made of the same material as the pixel electrodes in the unit pixel, and are connected to the charge control lines through the contact holes.

An insulating film is provided on the plurality of gate lines, the plurality of charge control lines, and the plurality of charge connection lines, and the plurality of gate connection lines can be located on the insulating film.

The plurality of gate lines may pass through the unit pixel region.

Wherein the first and second data lines overlap a part of the unit pixel region and a line width of a data line connected to a unit pixel of the first and second data lines in the unit pixel region is greater than a line width of the unit pixel Is smaller than the line width of the data line not connected to the data line.

Wherein the unit pixel includes a thin film transistor connected to one of the first and second data lines and the gate line, and a pixel electrode provided in a region above the thin film transistor, wherein the pixel electrode above the thin film transistor Is preferably removed.

Wherein the unit pixel includes a gate electrode, a gate insulating film and an active layer provided on the gate electrode, and a thin film transistor including source and drain electrodes provided on the active layer, wherein the active layer exists under the data line, It is possible for the lines and the active layer to have the same planar shape.

Wherein the unit pixel includes first and second sub-pixels, the gate line is electrically connected to the first and second sub-pixels, and the charge control line is connected to at least one of the first and second sub- Pixel is preferably electrically connected to the sub-pixel.

It is effective that the first and second sub-pixels are charged with different voltages.

The odd-numbered unit pixels of the plurality of unit pixels arranged in the pixel column direction are connected to one of the first and second data lines, and the even-numbered unit pixels are connected to the data lines .

The first sub-pixel includes a first pixel electrode and a first thin film transistor for applying a signal of the first or second data line to the first pixel electrode according to a gate turn-on voltage of the gate line effective.

The second sub-pixel includes a second thin film transistor for applying a signal of the first or second data line to the second pixel electrode according to a gate turn-on voltage of the gate line, And a charge control transistor for conducting the second pixel electrode and the charge control electrode in accordance with a gate turn-on voltage of the charge control line.

Wherein the charge connection line is partially overlapped with at least one gate line or at least one gate connection line, and after the gate turn-on voltage is applied to the at least one gate line or the at least one gate connection line, It is preferable that a gate turn-on voltage is applied to the line.

It is effective that the plurality of charge control lines and the plurality of gate lines are alternately arranged and the charge connection line is connected to a gate line disposed after the at least two charge control lines connected.

And a plurality of sustain lines extending in the pixel column direction in an area between the plurality of first and second data lines.

Wherein the unit pixel includes a first holding line extending through the first pixel electrode and extending in the pixel row direction, first and second holding lines extending through the first pixel electrode, A second sustaining line extending in the row direction, and a third sustaining line extending in the pixel row direction through the charge control electrode.

The first and second pixel electrodes may include a plurality of domains having curvature.

The unit pixel includes a plurality of pixel electrodes connected to the gate line, and a charge control electrode connected to the charge control line, and the charge control electrode overlaps part of the sustain line.

It is effective that one end of the plurality of charge control lines extends outside the pixel matrix and the one end is connected to the charge connection line.

A plurality of gate lines extending in the row direction and connected to the pixels; a plurality of first and second data lines extending in the column direction and connected to the pixels; A plurality of gate connection lines connecting at least two adjacent gate lines and a plurality of charge control lines extending in the row direction between a sustain line overlapping the unit pixels and two pixel rows.

The plurality of gate lines may pass through the unit pixel region.

The unit pixel includes a pixel electrode, and the first and second data lines are overlapped with the pixel electrode, and the data connected to one unit pixel of the first and second data lines in the unit pixel region It is effective that the line width of the line is smaller than the line width of the data line not connected to the one unit pixel.

Wherein the unit pixel includes a thin film transistor connected to one of the first and second data lines and the gate line, and a pixel electrode provided in a region above the thin film transistor, wherein the pixel electrode above the thin film transistor Is preferably removed.

It is effective that the charge control line is made of the same material as the gate line. And the charge control line is connected to the sustain line.

The unit pixel preferably includes at least one thin film transistor connected to one of the first and second data lines and the gate line.

Wherein the thin film transistor includes a gate electrode, a gate insulating film and an active layer provided on the gate electrode, and a source and a drain electrode provided on the active layer, wherein the active layer exists under the data line, It is possible to have the same planar shape.

It is preferable that an even-performing pixel is connected to the first data line and a even-performing pixel is connected to the second data line.

The unit pixel includes a plurality of sub-pixels, a first thin film transistor connected to the plurality of sub-pixels, and a second thin film transistor connected to at least one of the plurality of sub-pixels, It is effective to include the second thin film transistor.

The plurality of sub-pixels each include a pixel electrode, and the pixel electrode may include a plurality of domains having a curvature.

In addition, a driving method of applying a gray-scale signal by applying a gate turn-on signal connected to at least two gate lines, a unit pixel including a plurality of sub-pixels according to the present invention, a gate line connected to the unit pixel, In which a gray-scale signal is applied to the plurality of sub-pixels by applying a gate turn-on voltage and a gray-scale signal of at least one of the plurality of sub-pixels is changed when a next gate turn- As shown in FIG.

When the next gate turn-on voltage is applied, it is preferable to raise the gray level signal of at least one sub-pixel among the plurality of sub-pixels.

When the next gate turn-on voltage is applied, it is preferable to lower the gray level signals of at least one sub-pixel among the plurality of sub-pixels.

As described above, according to the present invention, at least two gate lines are connected to the gate connection line to increase the resolution, so that sufficient time can be secured for the gate turn-on voltage to be applied to the gate line even if the number of gate lines is increased.

Further, according to the present invention, two charge control lines are connected by a charge connection line, and a charge connection line is connected to a gate connection line of a next stage to control the amount of charge charged between the first and second sub- Can be improved.

In addition, the present invention can prevent the gate line and the charge connection line from being short-circuited by fabricating the charge connection line in the form of a bridge.

Further, according to the present invention, a plurality of gate lines can pass through the central region of the unit pixel, and the parasitic capacitance values generated between the plurality of gate lines and the pixel electrodes can be made uniform.

In addition, the present invention can change the line width of the data lines located on both sides of each unit pixel, or make the parasitic capacitance value between the data lines and the pixel electrode uniform by preventing the thin film transistor and the pixel electrode from overlapping each other.

In addition, the present invention can reduce the parasitic capacitance value between adjacent pixel electrodes by forming charge control lines in adjacent unit pixel regions.

1 is a conceptual view of a display device according to a first embodiment of the present invention;
2 is a circuit diagram of a display device according to the first embodiment;
3 is a schematic plan view of a display device according to the first embodiment;
4 is a cross-sectional view taken along the line AA in Fig.
5 is a cross-sectional view taken along the line BB in Fig.
6 to 8 are views for explaining a manufacturing process of the thin film transistor substrate according to the first embodiment.
9 is a cross-sectional view taken along the line AA in Fig.
10 is a cross-sectional view taken along line BB in Fig.
11 is a sectional view taken along the line AA in Fig.
12 is a sectional view taken along line BB in Fig.
13 is a cross-sectional view taken along the line AA in Fig.
Fig. 14 is a cross-sectional view taken along the line BB in Fig. 8; Fig.
15 is a plan view of a display device according to the second embodiment of the present invention.
FIG. 16 is a cross-sectional view taken along line CC in FIG. 15; FIG.
17 is a plan view of a display device according to a third embodiment of the present invention.
18 is a cross-sectional view taken along line CC of Fig.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. It will be apparent to those skilled in the art that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, It is provided to let you know.

In the drawings, the thickness is enlarged to clearly illustrate the various layers and regions, and the same reference numerals denote the same elements in the drawings. Further, when a portion such as a layer, a film, an area, a plate, or the like is expressed as being on or over another portion, it is not only the case where each portion is directly on or above the other portion, And the like.

FIG. 1 is a conceptual diagram of a display device according to a first embodiment of the present invention, and FIG. 2 is a circuit diagram of a display device according to the first embodiment.

1 and 2, a display device according to the present embodiment includes a pixel matrix, a plurality of gate connection lines 110-1, 110-2 and 110-3, a plurality of gate lines 100-1a and 100-3 A plurality of first and second data lines 200-1a, 200-2a, 200-3a, 200-4a, 200-5a, and 100-3a, 200-6a, 200-1b, 200-2b, 200-3b, 200-4b, 200-5b, 200-6b, a plurality of charge control lines 300-1a, 300-2a, 300-1b, 300-2b And a plurality of charge connection lines 310-1 and 310-2.

The pixel matrix includes a plurality of unit pixels 500 arranged in a matrix form. The pixel matrix includes a plurality of pixel columns and a plurality of pixel rows. In this embodiment, unit pixels 500 emitting red, green, and blue light in the pixel row direction are sequentially arranged. However, the present invention is not limited thereto, and unit pixels 500 emitting red, green, and blue light in the pixel column direction may be sequentially arranged. Each unit pixel 500 includes a first sub-pixel 501 and a second sub-pixel 502. However, the present invention is not limited to this, and a larger number of sub-pixels may be provided in the unit pixel 500.

The first sub-pixel 501 includes a first thin film transistor 601, a first liquid crystal capacitor Clc1, and a first storage capacitor Cst1. The gate terminals of the first thin film transistor 601 are connected to the gate lines 100-Ga; 100-1a, 100-2a, 100-3a, and 100-Gb; 100-1b, 100-2b, and 100-3b, The source terminal is connected to the first data line 200-Da 200-1a, 200-2a, 200-3a, 200-4a, 200-5a, 200-6a or the second data line 200- 200-2b, 200-3b, 200-4b, 200-5b, and 200-6b, and the drain terminal is connected to the first liquid crystal capacitor Clc1 and the first holding capacitor Cst1. The second sub-pixel 502 includes a second thin film transistor 602, a charge control transistor 701, a second liquid crystal capacitor Clc2, a second sustain capacitor Cst2, and a charge-down capacitor Cdown. The gate terminal of the second thin film transistor 602 is connected to the gate lines 100-1a, 100-2a, 100-3a, 100-1b, 100-2b, and 100-3b, and the source terminal is connected to the first or second Data lines 200-1a, 200-2a, 200-3a, 200-4a, 200-5a, 200-6a, 200-1b, 200-2b, 200-3b, 200-4b, 200-5b, 200-6b And the drain terminal thereof is connected to the second liquid crystal capacitor Clc2 and the second holding capacitor Cst2. The gate terminal of the charge control transistor 701 is connected to the charge control lines 300-Ca 300-1a, 300-2a and 300-Cb 300-1b and 300-2b and the source terminal thereof is connected to the second liquid crystal capacitor Ccl2, and the drain terminal thereof is connected to the charge-down capacitor Cdown. Although not shown, the unit pixel 500 may further include a charge-up capacitor Cup. At this time, the drain terminal of the charge control transistor 701 may be connected to one electrode of the charge-up capacitor Cup. At this time, it is preferable that the other electrode of the charge-up capacitor (Cup) is connected to the drain terminal of the first thin film transistor (601).

The plurality of gate lines 100-1a, 100-2a, 100-3a, 100-1b, 100-2b, and 100-3b extend in the row direction of the pixel mattress. Each of the plurality of gate lines 100-1a, 100-2a, 100-3a, 100-1b, 100-2b, and 100-3b is connected to a plurality of pixel rows of the pixel matrix. That is, one gate line 100-1a, 100-2a, 100-3a, 100-1b, 100-2b, and 100-3b is connected to one pixel row. Each of the plurality of gate lines 100-1a, 100-2a, 100-3a, 100-1b, 100-2b, and 100-3b penetrates the unit pixel region as shown in FIG. That is, the gate lines 100-1a, 100-2a, 100-3a, 100-1b, 100-2b, and 100-3b overlap a unit pixel region and a part thereof. Of course, the present invention is not limited thereto, and the gate lines 100-1a, 100-2a, 100-3a, 100-1b, 100-2b, and 100-3b may extend outside the unit pixel region.

A plurality of first and second data lines 200-1a, 200-2a, 200-3a, 200-4a, 200-5a, 200-6a, 200-1b, 200-2b, 200-3b, 200-4b, 200-5b, and 200-6b extend in the column direction of the pixel matrix. A plurality of first and second data lines 200-1a, 200-2a, 200-3a, 200-4a, 200-5a, 200-6a, 200-1b, 200-2b, 200-3b, 200-4b, 200-5b, and 200-6b are connected to pixel columns of the pixel matrix, respectively. Two data lines are connected to one pixel column. That is, one of the first data lines 200-1a, 200-2a, 200-3a, 200-4a, 200-5a, and 200-6a is connected to one pixel column, and one of the second data lines 200- 1b, 200-2b, 200-3b, 200-4b, 200-5b, and 200-6b are connected to the one pixel column. As shown in FIG. 1, one of the first data lines 200-1a, 200-2a, 200-3a, 200-4a, 200-5a, and 200-6a is located on the left side of one pixel column, 2 data lines 200-1b, 200-2b, 200-3b, 200-4b, 200-5b, and 200-6b are located on the right side of one pixel column. At this time, the odd-numbered unit pixels among the pixel columns are connected to the first data lines 200-1a, 200-2a, 200-3a, 200-4a, 200-5a, and 200-6a or the second data lines 200- 1b, 200-2b, 200-3b, 200-4b, 200-5b, and 200-6b. Unit pixels located at even-numbered positions among the pixel columns are connected to one remaining data line to which odd-numbered unit pixels are not connected.

The plurality of gate connection lines 110-1, 110-2, and 110-3 includes at least two adjacent gate lines 100-1a, 100-2a, 100-3a, 100-1b, 100-2b, and 100-3b ). In this embodiment, the first and second gate lines 100-1a and 100-1b, 100-2a and 100-2b are connected to one gate connection line 110-1 and 110-2, Respectively. Of course, a larger number of gate lines 100-1a, 100-2a, 100-3a, 100-1b, 100-2b, and 100-3b are connected to one gate connection line 110-1, 110-2, . Thus, in this embodiment, the two gate lines 100-1a, 100-2a, 100-3a, 100-1b, 100-2b, and 100-3b are connected to the gate connection lines 110-1, 110-2, 3) to simultaneously provide the gate turn-on voltage to the first and second gate lines 100-1a and 100-1b, 100-2a and 100-2b.

* If this increases the number of gate lines to increase the resolution, the time during which the gate turn-on voltage is applied to one gate line can be increased. For example, consider a case where the resolution is increased from 1920 * 1080 to 4096 * 2160 as follows. There are 1080 gate lines at a resolution of 1920 * 1080 and 2160 gate lines at a resolution of 4096 * 2160. And the time for display devices having two resolutions to represent one video frame is the same. That is, if it is assumed that the time for expressing one image frame is 1 second, it is as follows. In the case of 1080 gate lines, gate turn-on voltage should be applied to all 1080 gate lines for 1 second. Therefore, the time for applying the gate turn-on voltage to one gate line is 1/1080 second. However, in the case of 2160 gate lines, the gate turn-on voltage must be applied to 2160 gate lines for 1 second. Therefore, the time when the gate turn-on voltage is applied to one gate line becomes 1/2160 seconds. When the resolution is doubled, the time for applying the gate turn-on voltage to one gate line is halved.

However, when two adjacent gate lines 100-1a and 100-1b, 100-2a and 100-2b are connected by one gate connection line 110-1 and 110-2 as in the present embodiment , And the number of the gate connection lines 110-1 and 110-2 is 1080. Therefore, a gate turn-on voltage may be applied to 1080 gate connection lines to represent one image frame. That is, a gate turn-on voltage is simultaneously applied to the two gate lines 100-1a and 100-1b, 100-2a and 100-2b to form one gate line 100-1a, 100-2a, 100-3a, 100- 1b, 100-2b, and 100-3b can be prevented from being reduced.

At this time, since the gate turn-on voltage is simultaneously supplied to the two adjacent gate lines 100-1a and 100-1b, 100-2a and 100-2b, the two gate lines 100-1a and 100-1b, 100-2a, Two pixel rows connected to each other operate simultaneously. That is, the first and second thin film transistors 601 and 602 in the two unit pixels located in the upper and lower positions are simultaneously turned on. In this case, when the first and second thin film transistors 601 and 602 located at the upper and lower sides are connected to the same data line, the two unit pixels located at the upper and lower sides represent the same image, so that the resolution can not be increased. Accordingly, in the present embodiment, the first and second thin film transistors 601 and 602 located at the upper portion are connected to the first data lines 200-1a, 200-2a, 200-3a, 200-4a, 200-5a, and 200-6a And the first and second thin film transistors 601 and 602 located at the bottom are connected to the second data lines 200-1b, 200-2b, 200-3b, 200-4b, 200-5b, and 200-6b, . The first and second data lines 200-1a, 200-2a, 200-3a, 200-4a, 200-5a, 200-6a, 200-1b, 200-2b, 200-3b, 200-4b, 5b, and 200-6b may be provided with different gradation signals (i.e., charge) so that the two unit pixels 500 positioned at the upper and lower sides may represent independent images.

In this embodiment, the charge control lines 300-1a, 300-2a, 300-1b, and 300-b for controlling the charge amount between the first and second sub-pixels 501 and 502 in the unit pixel 500, 2b. The plurality of charge control lines 300-1a, 300-2a, 300-1b, and 300-2b extend in the row direction of the pixel matrix and are connected to a plurality of pixel rows, respectively. The plurality of charge control lines 300-1a, 300-2a, 300-1b, and 300-2b may include a plurality of gate lines 100-1a, 100-2a, 100-3a, 100-1b, 100-2b, and 100- 3b are electrically insulated.

That is, the plurality of charge control lines 300-1a, 300-2a, 300-1b, and 300-2b are connected to the gate lines 100-1a, 100-2a, 100-3a, and 100-1b And the plurality of charge control lines 300-1a, 300-2a, 300-1b, and 300-2b are electrically insulated from the gate lines 100-1a, 100-2b, and 100-3b , 100-2a, 100-3a, 100-1b, 100-2b, and 100-3b. This makes it possible to improve the visibility of the display device. A gate turn-on voltage is applied to the gate lines 100-1a, 100-2a, 100-3a, 100-1b, 100-2b and 100-3b so that the first and second sub-pixels 501 and 502 of the unit pixel Charge the self. Then, when the gate turn-on voltage is provided to the next gate lines 100-1a, 100-2a, 100-3a, 100-1b, 100-2b, and 100-3b, a plurality of charge control lines 300-1a, 300 -2a, 300-1b, and 300-2b are also provided with a gate turn-on voltage to change the amount of charge of at least one of the first and second sub-pixels 501 and 502. In the present embodiment, the charge amount of the second sub-pixel 502 is reduced to improve the visibility.

In the above description, the charge control lines 300-1a, 300-2a, 300-1b, and 300-2b are connected to the gate lines 100-1a, 100-2a, 100-3a, 100-1b, 100-2b, The gate turn-on voltage applied to the gate lines 100-1a, 100-2a, 100-3a, 100-1b, 100-2b, and 100-3b is simultaneously applied. That is, the two gate lines 100-1a, 100-2a, 100-3a, 100-1b, and 100-3b are connected to the gate lines 100-1a, 100-2a, 100-3a, and 100-1b through a plurality of stages connected to the plurality of gate connection lines 110-1, 110-2, 100-2b, 100-3b, and the gate turn-on voltage is also provided to the charge control lines 300-1a, 300-2a, 300-1b, and 300-2b. However, the charge control lines 300-1a, 300-2a, 300-1b, and 300-2b are not limited to the gate lines 100-1a, 100-2a, 100-3a, 100-1b, -2b, and 100-3b, and the gate turn-on voltage is supplied through the separate gate turn-on voltage supply means to change the charge amount of the sub-pixel. That is, it is possible to provide a gate turn-on voltage to the charge control lines 300-1a, 300-2a, 300-1b, and 300-2b using a separate stage unit.

In this embodiment, two gate lines 100-1a and 100-1b, 100-2a and 100-2b are connected through one gate connection line 110-1 and 110-2. Therefore, the plurality of charge control lines 300-1a, 300-2a, 300-1b, and 300-2b are also connected to the two charge control lines 300-1a and 300-1b, 300-2a, and 300-2b And are connected by one charge connection line 310-1 and 310-2. The charge connection lines 310-1 and 310-2 are connected to the rear gate connection lines 110-2 and 110-3. In this case, an area where the gate connection line 110-1 and the charge connection line 310-1 overlap is generated as in the K area of FIG. Therefore, one of the gate connection lines 110-1, 110-2, and 110-3 or the charge connection lines 310-1 and 310-2 may be fabricated in the form of a bridge wiring. Since the gate connection lines 110-1, 110-2 and 110-3 and the charge control lines 310-1 and 310-2 are both connected to the gate lines, It is because. Thus, in this embodiment, the charge connection lines 310-1 and 310-2 are not fabricated together with the gate lines, but are formed in the form of a bridge wiring.

Hereinafter, the display device according to the present embodiment will be described in detail with reference to the drawings.

Fig. 3 is a plan view of a plan view of the display device according to the first embodiment. Fig. 4 is a sectional view taken along line A-A of Fig. 3, and Fig. 5 is a sectional view taken along line B-B of Fig.

3 to 5, the display device according to the present embodiment includes a thin film transistor substrate 1000 as a lower substrate, a common electrode substrate 2000 as an upper substrate facing the thin film transistor substrate 1000, And a liquid crystal 30.

The surfaces of the upper and lower substrates may be provided with an alignment film (not shown) for aligning the liquid crystal molecules. Here, the molecular orientation of the liquid crystal 30 may be a vertical alignment mode in which it is perpendicular to each substrate. It may not be vertical orientation, and is not particularly limited.

The thin film transistor substrate 1000 has a light-transmitting insulating substrate 10. It is preferable to use glass or translucent plastic as the translucent insulating substrate 10.

The thin film transistor substrate 1000 has a plurality of gate lines 100-Ga and 100-Gb extending in the row direction on the insulating substrate 10. [ A part of the plurality of gate lines 100-Ga and 100-Gb protrudes upward and / or downward to form first and second gate terminals of the first and second thin film transistors 601 and 602. The gate lines 100-Ga and 100-Gb may be formed as a single layer, or may be formed as multiple layers of two or more layers. In the case of forming at least two layers, it is preferable that one layer is formed of a material having a low resistance and the other layer is made of a material having good contact properties with other materials. For example, a double layer of Cr / Al (or Al alloy) or a double layer of Al (or Al alloy) / Mo may be used. Alternatively, a gate line 100-Ga, 100-Gb may be formed as a variety of metals or conductors .

As shown in FIG. 3, two adjacent gate lines 100-Ga and 100-Gb among the plurality of gate lines 100-Ga and 100-Gb are connected to each other by a plurality of connection gate lines 110- . The plurality of connection gate lines 110-G are made of the same material on the same plane as the gate lines 100-Ga and 100-Gb. A charge pad 120 to be connected to the charge connection line 310-C is provided in a connection region between the plurality of connection gate lines 110-G and the first gate line 100-Ga. Gate contact pads (not shown) for connection to external circuits are formed at the ends of the plurality of connection gate lines 110-G.

The thin film transistor substrate 1000 includes a plurality of charge control lines 300-Ca and 300-Cb extending in the same direction as the plurality of gate lines 100-Ga and 100-Gb. A part of the charge control lines 300-Ca and 300-Cb protrudes upward and / or downward to form a gate terminal 711 of the charge control transistor 701. The charge control lines 300-Ca and 300-Cb are formed of the same material on the same plane as the gate lines 100-Ga and 100-Gb. 3, two adjacent charge control lines 300-Ca and 300-Cb among the plurality of charge control lines 300-Ca and 300-Cb are connected to a plurality of charge connection lines 310- Lt; / RTI > An insulating protective film is disposed between the charge connection line 310-C and the two charge control lines 300-Ca and 300-Cb. Therefore, the charge connection line 310-C and the two charge control lines 300-Ca and 300-Cb are connected through the first and second charge contact holes 321 and 322. The charge connection line 310-C is connected to the charge pad 120.

Here, the thin film transistor substrate 1000 is divided into an image display region where a plurality of unit pixels are provided and a peripheral region. At this time, it is preferable that the charge connection line 310-C is located in the peripheral region. Thus, a sufficient process margin for forming the charge connection line 310-C can be ensured, and a phenomenon of shorting to the pixel electrode in the image display region can be prevented. Of course, the gate lines 100-Ga and 100-Gb described above are provided in the image display region. Of course, a part of the gate lines 100-Ga and 100-Gb may extend to the peripheral region. The gate connection line 110-G is provided in the peripheral region. Of course, a part of the gate connection line 110-G may extend to the image display area.

The thin film transistor substrate 1000 includes a plurality of first and second data lines 200-Da and 200-Db intersecting a plurality of gate lines 100-Ga and 100-Gb. The first and second data lines 200-Da and 200-Db are positioned adjacent to the left and right sides of one pixel row. A part of the first and second data lines 200-Da and 200-Db protrude to form first and second source terminals 631 and 641 of the first and second thin film transistors 601 and 602. The first and second data lines 200-Da and 200-Db may be formed as a single layer, or may be formed as multiple layers of two or more layers having different material properties. In the case of forming at least two layers, it is preferable that one layer is formed of a material having a low resistance so as to reduce a delay of a data signal and a voltage drop, and the other layer is made of a material having good contact properties with other materials. Although the first and second data lines 200-Da and 200-Db are shown in the drawing, the first and second data lines 200-Da and 200-Db are not limited thereto.

The thin film transistor substrate 1000 includes a plurality of sustain lines 400 extending to a region between the first and second data lines 200-Da and 200-Db. That is, the plurality of sustain lines 400 extend in parallel with the first and second data lines 200-Da and 200-Db. The sustain line 400 is preferably formed of the same material on the same plane as the first and second data lines 200-Da and 200-Db. The holding line 400 is used as one electrode terminal of the first and second holding capacitors Cst1 and Cst2. Then, as shown in FIG. 3, a part of the holding line 400 is protruded to form the protrusion 410. At this time, the region of the protrusion 410 is used as one electrode terminal of the charge down capacitor Cdown. The sustain line 400 may penetrate the central region of the unit pixel in the column direction. The first and second thin film transistors 601 and 602 in the plurality of unit pixels arranged in the column direction are alternately arranged on the left and right sides of the sustaining line 400 with respect to the sustaining line 400. [ 3, the first and second thin film transistors 601 and 602 of the upper unit pixel are located on the right side of the sustain line 400 and the first and second thin film transistors 601 and 602 of the lower unit pixel 1 and the second thin film transistors 601 and 602 are located on the left side of the sustaining line 400. The first and second data lines 200 -Da and 200 -Db are located on the left and right sides of the unit pixel column, and one unit pixel of the two unit pixels is connected to the first data line 200-Da on the left side. And the remaining unit pixels are connected to the second data line 200-Db on the right side.

The thin film transistor substrate 1000 includes first and second pixel electrodes 510 and 520 which are used as one electrode terminals of the first and second pixel capacitors Clc1 and Clc2 and the first and second holding capacitors Cst1 and Cst2, ). The first and second pixel electrodes 510 and 520 are made of a transparent conductive material such as ITO or IZO. The first and second pixel electrodes 510 and 520 are formed in the unit pixel region. The first and second pixel electrodes 510 and 520 are spaced apart by a cutout. As shown in Fig. 3, the shape of the incision has an inverted V-shape. The first pixel electrode 510 is located on the upper side of the unit pixel region and the second pixel electrode 520 is located on the lower side of the unit pixel region. The first and second pixel electrodes 510 and 520 include a plurality of domains. As the domain dividing means, a cutting pattern or a protrusion is used. The first and second pixel electrodes 510 and 520 may be mirror image-symmetric with respect to the sustain line 400. The first and second thin film transistors 601 and 602, the gate lines 100-Ga and 100-Gb, the first and second pixel electrodes 510 and 520, 2 source lines 200-Da, 200-Db and sustain line 400). As the insulating film, an organic film and / or an inorganic film can be used. In this embodiment, an organic protective film 530 is used as an insulating film. Of course, a silicon nitride film may be further formed under the organic passivation layer 530.

3, the gate lines 100-Ga and 100-Gb penetrate the region between the first and second pixel electrodes 510 and 520 (that is, the cutout region) in the row direction do. The overlapping area between the gate lines 100-Ga and 100-Gb and the first and second pixel electrodes 510 and 520 is set to be within a unit pixel area by arranging the gate lines 100-Ga and 100- Make it uniform. This makes it possible to solve the problem caused by the parasitic capacitance generated in the overlap region.

The thin film transistor substrate 1000 includes first and second thin films connected to one data line of the first and second data lines 200-Da and 200-Db and one gate line 100-Ga and 100-Gb, Transistors 601 and 602 are provided.

The first and second thin film transistors 601 and 602 are connected to the first and second gate terminals 611 and 621 and the first and second source terminals 631 and 641 and the first and second drain terminals 651 and 651, 661). The first and second thin film transistors 601 and 602 are electrically connected to the gate insulating films 612 and 622 provided on the first and second gate terminals 611 and 621 and the active layer (not shown) provided on the gate insulating films 612 and 622 613, 623, and ohmic contact layers 614, 624. As shown in Figs. 3 and 4, the first and second gate terminals 611 and 621 have a single body. As the gate insulating films 612 and 622, a silicon nitride film or a silicon oxide film can be used. The active layers 613 and 623 are located above the first and second gate terminals 611 and 621, respectively. The first and second source terminals 631 and 641 are formed into a linear shape bent on the active layers 613 and 623. 3, the first and second source terminals 631 and 641 are located below the first to third extension straight lines and the gate lines 100-Ga and 100-Gb, A first connection line connecting straight lines and a second connection line located above the gate lines 100-Ga and 100-Gb and connecting the second and third extended straight lines. The first connection line is connected to the first or second data line 200-Da or 200-Db. The first and second drain terminals 651 and 661 extend to regions above the active layers 613 and 623 in the lower region of the first and second pixel electrodes 510 and 520, respectively. The first drain terminal 651 extends into the space between the first and second extended straight lines and the second drain terminal 661 extends into the space between the second and third extended straight lines. The first drain terminal 651 is connected to the first pixel electrode 510 through the first pixel contact hole 652. The second drain terminal 661 is connected to the second pixel electrode 520 through the second pixel contact hole 662.

Here, although not shown, the active layers 613 and 623 are not located only above the first and second gate terminals 611 and 621, but extend in the lower region of the extended first and second drain terminals 651 and 661 And may be located in a lower region of the first and second data lines 200-Da and 200-Db. That is, the active layers 613 and 623 exist under the first and second data lines 200-Da and 200-Db and the first and second data lines 200 -Da and 200 -Db and the active layer 613, and 623 have the same planar shape.

The thin film transistor substrate 1000 includes a charge control transistor 701 connected to the charge connection line 310. [ The charge control transistor 701 includes a gate terminal 711 connected to the charge connection line 310 and the charge control lines 300-Ca and 300-Cb, a gate insulating film 712 formed on the gate terminal 711, An active layer 713 formed on the gate insulating film 712 in the region above the gate terminal 712 and a source terminal 721 and a drain terminal 731 formed on the active layer 713. The source terminal 721 is connected to the second pixel electrode 520 through the source contact hole 722. The drain terminal 731 is connected to the charge control electrode 800 through the drain contact hole 732. The charge control electrode 800 is used as one electrode terminal of the charge down capacitor Cdown. That is, a part of the charge control electrode 800 overlaps with the protruding portion 410 of the holding line 400. When the charge control transistor 701 is turned on, part of the charge charged in the second pixel electrode 520 by the charge control transistor 701 moves to the charge control electrode 800. [ Here, the charge control electrode 800 is formed simultaneously with the first and second pixel electrodes 510 and 520. The charge control electrode 800 is located in the cutout region below the second pixel electrode 520 and the charge control transistor is positioned in the region adjacent to the cutout region of the second pixel electrode 520 to make the length of the wiring for contact connection Can be minimized. This can reduce the aperture ratio reduction.

Next, the common electrode substrate 2000 includes a light-transmitting insulating substrate 20, a light-shielding pattern 910 for preventing optical interference between unit pixel areas adjacent to the light-shielding, a color filter 920 of red, A light shielding pattern 910, an overcoat film 930 provided on the color filter 920, and a common electrode 940 provided on the overcoat film 930. A black matrix is used as the light shielding pattern 910. An organic material is used for the overcoat film 930. A transparent conductive material such as ITO or IZO is used as the common electrode 940. The common electrode 940 is provided with a plurality of dissection patterns 941 for domain control. However, the present invention is not limited to this, and other means such as projections may be used for domain control.

Here, the common electrode 940 is used as one electrode terminal of the first and second pixel capacitors Clc1 and Clc2. That is, the first pixel capacitor Clc1 uses the first pixel electrode 510 and the common electrode 940 as the upper and lower electrodes, respectively, and uses the liquid crystal 30 as the dielectric. In the second pixel capacitor Clc2, the second pixel electrode 520 and the common electrode 940 are used as upper and lower electrodes, respectively, and a liquid crystal is used as a dielectric.

The basic panel of the display device according to an embodiment of the present invention is provided by combining the thin film transistor substrate 1000 and the common electrode substrate 2000 with the liquid crystal 30 interposed therebetween. The display device can arrange elements such as a polarizing plate, a backlight, an optical plate / sheet, etc., which are not shown on both sides of the basic panel.

In this embodiment, two gate lines 100-Ga and 100-Gb are connected to one gate connection line 110-G and a gate turn-on voltage is applied to the gate connection line 100-G, (That is, the gate turn-on time of the thin film transistor) that may occur when the gate voltage is increased. A unit pixel having first and second sub-pixels in the unit pixel region and a charge amount control portion for controlling the charge amount of the second sub-pixel by driving in accordance with the next gate turn-on voltage signal can be manufactured. At this time, the first sub-pixel is a main pixel expressing a high gradation, and the second sub-pixel is a sub-pixel expressing a low gradation. This makes it possible to improve the visibility of the display device.

Hereinafter, a method of manufacturing a display device having the above structure will be described with reference to a thin film transistor substrate.

6 to 8 are views for explaining a manufacturing process of the thin film transistor substrate according to the first embodiment. Fig. 9 is a sectional view taken along the line A-A of Fig. 6, and Fig. 10 is a sectional view taken along line B-B of Fig. Fig. 11 is a sectional view cut along the line A-A in Fig. 7, and Fig. 12 is a sectional view taken along line B-B in Fig. Fig. 13 is a sectional view cut along the line A-A in Fig. 8, and Fig. 14 is a sectional view taken along line B-B in Fig.

6, 9, and 10, a first conductive film is formed on the substrate 10. [ A plurality of gate lines 100-Ga and 100-Gb, a plurality of gate connection lines 110-G and charge control lines 300-Ca and 300-Cb are formed by patterning the first conductive film. At this time, the gate terminals 611 and 621 for the first and second thin film transistors and the gate terminal 711 for the charge control transistor are also formed.

Wherein at least one of Cr, MoW, Cr / Al, Cu, Al (Nd), Mo / Al, Mo / Al (Nd), Cr / Al (Nd), and Mo / Al / Mo is used as the first conductive film Is preferably used. However, the present invention is not limited thereto. As described above, the first conductive film may be formed of a metal or an alloy containing at least one of Al, Nd, Ag, Cr, Ti, Ta, . In other words, it may be formed of a double layer or a triple layer including a metal layer of Cr, Ti, Ta, Mo or the like having excellent physical and chemical properties and an Al or Ag series metal layer having a small specific resistance. After the above-described first conductive film is formed on the entire substrate, a photosensitive film is applied, and then a lithography process using a mask is performed to form a photoresist mask pattern. An etching process is performed using the photoresist mask pattern as an etching mask. As a result, the first and second gate lines 100-Ga and 100-Gb are formed as shown in FIGS. 6, 9 and 10, and the first and second gate lines 100Ga and 100- Thereby forming connection gate lines 110-G to be connected. A plurality of gate terminals 611 and 621 are formed in the first and second gate lines 100-Ga and 100-Gb. The first and second charge control lines 300-Ca and 300-Cb are formed and gate terminals 711 are formed in the first and second charge control lines 300-Ca and 300-Cb.

7, 11 and 12, gate insulating films 612 and 622, a thin film for an active layer and a thin film for an ohmic contact layer are sequentially formed on a substrate 10 provided with gate lines 100-Ga and 100-Gb A thin film for the active layer and a thin film for the ohmic contact layer are patterned to form the active layers 613, 623, and 713 and the ohmic contact layers 614 and 624.

As the gate insulating films 612 and 622, it is preferable to use an inorganic insulating material containing silicon oxide or silicon nitride. An amorphous silicon layer is used as the thin film for the active layer and an amorphous silicon layer doped with a high concentration of the silicide or the N type impurity is used as the thin film for the ohmic contact layer.

The first and second data lines 200 -Da and 200 -Db, the source terminals 631, 641, and 721, the drain terminals 651 and 661, and the drain electrodes 651 and 662 are formed by patterning the second conductive film on the entire structure. 731 and a sustaining line 400 are formed. As the second conductive film, it is preferable to use a single layer or multilayer of at least one metal selected from the group consisting of Mo, Al, Cr and Ti. Of course, the same material as the first conductive film may be used for the second conductive film. The first and second thin film transistors 601 and 602 having the gate terminals 611 and 612, the source terminals 631 and 641 and the drain terminals 651 and 661 are fabricated. A charge control transistor 701 including a gate terminal 711, a source terminal 721, and a drain terminal 731 is fabricated.

8, 13 and 14, a protective film 530 is formed on a substrate 10 provided with first and second thin film transistors 601 and 602 and a charge control transistor 701, and a photoresist mask pattern The first and second pixel contact holes 652 and 653 exposing a part of the drain terminals 651 and 661 of the first and second thin film transistors 601 and 602 are formed by removing a part of the protective film 530 through the etching process, 662 are formed. A source contact hole 722 exposing a part of the source terminal 721 of the charge control transistor 701 and a drain contact hole 732 exposing a part of the drain terminal 731 are formed. The charge contact holes 321 and 322 exposing the one end regions of the charge control lines 300-Ca and 300-Cb are formed. A contact hole exposing a part of the charge pad 120 is formed.

A third conductive film is formed on the protective film 530 provided with the contact holes described above. The first and second pixel electrodes 510 and 520 are formed by patterning the third conductive film using a photoresist mask pattern (not shown) to form the charge control electrode 800. Then, a charge connection line 310-C is formed.

Here, it is preferable to use a transparent conductive film containing indium tin oxide (ITO) or indium zinc oxide (IZO) as the third conductive film. The first pixel electrode 510 is connected to the drain terminal 651 of the first thin film transistor 601 through the first pixel contact hole 652. The second pixel electrode 520 is connected to the drain terminal 661 of the second thin film transistor 602 through the second pixel contact hole 662 and is connected to the drain of the charge control transistor 700 through the source contact hole 722. [ And is connected to the source terminal 721. The charge control electrode 800 is connected to the drain terminal 731 of the charge control transistor 700 through the drain contact hole 732.

A first charge contact hole 321 of a charge control line 300-Ca provided between two gate lines 100-Ga and 100-Gb connected by a gate connection line 110-G, The second charge contact hole 322 of the charge control line 300-Cb on the lower side of the charge control line 300-Ca is connected by the charge connection line 310-C. The charge connection line 310 is connected to the charge connection pad 110 of the gate connection line 110-G and / or the gate lines 100-Ga and 100-Gb connected to the next pixel row.

The charge connection line 310 formed by the third conductive film is connected to the charge control lines 300-Ca and 300-Cb under the charge connection line 310 through the first and second charge contact holes 321 and 322, ) Is referred to as a bridge wiring form.

A unit pixel having first and second sub-pixels and capable of controlling a charging amount in the first and second sub-pixels can be manufactured through the above-described process, and unit pixels located on the upper and lower sides can be simultaneously driven.

After the first and second pixel electrodes 510 and 520 are formed as described above, a first alignment layer (not shown) is formed on the entire structure. Thus, a lower substrate, that is, a thin film transistor substrate is manufactured.

Although not shown, the common electrode substrate is manufactured by sequentially forming a black matrix, a color filter, an overcoat film, a projection pattern, a transparent common electrode, and a second alignment film (not shown) sequentially on a transparent insulating substrate. Subsequently, these substrates are bonded to each other via spacers (not shown) between the thin film transistor substrate and the common electrode substrate manufactured as described above. Subsequently, a liquid crystal material is injected into a predetermined space formed by spacers using a vacuum injection method to form a liquid crystal layer, thereby manufacturing a liquid crystal display device according to this embodiment.

Though the thin film transistor substrate of the above-described embodiment is formed by the five-mask process, it is not limited to this, and may be formed by five or more mask processes or five or less mask processes.

The present invention is not limited to the above description, and the sustain lines may extend parallel to the gate lines, and the line widths of the first and second data lines located on both sides of the unit pixel may be different from each other. Hereinafter, a display device according to a second embodiment of the present invention will be described with reference to the drawings. Description of the following description of the first embodiment will be omitted. The technique of the second embodiment described later can be applied to the first embodiment described above.

15 is a plan view of a display device according to a second embodiment of the present invention. 16 is a cross-sectional view taken along the line C-C in Fig.

15 and 16, the display device according to the present embodiment includes first to third sustaining lines 401, 402, and 403 extending in parallel with the gate lines 100-Ga and 100-Gb . The first sustaining line 401 passes through the first sub pixel region, and the second and third sustaining lines 402 and 403 pass through the second sub pixel region. The first sustain line 401 has a first protrusion overlapping the first pixel electrode 510. The second sustain line 402 has a second protrusion overlapping the second pixel electrode 520. The third sustain line 403 has a third protrusion partly overlapping the charge control electrode 800. [ A drain terminal 651 of the first thin film transistor 601 connected to the first pixel electrode 510 through the first pixel contact hole is located on the first protrusion. Therefore, the capacitance of the first holding capacitor Cst1 is changed in accordance with the overlapping area between the first projecting portion and the drain terminal 651 of the first thin film transistor 601. A drain terminal 661 of the second thin film transistor 602 connected to the second pixel electrode 520 through the second pixel contact hole is located on the second protrusion. The capacitance of the second holding capacitor Cst is changed according to the overlapping area between the second projection and the drain terminal 661 of the second thin film transistor 602. [ A drain terminal 731 of the charge control transistor 700 connected to the charge control electrode 800 through the contact hole is located on the third protrusion. The charge-down capacitor Cdown is changed according to the overlapping area between the drain terminal 731 and the third projection. The first to third sustaining lines 401, 402, and 403 of this embodiment are formed together with the gate lines 100-Ga and 100-Gb. The first to third holding lines 401, 402, and 403 are all connected to one side of the substrate 10.

The first and second data lines 200-Da and 200-Db of the present embodiment are overlapped with the first and second pixel electrodes 510 and 520, respectively. At this time, any one of the data lines of the first or second data lines 200-Da and 200-Db in one unit pixel is connected to the source terminals 631 and 641 of the first and second thin film transistors 601 and 602, Lt; / RTI > The line width of the data line connected to the source terminals 631 and 634 of the first and second thin film transistors 601 and 602 in the unit pixel region is made smaller than the line width of the unconnected data line, The parasitic capacitance between the electrodes can be kept the same. That is, in this embodiment, the parasitic capacitance is kept equal by making the overlapping areas of the pixel electrodes and the lines for providing the data signals equal in the unit pixel region. Since the first data line 200-Da located at the left edge of the upper unit pixel region has no extended source terminal, the first data line 200-Da and the first and second pixel electrodes 200- The parasitic capacitance corresponding to the overlapping area between the electrodes 510 and 520 is obtained. A portion of the second data line 200-Db located at the right edge of the upper unit pixel region extends to form source terminals 631 and 634. Accordingly, not only the overlapping area of the second data line 200-Db and the first and second pixel electrodes 510 and 520 but also the overlapping area between the source terminals 631 and 634 and the first and second pixel electrodes 510 and 520 The parasitic capacitance is equal to the sum of the overlap area. The line width T2 of the second data line 200-Db is made smaller than the line width T1 of the first data line 200-Da. At this time, the line width T2 of the second data line 200-Db is set to the first data line 200-Da so as to be subtracted by the overlapping area between the source terminals 631 and 634 and the pixel electrodes 510 and 520, Is smaller than the line width (T1). Of course, the line width T1 of the first data line 200-Da may be increased.

15, since the second data line 200-Db located at the right edge of the lower unit pixel region has no extended source terminal, the second data line 200-Db and the first and second And has a parasitic capacitance corresponding to the area superimposed between the pixel electrodes 510 and 520. However, a portion of the first data line 200-Da located at the left edge of the lower unit pixel region extends to form the source terminals 631 and 634. Accordingly, not only the overlapping area of the first data line 200-Da and the first and second pixel electrodes 510 and 520, but also the overlapping area between the source terminals 631 and 634 and the first and second pixel electrodes Parasitic capacitance. Then, the line width of the first data line 200-Da is made smaller than the line width of the second data line 200-Da.

This is because the first and second thin film transistors 601 and 602 in the pixel column are alternately connected to the first and second data lines 200-Da and 200-Db arranged on the left and right sides, 200-Da, 200-Db) also narrows alternately.

In addition, the present invention is not limited to the above description, and a single pixel electrode may be provided in a unit pixel region, a pixel electrode in a region above the thin film transistor may be cut off, Lines may be formed. Hereinafter, a display device according to a third embodiment of the present invention will be described with reference to the drawings. The description overlapping with the description of the first and second embodiments described above will be omitted. The technique of the third embodiment described later can be applied to the first and second embodiments described above.

17 is a plan view of a display device according to a third embodiment of the present invention. 18 is a cross-sectional view taken along the line C-C of Fig.

Referring to FIGS. 17 and 18, the display device according to the present embodiment includes one of the first and second data lines 200-Da and 200-Db and the gate lines 100-Ga and 100-Gb A pixel electrode 550 connected to the drain terminal 681 of the thin film transistor 603; The pixel electrode 550 has a cutout groove 551 for opening the upper region of the thin film transistor 603. The cutout groove 551 is formed in the same rectangular shape as the thin film transistor 603 as shown in FIG. The cutout groove 551 may be formed by removing the pixel electrode 550 located on the source terminal 671 of the TFT 603. [ As described above, a difference in parasitic capacitance occurs depending on the difference in overlapping area between the pixel electrode and the lines for transmitting the data signal. A cutout groove 551 in which the pixel electrode 550 is cut out is formed on the upper side of the thin film transistor 603 so that the source terminal 671 of the thin film transistor 603 and the pixel electrode 550 are not overlapped do. The overlapping area between the pixel electrode 550 and the first and second data lines 200 -Da and 200 -Db can be equalized. The parasitic capacitance between the pixel electrode 550 and the first and second data lines 200 -Da and 200 -Db can be equalized.

In addition, in this embodiment, charge control lines 450 are formed in the pixel column direction, that is, in the region between vertically adjacent pixel electrodes 550. The charge control line 450 is formed so as to overlap the pixel electrodes 550 adjacent to the upper and lower sides. Coupling between the adjacent pixel electrodes 550 in the vertical pixel column direction can be prevented and parasitic capacitance formed between adjacent pixel electrodes 550 in the pixel column direction can be reduced. The charge control line 450 is formed together with the gate lines 100-Ga and 100-Gb and the sustain line 400. The charge control line 450 is connected to the sustain line 400 at one edge region of the substrate 10. [ The charge control line 450 maintains the ground potential, which is the potential of the sustain line 400. [ When a charge control line 450 having a ground potential is disposed between the two pixel electrodes 550, the charge control line 450 shields the electric field. Therefore, the parasitic capacitance between the adjacent pixel electrodes 550 can be reduced.

Although the present invention has been described with reference to the accompanying drawings and the preferred embodiments described above, the present invention is not limited thereto but is limited by the following claims. Accordingly, those skilled in the art will appreciate that various modifications and changes may be made thereto without departing from the spirit of the following claims.

100-Ga, 100-Gb: gate line
10, 20: substrate 110-G: gate connection line
200-Da: first data line 200-Db: second data line
300-Ca, 300-Cb: charge control line 310-C: charge connection line
400, 401, 402, 403: maintain line 450: charge control line
500: unit pixel, 501, 502: sub pixel
510, 520, 550: pixel electrode 800: charge control electrode
601, 602, 603, 701: thin film transistors

Claims (13)

A first unit pixel and a second unit pixel adjacent to the first unit pixel in a first direction;
A first gate line and a second gate line extending in a second direction intersecting with the first direction and electrically connected to the first unit pixel and the second unit pixel, respectively;
A first data line and a second data line extending in the first direction and electrically connected to the first unit pixel and the second unit pixel, respectively;
A first charge control line and a second charge control line extending in the second direction and electrically connected to the first unit pixel and the second unit pixel, respectively; And
And a sustain line to which a common voltage is applied,
Wherein the first unit pixel and the second unit pixel each include a first sub-pixel and a second sub-pixel,
The first charge control line and the second charge control line are connected to the second sub-pixel of the first unit pixel and the second sub-pixel of the second unit pixel, respectively,
Wherein the first gate line and the second gate line are simultaneously applied with a first voltage,
Wherein the first charge control line is applied with a second voltage after the first voltage is applied to the first gate line and the second gate line. The method according to claim 1,
Wherein the first charge control line and the second charge control line are simultaneously receiving the second voltage. The method according to claim 1,
And the voltage charged in the second sub-pixel of the first unit pixel is changed when the second voltage is applied to the first charge control line. The method of claim 3,
Wherein a voltage charged in the first sub-pixel of the first unit pixel and a voltage charged in the second sub-pixel of the first unit pixel are different from each other. The method according to claim 1,
The first sub-pixel of the first unit pixel includes:
A first pixel electrode; And
And a first thin film transistor for applying a data signal to the first pixel electrode according to the first voltage. The method according to claim 1,
And the second sub-pixel of the first unit pixel,
A second pixel electrode;
A second thin film transistor for applying a data signal to the second pixel electrode according to the first voltage; And
And a charge control transistor electrically connected to the first charge control line and the second pixel electrode according to the second voltage. The method according to claim 6,
And a charge control electrode electrically connected to the charge control transistor,
And the charge control electrode overlaps with a part of the sustain line. The method according to claim 6,
And the first charge control line is connected to the gate terminal of the charge control transistor. The method according to claim 1,
And a third gate line adjacent to the second gate line,
The third gate line receives a third voltage,
And the second voltage and the third voltage are simultaneously applied to the first charge control line and the third gate line, respectively. The method according to claim 1,
The first voltage is applied to the first gate line and the second gate line through the first voltage supply unit,
And the second voltage is applied to the first charge control line through a second voltage supply unit separated from the first voltage supply unit. The method according to claim 1,
Wherein when the first voltage is applied to the first gate line and the second gate line, the second voltage is not applied to the first charge control line. A first unit pixel and a second unit pixel adjacent to the first unit pixel in a first direction;
A first gate line and a second gate line extending in a second direction intersecting with the first direction and electrically connected to the first unit pixel and the second unit pixel, respectively;
A first data line and a second data line extending in the first direction and electrically connected to the first unit pixel and the second unit pixel, respectively;
A first charge control line and a second charge control line extending in the second direction and electrically connected to the first unit pixel and the second unit pixel, respectively; And
And a sustain line to which a common voltage is applied,
Wherein the first unit pixel and the second unit pixel each include a first sub-pixel and a second sub-pixel,
The first charge control line and the second charge control line are connected to the second sub-pixel of the first unit pixel and the second sub-pixel of the second unit pixel, respectively,
Wherein the first gate line and the second gate line are simultaneously applied with a first voltage,
Wherein the first charge control line is applied with a second voltage after the first voltage is applied to the first gate line and the second gate line,
Wherein the first charge control line and the second charge control line are simultaneously receiving the second voltage. A first unit pixel and a second unit pixel adjacent to the first unit pixel in a first direction;
A first gate line and a second gate line extending in a second direction intersecting with the first direction and electrically connected to the first unit pixel and the second unit pixel, respectively;
A first data line and a second data line extending in the first direction and electrically connected to the first unit pixel and the second unit pixel, respectively;
A first charge control line and a second charge control line extending in the second direction and electrically connected to the first unit pixel and the second unit pixel, respectively; And
And a sustain line to which a common voltage is applied,
Wherein the first unit pixel and the second unit pixel each include a first sub-pixel and a second sub-pixel,
The first charge control line and the second charge control line are connected to the second sub-pixel of the first unit pixel and the second sub-pixel of the second unit pixel, respectively,
Wherein the first gate line and the second gate line are simultaneously applied with a first voltage,
Wherein the first charge control line is applied with a second voltage after the first voltage is applied to the first gate line and the second gate line,
The first voltage is applied to the first gate line and the second gate line through the first voltage supply unit,
And the second voltage is applied to the first charge control line through a second voltage supply unit separated from the first voltage supply unit.

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