CN111108432A

CN111108432A - Display screen and terminal equipment

Info

Publication number: CN111108432A
Application number: CN201880061419.4A
Authority: CN
Inventors: 李文兵; 马磊; 张峰; 王振伟
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-02-11
Filing date: 2018-02-11
Publication date: 2020-05-05
Also published as: WO2019153299A1

Abstract

The utility model provides a display screen and terminal equipment, relates to and shows technical field, can reduce the display screen and show the probability that unusual phenomena such as horizontal line or scintillation appear in-process. The display screen is provided with an opening (10). The display screen comprises an array substrate (100) and a box aligning substrate (200) which are oppositely arranged, and a liquid crystal layer (300) is arranged between the array substrate (100) and the box aligning substrate (200). In addition, the array substrate (100) comprises a first insulating layer (301) and a common electrode layer (500). The common electrode layer (500) is located above the first insulating layer (301). Between the opening (10) and the effective display area of the display screen, a Grid Line (GL) is arranged on the lower surface of the first insulating layer (301). An auxiliary conductive layer (20) is provided over the first insulating layer (301) between the opening (10) and the effective display area of the display screen. The auxiliary conductive layer (20) is in the same layer as the common electrode layer (500). The display screen is used for displaying images.

Description

Display screen and terminal equipment

Technical Field

The application relates to the technical field of display, in particular to a display screen and terminal equipment.

Background

With the development of diversified functions of display devices, such as mobile phones, a variety of devices for implementing different functions, such as cameras, receivers, and photosensitive devices for collecting fingerprints, are integrated in the mobile phones. Based on this, in order to increase the screen occupation ratio (the ratio of the effective display area of the display screen to the whole display screen) of the display screen of the mobile phone, as shown in fig. 1a, in the prior art, an opening 10 is usually formed on the display screen, so that the camera, the receiver, the photosensor and other components can be disposed in the opening 10. On the basis, the parts of the display screen positioned at the two sides of the opening 10 can still display without adopting a shading material for shading, thereby achieving the purpose of improving the display screen ratio.

However, due to the presence of the above-mentioned openings 10 in the display screen, sub-pixels cannot be arranged at the positions of the openings 10. In this case, in fig. 1a, the sub-pixels (i.e. the sub-pixels in the same row) driven by the same row of gate lines on both sides of the opening 10 need to be disposed on both sides of the opening 10 by bypassing the opening 10, so that the whole row arrangement cannot be realized, and the sub-pixels in the same row under the opening 10 can be arranged in the whole row without being affected by the opening 10. Therefore, the number of the sub-pixels in the same row on both sides of the opening 10 is smaller than the number of the sub-pixels in the same row under the opening 10. Therefore, in the display process of the display screen, the charging time of a row of sub-pixels at two sides of the opening 10 and the charging time of a row of sub-pixels below the opening 10 are different, so that the deflection speed of the liquid crystal molecules at two sides of the opening 10 is different from the deflection speed of the liquid crystal molecules below the opening 10, and abnormal phenomena such as horizontal stripes or flicker occur in the display process of the display screen.

Disclosure of Invention

The embodiment of the invention provides a display screen and terminal equipment, which can reduce the probability of abnormal phenomena such as transverse striations or flicker and the like in the display process of the display screen under the condition that the display screen is provided with a slotted zone.

In order to achieve the above purpose, the following technical solutions are adopted in this embodiment:

in a first aspect, a display screen is provided, wherein the display screen has an opening. In addition, the display screen comprises an array substrate and a box aligning substrate which are oppositely arranged, and a liquid crystal layer is arranged between the array substrate and the box aligning substrate. The array substrate comprises a first insulating layer. And a grid line is arranged on the lower surface of the first insulating layer between the opening and the effective display area of the display screen. In addition, the array substrate further comprises an auxiliary conducting layer arranged between the opening and the effective display area of the display screen and above the first insulating layer. In this case, a capacitor, referred to as a first capacitor, may be formed between the auxiliary conductive layer and the gate line between the opening and the active display area of the display screen. The auxiliary conductive layer may be supplied with the same voltage as the common electrode layer during display. At this time, the voltage across the gate line between the opening and the effective display area of the display screen needs to charge the first capacitor, so that the load across the gate line between the opening and the effective display area of the display screen can be increased, and the charging time of at least one row of sub-pixels in the display areas at two sides of the opening is reached, so that the charging time of one row of sub-pixels at two sides of the opening is the same or substantially the same as that of one row of sub-pixels below the opening. Thus, the deflection speed of the liquid crystal molecules corresponding to the display area positions on the two sides of the opening is approximately the same as the deflection speed of the liquid crystal molecules corresponding to the display area positions below the opening, so that the probability of abnormal phenomena such as transverse striations or flicker can be reduced.

With reference to the first aspect, in a design of applying the array substrate to a liquid crystal display panel, the array substrate further includes a common electrode layer, and the common electrode layer is located above the first insulating layer. In order to simplify the manufacturing process, the auxiliary conductive layer may be formed on the same layer as the common electrode layer by a single mask and exposure process.

Optionally, in a design of applying the array substrate to a liquid crystal display, the auxiliary conductive layer and the common electrode layer are integrated. During the display, only the common voltage needs to be supplied to the common electrode layer, and the auxiliary conductive layer may receive the common voltage.

Optionally, in the design of applying the array substrate to the liquid crystal display, the first insulating layer is a gate insulating layer; the array substrate further comprises a data line in contact with the upper surface of the gate insulating layer, a second insulating layer covering the upper surface of the data line, a pixel electrode positioned on the upper surface of the second insulating layer, and a third insulating layer positioned on the upper surface of the pixel electrode. In this case, the auxiliary conductive layer in the same layer as the common electrode layer is located on the upper surface of the third insulating layer. A scheme of providing an auxiliary conductive layer on an array substrate having a bottom gate type TFT is realized.

Optionally, in the design of applying the array substrate to the liquid crystal display, the first insulating layer is a gate insulating layer; the array substrate further comprises a data line contacting the upper surface of the gate insulating layer, and a second insulating layer covering the upper surface of the data line. In this case, the auxiliary conductive layer in the same layer as the common electrode layer is located on the upper surface of the second insulating layer. Another scheme of providing an auxiliary conductive layer on an array substrate having a bottom gate type TFT is realized.

Optionally, in a design of applying the array substrate to a liquid crystal display, the array substrate further includes a gate insulating layer; the gate line is on the upper surface of the gate insulating layer. In addition, the array substrate further comprises a pixel electrode positioned on the upper surface of the first insulating layer, and a third insulating layer positioned on the upper surface of the pixel electrode. In this case, the auxiliary conductive layer in the same layer as the common electrode layer is located on the upper surface of the third insulating layer. Or, the array substrate further comprises a data line in contact with the upper surface of the first insulating layer, a second insulating layer covering the data line, a pixel electrode on the upper surface of the second insulating layer, and a third insulating layer on the upper surface of the pixel electrode. In this case, the auxiliary conductive layer in the same layer as the common electrode layer is located on the upper surface of the third insulating layer. The scheme of arranging the auxiliary conductive layer on the array substrate with the top gate type TFT is realized.

Optionally, in the design of applying the array substrate to the liquid crystal display screen, the line width of the gate line between the opening and the effective display area of the display screen is greater than the line width of the gate line in the effective display area. Thereby increasing the load across the gate lines between the openings and the active display area of the display screen.

Optionally, in a design that the array substrate is applied to a liquid crystal display screen, a data line crossing the gate line is disposed above the first insulating layer between the opening and the effective display area of the display screen. In addition, two adjacent data lines and two adjacent gate lines cross to define a dummy sub-pixel. Wherein, a thin film transistor is also arranged in the dummy sub-pixel. The grid electrode of the thin film transistor is connected with the grid line, the first electrode of the thin film transistor is connected with the data line, and the second electrode of the thin film transistor is vacant. The parasitic capacitance of the TFT disposed in the dummy sub-pixel can increase the number of capacitances connected through the gate line between the opening and the effective display area of the display screen, thereby achieving an increase in the load through the gate line between the opening and the effective display area of the display screen.

Optionally, in a design of applying the array substrate to the liquid crystal display panel, the auxiliary conductive layer includes at least one row of sub-electrodes disposed at intervals and electrically connected to each other. The orthographic projection of the grid line between the opening and the effective display area of the display screen on the substrate of the array substrate is overlapped with at least part of the orthographic projection of the at least one row of sub-electrodes on the substrate. The larger the overlapping area of the orthographic projection of the sub-electrode on the array substrate and the orthographic projection of the grid line passing through the opening and the effective display area of the display screen on the substrate is, the larger the capacitance connected with the grid line passing through the opening and the effective display area of the display screen is. Therefore, the compensation quantity of the capacitance connected with the grid line passing through the opening and the effective display area of the display screen can be obtained, and then the distribution density and the shape of the row of sub-electrodes covering the grid line are set according to the compensation quantity, so that the purpose of capacitance compensation is achieved.

Optionally, in a design that the array substrate is applied to a liquid crystal display, an orthogonal projection of a gate line between the opening and the effective display area of the display screen on a substrate of the array substrate overlaps at least a part of an orthogonal projection of the auxiliary conductive layer on the substrate, so that a part of the auxiliary conductive layer can be used as one electrode plate of the capacitor, and the gate line which passes through the opening and the effective display area of the display screen and overlaps the orthogonal projection with the auxiliary conductive layer is used as the other electrode plate of the capacitor.

Optionally, in a design of applying the array substrate to the liquid crystal display screen, the opening is a groove disposed on at least one side of the display screen and recessed toward the inside of the display screen. The groove is used for arranging a receiver, a sensor, a transmitter and the like.

In combination with the first aspect, in the design of applying the array substrate to the OLED display screen, the array substrate further includes an upper electrode, the upper electrode is located above the first insulating layer, and in order to simplify the manufacturing process, an auxiliary conductive layer on the same layer as the upper electrode may be formed by using a single mask and an exposure process.

Optionally, in the design of applying the array substrate to the OLED display screen, the array substrate further includes a pixel defining layer located above the first insulating layer. The auxiliary conductive layer is located on the upper surface of the pixel defining layer.

Optionally, in the design of applying the array substrate to the OLED display screen, the line width of the gate line between the opening and the effective display area of the display screen is greater than the line width of the gate line in the effective display area. Thereby increasing the load across the gate lines between the openings and the active display area of the display screen.

Optionally, in the design of applying the array substrate to the OLED display screen, a data line crossing the gate line is disposed above the first insulating layer between the opening and the effective display area of the display screen. In addition, two adjacent data lines and two adjacent gate lines cross to define a dummy sub-pixel. Wherein, a thin film transistor is also arranged in the dummy sub-pixel. The grid electrode of the thin film transistor is connected with the grid line, the first electrode of the thin film transistor is connected with the data line, and the second electrode of the thin film transistor is vacant. The parasitic capacitance of the TFT disposed in the dummy sub-pixel can increase the number of capacitances connected through the gate line between the opening and the effective display area of the display screen, thereby achieving an increase in the load through the gate line between the opening and the effective display area of the display screen.

Optionally, in the design of applying the array substrate to the OLED display screen, the auxiliary conductive layer includes at least one row of sub-electrodes disposed at intervals and electrically connected to each other. The orthographic projection of the grid line between the opening and the effective display area of the display screen on the substrate of the array substrate is overlapped with at least part of the orthographic projection of the at least one row of sub-electrodes on the substrate. The larger the overlapping area of the orthographic projection of the sub-electrode on the array substrate and the orthographic projection of the grid line passing through the opening and the effective display area of the display screen on the substrate is, the larger the capacitance connected with the grid line passing through the opening and the effective display area of the display screen is. Therefore, the compensation quantity of the capacitance connected with the grid line passing through the opening and the effective display area of the display screen can be obtained, and then the distribution density and the shape of the row of sub-electrodes covering the grid line are set according to the compensation quantity, so that the purpose of capacitance compensation is achieved.

Optionally, in a design that the array substrate is applied to an OLED display screen, an orthogonal projection of a gate line between the opening and the effective display area of the display screen on a substrate of the array substrate overlaps at least a part of an orthogonal projection of the auxiliary conductive layer on the substrate, so that a part of the auxiliary conductive layer may serve as one electrode plate of the capacitor, and the gate line, which passes through between the opening and the effective display area of the display screen and overlaps with the auxiliary conductive layer in the orthogonal projection, serves as the other electrode plate of the capacitor.

Optionally, in a design of applying the array substrate to an OLED display screen, the opening is a groove disposed on at least one side of the display screen and recessed into the display screen. The groove is used for arranging a receiver, a sensor, a transmitter and the like.

In a second aspect, a display screen is provided, wherein the display screen has an opening. In addition, the display screen comprises an array substrate and a box aligning substrate which are oppositely arranged, and a liquid crystal layer is arranged between the array substrate and the box aligning substrate. The array substrate comprises a first insulating layer. And a grid line is arranged on the lower surface of the first insulating layer between the opening and the effective display area of the display screen. In addition, the pair of box substrates further comprise an auxiliary conducting layer, and the orthographic projection of the auxiliary conducting layer on the substrate of the substrate is positioned between the opening and the effective display area of the display screen. The display screen has the same technical effects as the display screen provided by the first aspect, and the details are not repeated here.

With reference to the second aspect, in a design of applying the array substrate to a liquid crystal display panel, the pair of cell substrates further includes a common electrode layer. In order to simplify the manufacturing process, the auxiliary conductive layer may be formed on the same layer as the common electrode layer by using a single mask and exposure process.

In a third aspect, a terminal device is provided, which comprises any one of the display screens described above. The terminal device has the same technical effect as the display screen, and the description is omitted here.

Drawings

Fig. 1a is a schematic structural diagram of an appearance of a display screen provided in the present application;

fig. 1b is a schematic structural diagram of an appearance of a display screen provided in the present application;

fig. 2 is a schematic longitudinal cross-sectional structural diagram of a display screen according to an embodiment of the present disclosure;

FIG. 3 is a schematic structural diagram of an array substrate in the display panel shown in FIG. 2;

FIG. 4a is a schematic view of an active area of the display screen shown in FIG. 1 a;

FIG. 4b is a schematic diagram illustrating a region division of the active display area shown in FIG. 4 b;

fig. 5 is a schematic structural diagram of an array substrate provided in the present application;

fig. 6 is a schematic structural diagram of an array substrate provided in the present application;

fig. 7 is a schematic longitudinal cross-sectional view of a display panel with bottom gate TFTs according to the present application;

fig. 8 is a schematic longitudinal cross-sectional view of a display panel with a top gate TFT according to the present application;

fig. 9 is a schematic view of another longitudinal cross-sectional structure of a display panel having a top gate type TFT provided in the present application;

FIG. 10 is a schematic top view of a sub-pixel of the structure shown in FIG. 2;

fig. 11 is a schematic diagram of a capacitance compensation scheme provided in an embodiment of the present application based on the structure shown in fig. 6;

FIG. 12 is a schematic diagram of the principle of capacitance compensation for the structure shown in FIG. 11;

FIG. 13 is a schematic diagram of another capacitance compensation scheme provided in an embodiment of the present application based on the structure shown in FIG. 6;

FIG. 14 is a schematic diagram of another capacitance compensation scheme provided in an embodiment of the present application based on the structure shown in FIG. 6;

fig. 15 is a schematic structural diagram of an external appearance of another display screen provided in the present application;

FIG. 16 is a schematic diagram of a capacitance compensation scheme provided by an embodiment of the present application in conjunction with the structures shown in FIGS. 15 and 6;

fig. 17 is a schematic diagram illustrating a driving method of a display panel provided in the present application;

FIG. 18 is a schematic longitudinal cross-sectional view of yet another display screen provided herein;

fig. 19 is a schematic structural diagram of an array substrate of an OLED display panel provided in the present application;

FIG. 20 is a schematic view of a sub-pixel of FIG. 19;

fig. 21 is a schematic longitudinal sectional structure view of an OLED display device having the array substrate shown in fig. 19.

Reference numerals:

01-a substrate; 10-opening; 11-sub display area; 12-a main display area; 20-auxiliary conductive layer; 40-dummy sub-pixels; 51-the first subsection; 52-second subsection; 60-an upper electrode; 61-a lower electrode; 62-a functional layer of organic material; 63-a pixel defining layer; 100-an array substrate; 200-pair of cassette substrates; 300-a liquid crystal layer; 301-a first insulating layer; 302-a second insulating layer; 303 — a third insulating layer; 400-a package substrate; 210-a filter unit; 201-sub-electrodes; 500-a common electrode layer; 501-pixel electrode.

Detailed Description

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present application, "a plurality" means two or more unless otherwise specified.

The Display screen related to the embodiment of the application can be a Thin Film Transistor-Liquid Crystal Display (TFT-LCD).

As can be seen from the partial longitudinal sectional structure of the TFT-LCD shown in fig. 2, the TFT-LCD includes an array substrate 100 and a pair of cell substrates 200 which are oppositely disposed. In addition, the TFT-LCD further includes a liquid crystal layer 300 disposed between the array substrate 100 and the opposite cell substrate 200.

As shown in fig. 2, the array substrate 100 includes a substrate 01 and thin film layers sequentially formed on the substrate 01. A part of the thin film layers in the array substrate 100 will be described below. For example, the array substrate 100 includes a first insulating layer 301 and a Common electrode layer (Common electrode layer) 500. The common electrode layer 500 is located above the first insulating layer 301. In addition, the lower surface of the first insulating layer 301 is provided with a Gate Line (GL) as shown in fig. 3 and a drain electrode of a TFT in the same layer as the GL as shown in fig. 2. In the following description of the present application, an insulating layer covering the GL and the upper surface of the gate g of the TFT in the same layer as the GL will be referred to as a first insulating layer 301.

In the array substrate 100 of the present invention, a thin film layer above a thin film layer, for example, a thin film layer above the first insulating layer 301 refers to a thin film layer, for example, the common electrode layer 500, which is formed on a side of the first insulating layer 301 away from the substrate 01 after the first insulating layer 301 is formed on the substrate 01. At this time, at least one other thin film layer may be provided between the common electrode layer 500 and the first insulating layer 301. For example, in fig. 2, an Active Layer (AL) of the TFT, a source s and a drain d of the TFT, and the second insulating Layer 302 are provided in this order between the first insulating Layer 301 and the common electrode Layer 500 in a direction away from the substrate 01. Fig. 2 is a distance description of only one structure of the array substrate, and the present application is not limited thereto.

As shown in fig. 3, the array substrate 100 is further provided with Data Lines (DL) crossing the GL lines. The DL may be provided in the same layer as the source s or drain d of the TFT in fig. 2.

In the array substrate 100, some thin film layers may be formed over the substrate 01 by a film forming process (e.g., the first insulating layer 301 formed by a coating process), and some thin film layers may be patterned to form predetermined patterns (e.g., GL, DL, the gate g, the source s, and the drain d of the TFT). The patterning process includes a photolithography process, an etching step, and the like for forming a predetermined pattern. The photoetching process comprises the process of forming a film, masking, exposing, developing and the like, wherein patterns are formed by using a photoresist, a mask plate, an exposure machine and the like. The substrate 01 may be a glass substrate or a substrate made of an organic material. This is not limited in this application.

A method for forming a thin film layer having a pattern by a photolithography process will be described with reference to the formation of a gate g of a DL and a TFT. Specifically, a film forming process, such as a deposition process, is performed on the substrate 01 to form a metal thin film layer (for example, the metal thin film layer may be made of molybdenum), a photoresist is coated on the metal thin film layer, and then the photoresist is subjected to mask exposure by using a mask plate, so that one part of the photoresist is irradiated by light passing through the mask plate, and the other part of the photoresist is shielded by a light shielding region on the mask plate and is not irradiated by the light; next, developing the photoresist, taking the photoresist as positive photoresist as an example, and dissolving the part irradiated by the light on the photoresist under the action of a developing solution so as to expose the metal thin film layer; then etching the metal film layer exposed from the developed area on the photoresist; next, the photoresist is stripped, so that a thin film layer having a preset pattern including a plurality of DL patterns and a pattern of the gate electrode g of the TFT connected to the DL can be formed.

Based on this, as shown in fig. 3, a rectangular region defined by crossing two adjacent GL lines and two adjacent DL lines in a horizontal and vertical direction is referred to as a Sub Pixel (Sub Pixel). In each sub-pixel, one TFT is provided at the intersection of GL and DL. The TFT has a gate g connected to GL, a first electrode connected to DL, and a second electrode connected to the pixel electrode 501. The first pole of the TFT can be a source electrode s of the TFT, and the second pole can be a drain electrode d of the TFT; alternatively, the first pole of the TFT may be the drain d of the TFT and the second pole may be the source s of the TFT.

In addition, the TFT-LCD further includes a color filter layer disposed on the array substrate 100, or as shown in fig. 2, disposed on the opposite-to-box substrate 200, and the color filter layer includes a plurality of filter units 210. At least three sub-pixels arranged in sequence constitute one Pixel (Pixel). The position of each sub-Pixel in the Pixel (Pixel) corresponds to the position of the filtering unit 210 of one color, so that the three sub-pixels in the Pixel (Pixel) can emit light of different colors, for example, red (R), green (G) and blue (B) under the filtering action of different filtering units 210.

The opposing substrate 200 provided with the color filter layer may be referred to as a color filter substrate. As shown in fig. 2, a Black Matrix (BM) for shielding DL, GL and TFTs on the array substrate 100 is provided on the cartridge substrate 200.

On the basis, as shown in fig. 4a, the display screen provided by the present application is provided with an opening (Notch) 10. Specifically, in the production process, a special-shaped cutting process may be adopted to cut off local areas of the array substrate 100 and the color filter substrate 200 in the same position in the display screen, which is originally a whole surface, so as to form the opening 10. In this case, the opening 10 can be used for placing a camera, a receiver, a sensor, a microphone, and the like which need to be integrated in the display screen.

For example, as shown in fig. 1a, a part of the display screen may be cut inward at one edge (e.g., an upper edge) of the array substrate 100 to form the opening 10, where the opening 10 is a groove recessed toward the inside of the display screen. In this case, the edge of the opening 10 may be a part of the edge (edge) of the display screen. Alternatively, as shown in fig. 1b, a part of the structure of the display screen may be cut away from the area surrounded by the four sides of the display screen to form an opening 10, and at this time, any one side of the display screen still maintains its original shape. For convenience of description, the opening 10 is a groove, and the groove is disposed at the middle position of the edge above the display screen, as shown in fig. 1 a.

In this case, under the influence of the opening 10, as shown in fig. 4a, the Active Area (AA) of the display screen needs to bypass the opening 10, so that the Active Area of the display screen is no longer a complete rectangle. In this case, as shown in fig. 4b, the effective display area of the display screen may be divided into sub display areas 11 located on both sides of the opening 10 and a main display area 12 located below the opening 10 and the sub display areas.

As shown in fig. 3, the sub-pixels in the main display region 12 are arranged in a matrix, and along the extending direction of the GL, the gates g of the TFTs in the sub-pixels in the same row in the main display region 12 are electrically connected to the same GL. Based on this, the sub-pixels in the main display area 12 receiving the same GL output signal are uniformly arranged from the left end (or right end) to the right end (or left end) of the array substrate 100. In this case, the main display region 12 is arranged with a plurality of rows of subpixels in a whole row.

In addition, in the sub-display regions 11 located at both sides of the opening 10, the gates g of the TFTs in the sub-pixels of the same row still need to be connected to the same GL, but due to the above-mentioned opening 10, the GL in the sub-display region 11 at the left side of the opening 10 needs to pass through the region between the opening 10 and the effective display region of the display screen to be routed around the opening 10 and then extend into the sub-display region 11 at the right side of the opening 10, thereby electrically connecting the gates g of the TFTs in the sub-pixels at the left and right sides of the opening 10 located in the same row.

Alternatively, the width of the area between the opening 10 and the effective display area of the display screen is generally less than or equal to about 1 mm.

In this application, the directional terms "left", "right", "upper" and "lower" are defined with respect to the schematically placed orientation of the array substrate or display screen in the drawings, and it is to be understood that these directional terms are relative concepts, which are used for relative description and clarification, and may be changed accordingly according to the change of the placed orientation of the array substrate or display screen.

As can be seen from the above, as shown in fig. 3, in the sub-display regions 11 on both sides of the opening 10, the sub-pixels receiving the output signal of the same GL are affected by the opening 10, and the whole row arrangement cannot be realized. Therefore, the number of sub-pixels in a row in the sub-display region 11 is smaller, and the number of sub-pixels in a row in the main display region 12 is larger.

On this basis, as shown in fig. 5, the common electrode layer 500 in the array substrate 100 is distributed in the entire effective display area of the display screen. Wherein, the orthographic projection of the pixel electrode 501 in each sub-pixel in the effective display area on the substrate 01 of the array substrate is overlapped with at least one part of the orthographic projection of the common electrode layer 500 on the substrate 01.

In addition, as can be seen from fig. 2, since the common electrode layer 500 and the pixel electrode 501 are different layers, an insulating layer is provided between the common electrode layer 500 and the pixel electrode 501, and the insulating layer is referred to as a third insulating layer 303 in this application. The material of the third insulating layer 303 may be silicon nitride. In this case, the common electrode layer 500 and the pixel electrodes 501 are disposed in an insulating manner, so that a capacitor for controlling the deflection of liquid crystal molecules, referred to as a liquid crystal capacitor C, is formed between each pixel electrode 501 and the common electrode layer 500_LC。

Based on this, when a row GL receives a gate scan signal, the TFTs in the respective sub-pixels controlled by the row GL may be driven to be turned on. At this time, each DL transmits a data voltage Vdata to the pixel electrode 501 through the turned-on TFT to charge the subpixel. In addition, the common electrode layer 500 is supplied with a common voltage Vcom. In this case, the liquid crystal capacitance C formed by the common electrode layer 500 and the pixel electrode 501_LCThe liquid crystal molecules at the corresponding position of the sub-pixel where the pixel electrode 501 is located can be controlled to deflect, so that the transmittance of light emitted by each sub-pixel can be controlled, and the display of each gray scale can be realized. In addition, the light rays may realize color display by the color filtering of each filtering unit 210 in the color filtering layer. As can be seen from the above, the number of sub-pixels in a row in the sub-display region 11 is smaller in fig. 5, and the number of sub-pixels in a row in the main display region 12 is larger. Therefore, in order to reduce the difference in the charging time of a row of sub-pixels of the sub-display region 11 and a row of sub-pixels of the main display region 12, the present application provides the following embodiments.

Example one

As shown in fig. 5, the array substrate 100 of the display panel provided by the present application further includes an auxiliary conductive layer 20 disposed between the opening 10 and the active display area of the display panel and above the first insulating layer 301. In addition, as can be seen from the above, GL between the opening 10 and the effective display area of the display screen is disposed on the lower surface of the first insulating layer 301. The auxiliary conductive layer 20 and the GL between the opening 10 and the active area of the display screen may be arranged in different layers and insulated. Optionally, an orthographic projection of the GL between the opening and the effective display area of the display screen on the substrate 01 of the array substrate 100 overlaps at least a part of an orthographic projection of the auxiliary conductive layer 20 on the substrate 01. Therefore, a capacitance, referred to as a first capacitance C1, may be formed between the auxiliary conductive layer 20 and GL between the opening 10 and the active display area of the display screen.

For convenience of description, as shown in fig. 5, the GL disposed between the opening and the effective display area of the display screen is referred to as a first gate line, abbreviated as GL 1. The GL1 can extend to the sub-display region 11 and be electrically connected to the gate g of the TFT in the sub-pixel of the sub-display region 11, thereby controlling the sub-pixel in the sub-display region 11. In addition, GL disposed in the main display region 12 is referred to as a second gate line, abbreviated as GL 2.

In this case, during the display process, the same voltage as that of the common electrode layer 500, i.e. the common voltage Vcom, may be provided to the auxiliary conductive layer 20, and at this time, the voltage on the GL1 needs to be charged to the auxiliary conductive layer 20 and the GL1 to form the first capacitor C1, so that the load of the GL1 can be increased, and the charging time of at least one row of sub-pixels in the sub-display region 11 is prolonged, so that the charging time of one row of sub-pixels in the sub-display region 11 is the same or substantially the same as that of one row of sub-pixels in the main display region 12. Thus, the deflection speed of the liquid crystal molecules corresponding to the position of the sub display region 11 is approximately the same as the deflection speed of the liquid crystal molecules corresponding to the position of the main display region 12.

Specifically, for example, the sub-display area 11 and the main display area 12 are both converted from a black frame to a white frame for displaying, and since the deflection speeds of the liquid crystal molecules corresponding to the two pixel areas are approximately the same, the light provided by the backlight module does not pass through the liquid crystal molecules corresponding to the sub-display area 11 in advance, so that the sub-display area 11 displays a white frame in preference to the main display area 12, and the probability of abnormal phenomena such as horizontal stripes or flickering caused by the difference between the sub-display area 11 and the main display area 12 displaying the white frame can be reduced.

In view of the above, the present application does not limit the material of the auxiliary conductive layer 50 and the position of the auxiliary conductive layer 50 on which thin film layer is located in the array substrate 100, as long as the auxiliary conductive layer 50 is located between the opening 10 and the display panel effective display area and above the first insulating layer 301.

In this case, since the area between the opening 10 and the effective display area of the display panel cannot display an image, the area needs to be shielded by the black matrix BM on the cell substrate 200, and thus the material of the auxiliary conductive layer 20 is selected without affecting the display effect. In this case, the material for forming the auxiliary conductive layer 20 may be selected from materials used for preparing the thin film layer having a conductive function in the array substrate 100. For example, a metal material (e.g., molybdenum metal) constituting the GL, or a metal material (e.g., an aluminum-titanium alloy) constituting the DL, or a transparent conductive material (e.g., Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO)) constituting the common electrode layer 500 and the pixel electrode 501 is used.

As described above, since the common electrode layer 500 is also located above the first insulating layer 301, the auxiliary conductive layer 20 may be disposed in the same layer as the common electrode layer 500. Based on this, in order to simplify the manufacturing process, as shown in fig. 6, the auxiliary conductive layer 20 and the common electrode layer 500 may be an integral structure, and thus may be formed through a single mask exposure process.

Hereinafter, the manner of disposing the auxiliary conductive layer 20 will be described with respect to the array substrate 100 having a different structure, based on the fact that the auxiliary conductive layer 20 and the common electrode layer 500 may be integrally configured.

Specifically, for example, as shown in fig. 2 or fig. 7, a bottom gate TFT is formed on the array substrate 100 and is used as a TFT in each sub-pixel. In the bottom Gate TFT, as shown in fig. 2 or 7, a Gate electrode g of the TFT is formed on a substrate 01 in advance of a Gate Insulator (GI) provided between an AL of the TFT and the Gate electrode g of the TFT. In this case, the first insulating layer 301 covering the upper surface of the GL is the gate insulating layer, and the material of the gate insulating layer may be silicon nitride or silicon oxide.

In this case, as shown in fig. 2, the array substrate 100 further includes a DL (the same layer as the source s and the drain d of the TFT) contacting the upper surface of the gate insulating layer (i.e., the first insulating layer 301), a second insulating layer 302 covering the upper surface of the DL, and a common electrode layer 500 on the upper surface of the second insulating layer 302. Since the auxiliary conductive layer 20 is disposed on the same layer as the common electrode layer 500, the auxiliary conductive layer 20 is disposed on the upper surface of the second insulating layer 302.

In this embodiment, the insulating layer between the DL and the transparent electrode (e.g., the common electrode layer 500 or the pixel electrode 501) is referred to as a second insulating layer. The upper surface of the second insulating layer 302 is used to fabricate a transparent electrode, and in order to improve the flatness of the transparent electrode, the material that can be selected to form the second insulating layer 302 may be an organic resin material.

On this basis, the upper surface of the common electrode layer 500 has a third insulating layer 303, the upper surface of the third insulating layer 303 has a pixel electrode 501, and the pixel electrode 501 is electrically connected to the drain d of the TFT through a via hole formed in the third insulating layer 303, the common electrode layer 500, and the second insulating layer 302.

Fig. 2 illustrates an example in which the pixel electrode 501 is located above the common electrode layer 500. In addition, as shown in fig. 7, the pixel electrode 501 may also be located below the common electrode layer 500. In this case, the array substrate 100 includes a DL (the same layer as the source s and drain d of the TFT) contacting the upper surface of the gate insulating layer (i.e., the first insulating layer 301), a second insulating layer 302 covering the upper surface of the DL, a pixel electrode 501 on the upper surface of the second insulating layer 302, a third insulating layer 303 on the upper surface of the pixel electrode 501, and a common electrode layer 500 on the upper surface of the third insulating layer 303. In this case, the auxiliary conductive layer 20 in the same layer as the common electrode layer 500 is also located on the upper surface of the third insulating layer 303.

Alternatively, for example, as shown in fig. 8 or 9, the TFT formed in each sub-pixel on the array substrate 100 is a top gate TFT. In the top Gate TFT, as shown in fig. 8 or 9, the AL of the TFT is formed on the substrate 01 in advance of a Gate Insulator (GI) provided between the AL of the TFT and the Gate g of the TFT. At this time, GL in the same layer as the gate g of the TFT is located on the upper surface of the gate insulating layer. The TFT having the top gate structure may be manufactured using a Low Temperature Poly Silicon (LTPS) process. The TFT prepared by the LTPS process has better conductivity and higher mobility.

In this case, as shown in fig. 8, the array substrate 100 further includes a pixel electrode 501 on the upper surface of the first insulating layer 301, and a DL (on the same layer as the source s and drain d of the TFT) on the upper surface of the pixel electrode 501, and a third insulating layer 303 on the upper surfaces of the DL and the pixel electrode 501. In this case, the auxiliary conductive layer 20 in the same layer as the common electrode layer 500 is also located on the upper surface of the third insulating layer 303.

Fig. 8 illustrates an example in which the pixel electrode 501 is located below the drain d (or DL) of the TFT. In addition, as shown in fig. 9, the pixel electrode 501 may also be positioned above the drain electrode d (or DL) of the TFT. In this case, the array substrate 100 further includes a DL (in the same layer as the source s and drain d of the TFT) contacting the upper surface of the first insulating layer 301, a second insulating layer 302 covering the DL, a pixel electrode 501 on the upper surface of the second insulating layer 302, and a third insulating layer 303 on the upper surface of the pixel electrode 501. In this case, the auxiliary conductive layer 20 in the same layer as the common electrode layer 500 is also located on the upper surface of the third insulating layer 303.

In addition, fig. 8 and 9 both illustrate an example in which the common electrode layer 500 is located above the pixel electrode 501. When the common electrode layer 500 is located below the pixel electrode 501, the structure of the array substrate can be configured with reference to fig. 2, and is not described herein again.

As can be seen from the above, the common electrode layer 500 and the pixel electrode 501 in fig. 2, 7, 8 and 9 are all formed on the array substrate 100. In this case, of the common electrode layer 500 and the pixel electrode 501, an upper electrode is a slit-shaped electrode, and a lower electrode is a planar electrode. For example, taking the structure shown in fig. 2 as an example, the pixel electrode 501 is located above, and the common electrode layer 500 is located below, so that the pixel electrode 501 is slit-shaped, and the common electrode layer 500 is planar, and in this case, the specific structure of the slit-shaped pixel electrode 501 and the planar common electrode layer 500 in one sub-pixel is as shown in fig. 10. In this case, the display panel formed by using the array substrate 100 is a Fringe Field Switching (FFS) type display panel. The FFS type display screen can form a multi-dimensional electric field by a parallel electric field generated by the edge of a slit-shaped electrode (for example, the pixel electrode 501 in fig. 10) in a plane and a longitudinal electric field generated between the pixel electrode 501 and the common electrode layer 500, so that all liquid crystal molecules in the liquid crystal layer 300 between the slits of the pixel electrode 501 and between the pixel electrode 501 and the common electrode layer 500 can be driven to deflect, thereby improving the light transmission efficiency of the liquid crystal layer and improving the display quality.

In addition to fig. 10, in the top view of the array substrate 100, the pixel electrode 501 is simplified and not shown in a slit-like structure.

Example two

In the solution of the present embodiment, a plurality of Dummy (Dummy) sub-pixels 40 are disposed between the opening 10 and the effective display area of the display screen.

Specifically, as shown in fig. 11, a DL crossing GL (i.e., GL1) is disposed above the first insulating layer 301 between the opening 10 and the effective display area of the display panel. Wherein two adjacent DLs and two adjacent GL intersect to define a dummy subpixel 40. A TFT is also provided in the dummy subpixel 40. The TFT has gate g connected to DL, first pole connected to GL, and second pole left vacant. Since the second polarity of the TFT in the dummy subpixel 40 is empty, the pixel electrode 501 to which the second polarity of the TFT is connected is not provided in the subpixel 40, and thus the dummy subpixel 40 cannot perform display.

It should be noted that, a data line may be formed by using a metal line in a different layer from the DL and GL, and one data line is electrically connected to one DL in the main display region 12. The dummy sub-pixel 40 is defined by the intersection of two adjacent data lines and two adjacent GL lines. As described above, the auxiliary conductive layer 20 integrated with the common electrode layer 500 is formed separately and insulated from GL1, and the first capacitor C1 is formed between the auxiliary conductive layer 20 and GL 1. In the main display region 12, the common electrode layer 500 is formed separately from and insulated from GL2, and a second capacitor C2 may be formed between the common electrode layer 500 and GL 2. In the case where GL1 and GL2 are made of the same material and have the same line width, the capacitance values of the first capacitor G1 and the second capacitor G2 may be the same or approximately the same. In this case, during the display process, the interference of the gate scanning signal of the pulse wave in GL1 on the auxiliary conductive layer 20 is the same as or approximately the same as the interference of the gate scanning signal in GL2 on the common electrode layer 500, so that the difference between the sub display region 11 and the main display region 12 can be reduced.

In addition, as can be seen from the above, the gate g and the GL of the TFT are made of the same material, and the source s and the drain d of the TFT are made of the same material as the DL. Therefore, the TFT itself has parasitic capacitances, for example, a parasitic capacitance Cgs between the gate g and the source s, and a parasitic capacitance Cgd between the gate g and the drain d. Therefore, by providing the dummy sub-pixels 40 described above, it is possible to form a plurality of parasitic capacitances of the TFTs between the openings 10 and the effective display area of the display screen.

Based on this, for example, the number of subpixels controlled by GL1 is m, and in this case, as shown in (a) of fig. 12, GL1 is connected with m liquid crystal capacitors C_LC(ii) a In the main display region 12, the number of the sub-pixels connected to GL2 is n, and in this case, as shown in fig. 12 (b), n liquid crystal capacitors C are connected to GL2_LC. Wherein n is more than m, and n and m are positive integers. In this case, as is clear from the above, the parasitic capacitances of the plurality of TFTs are also connected to GL 1. In this case, when the start terminal of GL1 receives a gate scan signal (Vg in magnitude), the TFTs in the m sub-pixels connected to GL1 and the TFTs in the n-m dummy sub-pixels 40 can be turned on during the gate scan signal transmission (e.g., from left to right), thereby turning on the liquid crystal capacitors C in the sub-pixels_LCAnd the parasitic capacitances in the dummy sub-pixel 40, in this case the gate scan signal at the end of GL1 has an amplitude Vg1, where Vg1 is slightly less than Vg.

Similarly, when the start terminal of GL2 in the main display area 12 receives a gate scan signal (with amplitude Vg), the TFTs in the n sub-pixels connected to GL2 can be turned on during the gate scan signal transmission process (e.g. from left to right), so as to couple the liquid crystal capacitors C in the sub-pixels_LCCharging is performed, in this case, the magnitude of the gate scan signal at the end of GL2 in the main display area 12 is Vg2, where Vg2 is slightly smaller than Vg.

In this case, although the number (m) of a row of subpixels controlled by GL1 is smaller than the number (n) of a row of subpixels controlled by one GL2 in the main display area 12, the parasitic capacitance of the TFT disposed in the dummy subpixel 40 can be increased by the dummy subpixel 40 disposed between the opening 10 and the effective display area of the display screen to increase the load of GL1, so that the voltage difference △ V between Vg1, which is the magnitude of the gate scan signal at the end of GL1, and Vg2, which is the magnitude of the gate scan signal at the end of GL2 in the main display area 12, is small.

EXAMPLE III

In this embodiment, the line width of the GL between the opening 10 and the effective display area of the display screen is greater than the line width of the GL in the effective display area. For example, the line width of G1 is greater than the line width of G2.

Based on this, the liquid crystal capacitance C formed by the pixel electrode 501 and the common electrode layer 500 of each sub-pixel in the main display area 12 can be calculated by software_LCAnd the total number n of sub-pixels of a row connected to a row GL2 in the main display area 12. In addition, a second capacitor C2 formed by the common electrode layer 500 and one GL2 in the main display area 12 can be obtained. The capacitance of the capacitor connected to one GL2 in the main display area 12 can thus be calculated, for example, to be n C_LC+C2。

Next, the total number m of subpixels controlled by GL1 is obtained, and all liquid crystal capacitances C connected to the row GL1 are calculated_LCIs, for example, m.times.C_LC. By comparing the size of all the liquid crystal capacitors connected to GL1 with the size of the capacitor connected to GL2 in the main display area 12, the difference between the two can be obtained, so as to obtain the compensation value needed to compensate the capacitor connected to GL 1.

In addition, as can be seen from the above, the auxiliary conductive layer 40 and the GL1 integrated with the common electrode layer 500 can form the first capacitor C1. Therefore, the line width of GL1 can be adjusted according to the obtained capacitance compensation value to increase the first capacitorThe capacitance of the capacitor C1, such that the capacitor GL1 is connected to, for example, m C_LCThe capacitance connected between the + C1 and one GL2 in the main display area 12 is, for example, n × C_LCThe + C2 are the same or approximately the same, and finally the purpose of capacitance compensation is achieved.

On this basis, as shown in fig. 13, in order for the GL1 between the opening 10 and the effective display area of the display screen to bypass the opening 10, the GL1 may include a first sub-portion 51 and a second sub-portion 52.

Wherein the first sub-portion 51 is parallel to GL2 in the main display area 12, and the second sub-portion 52 intersects the first sub-portion 51. Thus, the length of GL1 including the first sub-portion 51 and the second sub-portion 52 is longer than that of GL2 in the main display area 12, and thus the resistance of GL1 is larger. In addition, the area where the second sub-portion 52 is located has a small wiring space. In this case, in order to effectively utilize the wiring space and reduce the resistance of the GL1, the line width of the first sub-portion 51 is greater than the line width of the second sub-portion 52, and the line width of the second sub-portion 52 is greater than the line width of the GL2 in the main display area 12.

As can be seen from the above, the third embodiment is different from the second embodiment in that only the line width of GL1 between the opening 10 and the effective display area of the display screen needs to be adjusted, and the dummy sub-pixel 40 needs to be disposed. Therefore, the area of the region between the opening 10 and the effective display area of the display screen is smaller in the third embodiment, which can be beneficial to reducing the size of the frame of the display screen.

Example four

As shown in fig. 14, the auxiliary conductive layer 20 includes at least one row of sub-electrodes 201 which are arranged at intervals and electrically connected to each other. An orthographic projection of GL1 between opening 10 and the effective display area of the display screen on the substrate 01 of the array substrate 100 overlaps at least part of an orthographic projection of at least one row of sub-electrodes 201 on the substrate 01.

For example, in fig. 14, the orthographic projection of the first row of sub-electrodes 201 on the substrate 01 overlaps with the orthographic projections of the first and second rows GL1 on the substrate 01.

As can be seen from the above description, since the auxiliary conductive layer 20 integrally formed with the common electrode layer 500 is disposed in a different layer from the GL1 between the opening 10 and the effective display area of the display panel and is insulated, a first capacitor C1 can be formed between each sub-electrode 201 and the GL1 in the auxiliary conductive layer 20. At this time, the larger the area where the orthographic projection of the sub-electrode 201 on the substrate 01 and the orthographic projection of GL1 on the substrate 01 overlap, the larger the capacitance connected to the bar GL 1. Therefore, it is known that the compensation amount of the capacitance connected to GL1 can be obtained, and then the distribution density and shape of the row of sub-electrodes 201 for covering GL1 can be set according to the compensation amount.

When the number of sub-pixels in each row is the same in the sub-display region 11, as shown in fig. 14, the distribution density and shape of each row of sub-electrodes 201 may be the same. In addition, when the edge of the opening 10 is a hypotenuse as shown in fig. 15, the number of sub-pixels in a row may be different in the sub-display region 11 as shown in fig. 16.

In this case, when the compensation amount of the capacitance connected to GL1 is different, the distribution density and the shape of each row of sub-electrodes 201 may be different.

For example, in fig. 16, the number of sub-pixels connected to the first line GL1 is smaller than the number of sub-pixels connected to the second line GL 1. As can be seen from the above, the compensation value for the capacitance connected to the first line GL1 needs to be larger than the compensation value for the capacitance connected to the second line GL 1. Therefore, the sub-electrodes 201 in the same row can overlap with the first and second rows GL1 at the same time, and each sub-electrode 201 in the row of sub-electrodes 201 is in the shape of a trapezoid, the long side of the trapezoid is located above, and the short side of the trapezoid is located below, so that the overlapping part of the orthographic projection of the sub-electrode 201 on the substrate 01 and the orthographic projection of the first row GL1 on the substrate 01 has a larger area, and the overlapping part of the orthographic projection of the sub-electrode 201 on the substrate 01 and the orthographic projection of the second row GL1 on the substrate 01 has a smaller area, and finally, the capacitance connected by the two sub-electrodes GL1 is the same as or approximately the same as the capacitance connected by the GL2 in the main display area 12.

It should be noted that the solutions of the second embodiment, the third embodiment and the fourth embodiment provided in the embodiments of the present application may be combined with each other. For example, the schemes of the second embodiment and the third embodiment are combined, that is, while the dummy sub-pixel 40 is disposed between the opening 10 and the effective display area of the display screen, the line width of GL1 between the opening 10 and the effective display area of the display screen can be increased; alternatively, the solutions of the third and fourth embodiments are combined, that is, the line width of the GL1 between the opening and the effective display area of the display screen is increased, and at the same time, the auxiliary conductive layer 20 between the opening 10 and the effective display area of the display screen is provided with a plurality of sub-electrodes 201 covering the GL 1. Other combining methods are not described in detail herein.

The following describes a display driving process of the display panel having the array substrate 100 and a compensation effect of the capacitor connected to the GL 1.

As shown in fig. 17, a Gate Driver on Array (GOA) circuit including a plurality of shift Register units (RS) is disposed on the Array substrate 100 in the non-effective display region outside the sub display region 11 and the main display region 12, and each stage RS is connected to one line GL. The GOA circuits may be all disposed in the non-effective display area on the left side, or the area of the non-effective display area is gradually reduced to meet the design requirement of narrow frame, so as shown in fig. 17, the GOA may be divided into two parts, the odd RS is disposed in the non-effective display area on the left side, and the even RS is disposed in the non-effective display area on the right side.

The first-level RS1, the second-level RS2, the third-level RS3 and the fourth-level RS4 are respectively connected with the GL1 in the positions of the first row, the second row, the third row and the fourth row in the sub-display area 11; the fifth stage RS5, the sixth stage RS6, the seventh stage RS7, and the eighth stage RS8 are connected to the GL2 in the fifth, sixth, seventh, and eighth row positions in the main display area 12, respectively.

In addition, a driving Integrated Circuit (IC) connected to the GOA Circuit and a source driver (not shown) is further disposed in the non-display region. The source driver is connected to the data lines DL for supplying data voltages to the data lines.

In the process of displaying a frame of picture, the driving IC controls each RS in the GOA circuit to output a gate scanning signal to the gate line GL connected thereto step by step, so as to implement the line-by-line scanning of all the gate lines. When one of the gate lines receiving the gate scan signal, for example, GL1 in the first row position in the sub-display region 11 receives the gate scan signal, the TFT in the sub-pixel connected to the GL1 is turned on, and the capacitor connected to GL1 (for example, the capacitor formed by the common electrode layer 500 and GL1 in the scheme shown in fig. 11) formed between the opening 10 and the effective display region of the display screen is in a charged state.

At the same time, the driving IC controls the source driver to output a data voltage to each data line DL, and the data voltage is transferred to the pixel electrode 501 of the first row of subpixels through the turned-on TFT to charge the row of subpixels. In this case, the time for which all the sub-pixels from the leftmost end to the rightmost end of the first row are charged is extended by the capacitance connected to GL1 of the first row, for example, T.

Next, the second stage RS2 outputs the gate scan signal to GL1 located in the second row, and the charging process of the sub-pixels connected to GL1 in the second row is the same as described above, except that the sub-pixels in the second row are charged from the right end to the left end, and the time for which the sub-pixels in the second row are charged is the same as or approximately the same as T.

Next, the third and fourth stages RS3 and RS4 output gate scan signals to GL1 at the third row and GL1 at the fourth row line by line. The charging process of the third row sub-pixel and the fourth row sub-pixel is the same as that described above and will not be described herein again.

Next, the fifth stage RS5 outputs a gate scan signal to the GL2 located at the fifth row position in the main display area 12, and the sub-pixels arranged in the entire row connected to the GL2 are charged from left to right. The charging process is as described above. At this time, although the number of the first row sub-pixels in the sub-display region 11 is smaller than the number of the fifth row sub-pixels in the main display region 12, it can be seen from the above that a capacitor for compensating for the load of GL1 connected to the first row sub-pixels is provided between the opening 10 and the effective display region of the display screen, and thus the time for which the fifth row sub-pixels are charged is the same as or approximately the same as T.

The charging process of the sub-pixels in each of the remaining rows of the main display area 12 is the same as described above, and is not described herein again. As can be seen from the above, although the number of the sub-pixels in each row of the array substrate 100 is not completely the same under the influence of the opening 10, in the solution provided in the present application, a capacitor may be disposed between the opening 10 and the effective display area of the display screen to compensate for the load of the gate line GL connected to fewer sub-pixels, so that the charging of the sub-pixels in each row tends to be the same, and further, the deflection speeds of the liquid crystal molecules corresponding to different sub-pixels are the same, thereby reducing the probability of poor display such as flicker or horizontal stripes.

EXAMPLE five

In the above embodiments, the auxiliary conductive layer 20 and the common electrode layer 500 are disposed on the array substrate 100 as an example. The present application may further dispose the auxiliary conductive layer 20 on the opposing substrate 200, and an orthographic projection of the auxiliary conductive layer 20 on the substrate 01 of the substrate 100 is located between the opening 10 and the effective display area of the display screen. In this case, as shown in fig. 18, when the common electrode layer 500 is disposed on the opposing substrate 200, the auxiliary conductive layer 20 and the common electrode layer 500 may still be made of the same material in the same layer and have an integral structure, so as to achieve the purpose of disposing the auxiliary conductive layer 20 on the opposing substrate 200.

The common electrode layer 500 is located on a surface of the color filter layer formed by the plurality of filter units 210, the surface being close to the array substrate 100.

Based on this, the scheme of the second embodiment can still be adopted on the array substrate 100, and the dummy sub-pixel 40 and the TFT located in the dummy sub-pixel 40 are formed between the opening 10 and the effective display area of the display screen; alternatively, the array substrate 100 may further adopt the solution of the third embodiment, and at least a part of the line width of GL1 between the opening 10 and the effective display area of the display screen is increased; alternatively, the structure of the array substrate 100 may be unchanged, and the auxiliary conductive layer 20 on the counter substrate 100 is formed in the manner of the fourth embodiment, at least one row of sub-electrodes 201 which are spaced from each other and electrically connected is formed at a position corresponding to between the opening 10 and the effective display area of the display screen, and an orthographic projection of the sub-electrodes 201 on the substrate 01 of the array substrate 100 overlaps with an orthographic projection of at least one GL1 on the substrate 01.

In this case, the process of compensating the capacitance connected to GL1 by the display screen is the same as described above, and is not described herein again.

The display panel shown in fig. 18 is a Twisted Nematic (TN) display panel. The TN display panel uses the principle of vertical electric field, and drives the liquid crystal molecules in the twisted nematic mode by forming a vertical electric field between the common electrode layer 500 oppositely disposed on the opposite-cell substrate 200 and the pixel electrode 501 oppositely disposed on the array substrate 100, thereby achieving the purpose of display.

The above embodiments are all described by taking a TFT-LCD as an example, and the capacitance compensation scheme provided in the embodiments of the present application can be applied to an Organic Light Emitting Diode (OLED) display screen as well.

Specifically, the OLED display panel includes an array substrate 100 as shown in fig. 19, sub-pixels arranged in an array are formed on the array substrate 100, and as shown in fig. 20, an OLED and a pixel circuit connected to the OLED are disposed in each sub-pixel.

The present application does not limit the specific structure of the pixel circuit, and the pixel circuit shown in fig. 20 is only exemplified by the simplest structure of the pixel circuit, and the pixel circuit includes a gate transistor Tc, a driving transistor Td and a capacitor C. In fig. 20, the cathode of the OLED is connected to the ground terminal GND, and when the driving transistor Td is turned on, a voltage difference is formed between the voltage terminal VDD and the ground terminal GND, so that the driving current flows through the OLED, and the OLED emits light. Of course, in order to realize compensation of the threshold voltage Vth of the driving transistor Td, the pixel circuit may further include a compensation unit; alternatively, the pixel circuit may further include a reset unit in order to reset the anode of the OLED or the gate of the driving transistor Td. The compensation unit and the reset unit are composed of a plurality of transistors, and detailed structures of the compensation unit and the reset unit are not repeated in the application.

Based on this, the longitudinal cross-sectional structure of the OLED display panel is shown in fig. 21, and it can be seen that the OLEDs are arranged in an array on the array substrate 100. The OLED comprises an upper electrode 60 (e.g. a cathode), a lower electrode 61 (e.g. an anode) and a functional layer 62 of organic material between the upper electrode 60 and the lower electrode 61. The lower electrode 60 and the organic material functional layer 62 are located in a recess provided in the pixel defining layer 63.

The bottom electrode 61 is connected to a TFT in a sub-pixel, such as the driving transistor Td. The organic material functional layer 62 may include a hole injection layer, a hole transport layer, an organic light emitting layer, an electron transport layer, an electron injection layer, and the like.

Further, as shown in fig. 19 and 21, the upper electrode 60 may be a whole layer, and the upper electrode 60 covers the effective display area having the sub display area 11 and the main display area 12. In this case, the auxiliary conductive layer 20 is disposed between the effective display area and the opening 10 on the array substrate 100, and an orthogonal projection of at least one GL1 between the opening 10 and the effective display area of the display screen on the substrate 01 of the array substrate 100 overlaps with a part of an orthogonal projection of the auxiliary conductive layer 20 on the substrate 01. Accordingly, in order to simplify the manufacturing process, the auxiliary conductive layer 20 may be formed in the same layer as the upper electrode 60 and be an integral structure.

In this case, similarly to the arrangement of the TFTs on the array substrate in the liquid crystal display panel, at least the first insulating layer 301 on the upper surface of the GL1 is provided between the upper electrode 60 and the GL 1. Therefore, at least the first insulating layer 301 is also provided between the auxiliary conductive layer 20 and the GL1 in the same layer as the upper electrode 60. In addition, as shown in fig. 21, since the upper electrode 60 is formed on the upper surface of the pixel defining layer 63, the pixel defining layer 63 located above the first insulating layer 301 may be further included between the auxiliary conductive layer 20 and the GL1 which are in the same layer as the upper electrode 60, and the auxiliary conductive layer 20 is formed on the upper surface of the pixel defining layer 63.

Thus, the auxiliary conductive layer 20 can form a capacitance with the GL1 between the opening 10 and the effective display area of the display screen, thereby increasing the load of the GL 1.

In addition, the scheme of the second embodiment can still be adopted on the array substrate 100 in the OLED display screen, and the dummy sub-pixel 40 and the TFT located in the dummy sub-pixel 40 are formed between the opening 10 and the effective display area of the display screen; alternatively, the array substrate 100 may also adopt the solution of the third embodiment, and at least a part of the line width of GL1 between the opening 10 and the effective display area of the display screen is increased; alternatively, the structure of the array substrate 100 may not be changed, and the auxiliary conductive layer 20 that is in the same layer as the upper electrode 60 and has an integral structure is formed by the fourth embodiment, so that at least one row of sub-electrodes 201 that are spaced from each other and electrically connected is formed between the opening 10 and the effective display area of the display screen.

In this case, the process of compensating the capacitance connected to GL1 by the OLED display is the same as described above, and will not be described herein again.

On this basis, as shown in fig. 21, the OLED display further includes an encapsulation substrate 400. The encapsulation substrate 400 is used for encapsulating an array substrate of an OLED display panel.

The application provides a terminal equipment, including above-mentioned arbitrary display screen, the structure and the technological effect of this display screen are the same as above, and this is no longer repeated here. The terminal equipment can be mobile phones, flat panels, televisions and other equipment with display screens.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

A display screen is characterized in that the display screen is provided with an opening, the display screen comprises an array substrate and a box aligning substrate which are oppositely arranged, and a liquid crystal layer is arranged between the array substrate and the box aligning substrate;

the array substrate comprises a first insulating layer and a common electrode layer; the common electrode layer is positioned above the first insulating layer; a grid line is arranged on the lower surface of the first insulating layer between the opening and the effective display area of the display screen; an auxiliary conducting layer is arranged above the first insulating layer between the opening and the effective display area of the display screen; the auxiliary conducting layer and the common electrode layer are on the same layer.
The display screen of claim 1, wherein the auxiliary conductive layer is of unitary construction with the common electrode layer.
A display screen according to claim 1 or 2, wherein the first insulating layer is a gate insulating layer;

the array substrate further comprises a data line in contact with the upper surface of the gate insulating layer, a second insulating layer covering the upper surface of the data line, a pixel electrode positioned on the upper surface of the second insulating layer, and a third insulating layer positioned on the upper surface of the pixel electrode; the auxiliary conductive layer is located on the upper surface of the third insulating layer.
The display screen of claim 2, wherein the array substrate further comprises a gate insulating layer; the grid line is positioned on the upper surface of the grid insulation layer;

the array substrate further comprises a pixel electrode positioned on the upper surface of the first insulating layer, and a third insulating layer positioned on the upper surface of the pixel electrode; the auxiliary conducting layer is positioned on the upper surface of the third insulating layer;

or, the array substrate further comprises a data line in contact with the upper surface of the first insulating layer, a second insulating layer covering the data line, a pixel electrode on the upper surface of the second insulating layer, and a third insulating layer on the upper surface of the pixel electrode; the auxiliary conductive layer is located on the upper surface of the third insulating layer.
A display screen according to any one of claims 1 to 4, wherein the line width of the grid lines between the opening and the active display area of the display screen is greater than the line width of the grid lines of the active display area.
The display panel according to any one of claims 1 to 4, wherein a data line crossing the gate line is provided over the first insulating layer between the opening and an active display region of the display panel;

two adjacent data lines and two adjacent grid lines intersect to define a dummy sub-pixel; a thin film transistor is also arranged in the dummy sub-pixel; the grid electrode of the thin film transistor is connected with the grid line, the first electrode of the thin film transistor is connected with the data line, and the second electrode of the thin film transistor is vacant.
A display screen according to any one of claims 1-4, wherein the auxiliary conductive layer comprises at least one row of sub-electrodes arranged at intervals and electrically connected with each other;

the orthographic projection of the grid line between the opening and the effective display area of the display screen on the substrate of the array substrate is overlapped with at least part of the orthographic projection of at least one row of the sub-electrodes on the substrate.
A display screen according to any one of claims 1 to 7, wherein an orthographic projection of the gate line between the opening and the active display area of the display screen on the substrate of the array substrate overlaps at least part of an orthographic projection of the auxiliary conductive layer on the substrate.
A display screen according to any one of claims 1 to 7, wherein the opening is a recess provided in at least one side of the display screen and recessed inwardly of the display screen.
The terminal equipment is characterized by comprising a display screen, wherein the display screen is provided with an opening and comprises an array substrate and a box aligning substrate which are oppositely arranged, and a liquid crystal layer is arranged between the array substrate and the box aligning substrate;

the array substrate comprises a first insulating layer and a common electrode layer; the common electrode layer is positioned above the first insulating layer; a grid line is arranged on the lower surface of the first insulating layer between the opening and the effective display area of the display screen; an auxiliary conducting layer is arranged above the first insulating layer between the opening and the effective display area of the display screen; the auxiliary conducting layer and the common electrode layer are on the same layer.
A terminal device according to claim 10, characterized in that the auxiliary conductive layer is of one-piece construction with the common electrode layer.
The terminal device of claim 11, wherein the first insulating layer is a gate insulating layer;

the array substrate further comprises a data line in contact with the upper surface of the gate insulating layer, a second insulating layer covering the upper surface of the data line, a pixel electrode positioned on the upper surface of the second insulating layer, and a third insulating layer positioned on the upper surface of the pixel electrode; the auxiliary conductive layer is located on the upper surface of the third insulating layer.
The terminal device of claim 11, wherein the array substrate further comprises a gate insulating layer; the grid line is positioned on the upper surface of the grid insulation layer;

the array substrate further comprises a pixel electrode positioned on the upper surface of the first insulating layer, and a third insulating layer positioned on the upper surface of the pixel electrode; the auxiliary conducting layer is positioned on the upper surface of the third insulating layer;

or, the array substrate further comprises a data line in contact with the upper surface of the first insulating layer, a second insulating layer covering the data line, a pixel electrode on the upper surface of the second insulating layer, and a third insulating layer on the upper surface of the pixel electrode; the auxiliary conductive layer is located on the upper surface of the third insulating layer.
A terminal device according to any of claims 10-13, wherein the line width of the gate lines between the opening and the active display area of the display screen is larger than the line width of the gate lines of the active display area.
A terminal device according to any of claims 10-13, wherein a data line crossing the gate line is provided over the first insulating layer between the opening and an active display area of the display screen;

two adjacent data lines and two adjacent grid lines intersect to define a dummy sub-pixel; a thin film transistor is also arranged in the dummy sub-pixel; the grid electrode of the thin film transistor is connected with the grid line, the first electrode of the thin film transistor is connected with the data line, and the second electrode of the thin film transistor is vacant.
A terminal device according to any one of claims 10-13, wherein the auxiliary conductive layer comprises at least one row of sub-electrodes arranged at intervals and electrically connected to each other;

the orthographic projection of the grid line between the opening and the effective display area of the display screen on the substrate of the array substrate is overlapped with at least part of the orthographic projection of at least one row of the sub-electrodes on the substrate.
The terminal device according to any one of claims 10 to 16, wherein an orthogonal projection of the gate line between the opening and the active display area of the display screen on the substrate of the array substrate overlaps at least a portion of an orthogonal projection of the auxiliary conductive layer on the substrate.
The terminal device according to any one of claims 10 to 16, wherein the opening is a groove provided on at least one side of the display screen and recessed toward the inside of the display screen.