KR101432007B1 - Apparatus and method for inspecting duly reach of semiconductor - Google Patents

Apparatus and method for inspecting duly reach of semiconductor Download PDF

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Publication number
KR101432007B1
KR101432007B1 KR1020140007032A KR20140007032A KR101432007B1 KR 101432007 B1 KR101432007 B1 KR 101432007B1 KR 1020140007032 A KR1020140007032 A KR 1020140007032A KR 20140007032 A KR20140007032 A KR 20140007032A KR 101432007 B1 KR101432007 B1 KR 101432007B1
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KR
South Korea
Prior art keywords
semiconductor
marker
image
test socket
camera
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KR1020140007032A
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Korean (ko)
Inventor
유광룡
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유광룡
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B11/00—Measuring arrangements characterised by the use of optical techniques
    • G01B11/02—Measuring arrangements characterised by the use of optical techniques for measuring length, width or thickness
    • G01B11/022—Measuring arrangements characterised by the use of optical techniques for measuring length, width or thickness by means of tv-camera scanning
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B11/00—Measuring arrangements characterised by the use of optical techniques
    • G01B11/26—Measuring arrangements characterised by the use of optical techniques for measuring angles or tapers; for testing the alignment of axes
    • G01B11/27—Measuring arrangements characterised by the use of optical techniques for measuring angles or tapers; for testing the alignment of axes for testing the alignment of axes
    • G01B11/272—Measuring arrangements characterised by the use of optical techniques for measuring angles or tapers; for testing the alignment of axes for testing the alignment of axes using photoelectric detection means
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2642—Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means

Abstract

The present invention relates to a test socket in which a semiconductor is seated and a marker whose area varies at a predetermined angle according to a seating position of the semiconductor is displayed; An image acquiring unit for photographing the marker when the semiconductor is mounted on the test socket; And a controller for comparing the reference image with the image taken by the camera to determine whether the semiconductor is seated at the designated position.

Description

TECHNICAL FIELD [0001] The present invention relates to an apparatus for inspecting a semiconductor,

The present invention relates to an apparatus and a method for inspecting whether or not a semiconductor is seated correctly at a specified position of a test socket, and more particularly, The present invention relates to an apparatus and method for checking whether a semiconductor is seated according to a matching rate of a camera image with a reference image.

Generally, a wafer on which a predetermined integrated circuit is formed is separated into semiconductor chips, and is completed with a semiconductor package (hereinafter referred to as a semiconductor) through an assembling process. Completed semiconductors are classified into normal products and defective products through various tests, and the reliability of the products is maintained through this process. In such a test process, the initial defect inspection of a semiconductor is called a burn-in test.

The burn-in test is performed in a state where the semiconductor is thermally stressed at a high temperature of about 80 to 125 ° C, and the semiconductor operates at a high temperature and a high electric field. During the burn-in test, defective semiconductors that do not have a long life span can not withstand the test conditions and cause defects. Normal semiconductors that pass the burn-in test can be guaranteed a long life span, have.

Such a burn-in test generally involves transferring a semiconductor to a test socket using a picker such as a robot arm or a vacuum adsorbing device, and proceeding with the semiconductor mounted on the test socket. Upon completion of the seating of the semiconductor, an inspection signal transmitted from the tester is transmitted to the test substrate, and the socket lead electrically connected to the test substrate is transferred to the lead of the semiconductor to perform the electrical characteristic inspection.

However, if the semiconductor is not properly seated in the test socket due to foreign substances in the test socket, inaccuracies of the robot arm, or insufficient suction force in the vacuum adsorption device, the semiconductor lead and the socket lead are not properly connected, There was a problem that the electric characteristic test was not properly performed.

Therefore, a need has arisen to overcome the above-mentioned problems and to check whether the semiconductor is correctly seated in a specified position of the test socket.

Korean Patent No. 10-1076741 (published on Sep. 14, 2011), "Semiconductor Device Vision Inspection System and Method of Test Handler" Korean Patent Publication No. 2009-0128707 (published Dec. 16, 2009), "Vision Inspection Apparatus for Semiconductor Package Manufacturing Apparatus" Korean Patent No. 10-1314592 (published on Mar. 31, 2013), "Vision Inspection Apparatus with Improved Inspection Speed"

The present invention provides an inspection apparatus and method that can accurately determine whether a semiconductor is seated in a test socket using an image photographed by a camera.

The present invention provides an inspection apparatus and method for detecting a semiconductor even if it is seated slightly off the designated position of the test socket.

The present invention provides an inspection apparatus and a method for inspecting whether a semiconductor is seated at a time for a plurality of test sockets.

 The semiconductor mount inspection apparatus of the present invention includes a test socket on which a semiconductor is mounted and on which a marker whose area is recognized at a predetermined angle according to a seating position of the semiconductor is displayed; An image acquiring unit for acquiring an image including the marker when the semiconductor is mounted on the test socket; And a control unit for comparing the degree of exposure of the marker in the reference image with the degree of exposure of the marker in the image acquired by the image acquiring unit to determine whether the semiconductor is seated at the designated position.

The test socket may further include: a lower body having a seating portion on which a semiconductor can be seated; An upper body slidably coupled to a guide bar of the lower body and having an opening through which a semiconductor can be inserted; A marker exposure adjusting part whose one end is selectively engaged with the semiconductor mounted on the lower body and whose degree of covering the marker varies depending on the seating position of the semiconductor; And a socket lead provided on the lower body and electrically connected to the lead of the semiconductor.

The marker exposure control unit may be rotatably coupled to the lower body, and the other end may be engaged with the upper body to rotate.

When the upper body is moved toward the lower body, the marker exposure control unit rotates to the outside of the test socket, so that the semiconductor pressing unit moves to the lower body, When the upper body is moved away from the lower body, the marker exposure control part is rotated to the inside of the test socket so that the semiconductor pressing part can move to the inside of the test socket.

The image obtaining unit may further include: at least one camera for collecting at least one image of a semiconductor array including at least one semiconductor; A lens provided in each of the at least one or more cameras to adjust a focal distance; And an illumination unit for illuminating the marker of the at least one test socket on which the at least one semiconductor is mounted so that the camera recognizes the marker.

In addition, the controller may determine whether the semiconductor is normally seated by comparing the degree of exposure of the marker in the reference image with the degree of exposure of the marker in the image captured in the image acquiring unit.

The controller may further include a camera setting unit for setting connection state information for the at least one camera and camera parameter information for identification information, initialization state, exposure time, and brightness of the at least one camera; An image preprocessing unit for combining the one or more images collected from the at least one camera to generate a merge image; An area setting unit for setting a reference pattern area for the generated merge image and a search area for searching the reference pattern area; A measurement setting unit configured to set a measurement area array for the generated merge image in consideration of the number and spacing of at least one or more semiconductors of the semiconductor array; And a determination unit for determining whether a normal landing has occurred by comparing the degree of exposure of the marker based on the reference image and a reference pattern area in the measurement area array.

The control unit may further include a reference image registration unit for setting a pattern area for determining whether a normal seating is established, and registering the set pattern area as the reference image.

In the case where the semiconductor is poorly adhered to the lower body, the semiconductor pushes the semiconductor pressing portion, and the marker exposure adjusting portion is rotated to the outside of the test socket, and the marker exposure adjusting portion may cover a part of the marker.

In addition, if the control unit determines that the semiconductor is in the test socket, the operation of the picker for transferring the semiconductor can be stopped.

In addition, the semiconductor placement inspection method of the present invention includes the steps of: pressing a semiconductor mounted on the test socket while the marker exposure control portion of the test socket is rotated; Collecting an image including a marker displayed on the test socket through a camera; Comparing the collected image with a reference image through a control unit and determining whether the semiconductor is normally seated in the test socket according to the degree of matching between the camera image and the reference image according to whether the marker is exposed or not; Wherein the control unit controls the semiconductor to perform an inspection if the semiconductor is determined to be a normal seating on the test socket and controls the picker to be a normal seating for the semiconductor when the semiconductor is determined to be a defective seating Step

The test socket may include a test socket for displaying a marker whose area is recognized according to a seating position of the semiconductor, an image acquiring unit for acquiring an image including the marker when the semiconductor is mounted on the test socket, The inspection method for a semiconductor placement inspection apparatus according to the present invention includes a control unit for comparing the degree of exposure of the marker in the image acquired by the image acquisition unit and determining whether the semiconductor is normally seated, Setting camera parameter information on identification status, initialization status, exposure time, and brightness of the at least one camera; Generating a merged image by combining one or more images collected from the at least one camera through a control unit; Setting a reference pattern region and a search region for searching the reference pattern region with respect to the generated merge image through a control unit; Setting a measurement area array for the generated merge image taking into account the number and spacing of at least one semiconductor of the semiconductor array through the control part; And comparing the exposure level of the marker based on the reference image and the reference pattern area in the measurement area array to determine whether or not a normal landing has occurred.

According to the present invention, even if the semiconductor is seated slightly off the designated position of the test socket, it can be sensed so that the accuracy and precision of inspection can be improved.

According to the present invention, it is possible to filter out the case where the semiconductor is misplaced in the test socket, so that the semiconductor can be accurately inspected and the reliability can be improved.

According to the present invention, it is possible to inspect whether a semiconductor is seated at a time for a plurality of test sockets, thereby speeding up the inspection.

1 is a perspective view of a test socket included in a semiconductor placement inspection apparatus according to the present invention.
2 is a cross-sectional view taken along line AA of FIG.
3 is a perspective view of an image acquiring unit of the semiconductor placement inspection apparatus according to the present invention.
4 is a side view of the image acquisition unit of the semiconductor placement inspection apparatus according to the present invention.
5 is a block diagram showing the components of a semiconductor inspection apparatus for measuring whether or not a semiconductor is normally seated according to the present invention.
6 is a side schematic view of the case where the semiconductor is normally seated in the test socket;
7 is a schematic plan view of the semiconductor device when the semiconductor device is normally placed on the test socket;
Fig. 8 is a schematic view of the test socket viewed from the side in the case where the semiconductor is poorly mounted.
9 is a schematic plan view of the test socket in the case where the semiconductor is poorly mounted.
10 is a flowchart showing a semiconductor placement inspection method according to the present invention.
11 is a flowchart showing a semiconductor placement inspection method through the semiconductor placement inspection apparatus of the present invention.
12 illustrates setting of a reference pattern region and a search region through the semiconductor placement inspection apparatus of the present invention.
Figs. 13 and 14 illustrate the setting of the measurement array through the semiconductor placement inspection apparatus of the present invention.
FIG. 15 illustrates determination of whether or not a normal seating is performed through the semiconductor placement inspection apparatus of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and accompanying drawings, but the present invention is not limited to or limited by the embodiments.

As used herein, the terms "embodiment," "example," "side," "example," and the like should be construed as advantageous or advantageous over any other aspect or design It does not.

Also, the term 'or' implies an inclusive or 'inclusive' rather than an exclusive or 'exclusive'. That is, unless expressly stated otherwise or clear from the context, the expression 'x uses a or b' means any of the natural inclusive permutations.

Also, the phrase "a" or "an ", as used in the specification and claims, unless the context clearly dictates otherwise, or to the singular form, .

It should also be understood that the term "and / or" as used herein refers to and includes all possible combinations of one or more of the listed related items.

Also, the term " comprises "and / or" comprising " means that there is a corresponding feature, step, operation, module, component, and / Components and / or groups of elements, components, components, and / or groups thereof.

In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The terminology used herein is a term used for appropriately expressing an embodiment of the present invention, which may vary depending on the user, the intent of the operator, or the practice of the field to which the present invention belongs. Therefore, the definitions of these terms should be based on the contents throughout this specification.

FIG. 1 is a perspective view of a test socket included in a semiconductor placement inspection apparatus according to the present invention, FIG. 2 is a cross-sectional view cut along the line AA in FIG. 1, And FIG. 4 is a side view of the image acquisition unit of the semiconductor placement inspection apparatus according to the present invention.

Referring to FIGS. 1 to 4, a semiconductor placement inspection apparatus according to an embodiment of the present invention includes a test socket 10, an image acquisition unit 20, and a control unit 30 (see FIG. 5).

The test socket 10 can be mounted with a semiconductor, and a test is made on the electrical characteristics of the semiconductor by supplying electricity to the semiconductor mounted on the test socket 10. The test socket 10 can be installed on the upper surface of a test substrate (not shown) electrically connected to a tester (not shown). When a semiconductor is mounted on the test socket 10, The electrical characteristics of the semiconductor mounted on the semiconductor chip 10 can be inspected.

The test socket 10 may include a lower body 12 and an upper body 11.

The lower body 12 may be mounted and fixed on the test substrate and a seating portion 121 (see Fig. 6) to which the semiconductor can be seated can be formed. The lower body 12 may be formed in a substantially rectangular parallelepiped shape and may be formed of PEI (polyetherimide), PES (), or the like.

The upper end of the lower body 12 is connected to the lead of the semiconductor when the semiconductor is seated and the lower end of the socket lead 13 is electrically connected to the circuit patterns of the test board provided at the lower portion of the lower body 12. [ .

The socket lead 13 includes an electrical connecting portion 131 protruding downward from the bottom surface of the lower body 12, a fixing portion 132 inserted into the lower body 12, a lead connecting portion 133 connected to the semiconductor lead, . ≪ / RTI > The socket lead 13 may be formed of an electrically conductive material, for example, made of Au-plated BeCu material.

The electrical connection part 131 protrudes downward from the lower body 12 and can be inserted into the upper surface of the test substrate and electrically connected to the circuit patterns of the test substrate.

The fixing portion 132 is inserted into the lower body 12 to prevent the socket lead 13 from being separated.

The lead connecting portion 133 may protrude upward from the fixing portion 132 and may be connected to the lead of the semiconductor when the semiconductor is mounted on the seating portion 121 so that the upper end thereof is positioned at the seating portion 121. The lead connecting portion 133 may be curved and bent to have elasticity. When the semiconductor is seated on the seating portion 121, the lead connecting portion 133 is bent downward. When the semiconductor is removed, the lead connecting portion 133 is restored to its original shape by elasticity .

The electrical connecting portion 131, the fixing portion 132, and the lead connecting portion 133 may be integrally formed, and may be formed as a single part forming one body.

The upper body 11 is spaced upward from the lower body 12 by a predetermined distance, and an opening 111 through which a semiconductor can be inserted may be formed on the upper surface. The opening 111 is formed at a position corresponding to the seating portion 121 of the lower body 12 so that the semiconductor inserted through the opening 111 can be seated on the seating portion 121.

The upper body 11 is connected to the lower body 12 by a guide bar 19 and the upper body 11 can move up and down along the guide bar 19. [ The guide bar 19 may be formed in a columnar shape, fixed to each corner of the lower body 12, and extend vertically upward from the lower body 12. The guide bar 19 can penetrate each corner of the upper body 11.

The semiconductor can be transported to the upper portion of the test socket 10 by a picker (not shown), and the picker can press the upper surface of the upper body 11 when the picker that adsorbed the semiconductor is lowered. The upper body 11 is pressed downward and guided by the guide bar 19 and can be moved downward. When the upper body 11 moves downward by a predetermined distance, the semiconductor adsorbed on the picker may fall on the seating portion 121 of the lower body 12. [

Between the upper body 11 and the lower body 12, an elastic member 17 may be provided. For example, the elastic member 17 may be a coil spring. The elastic member 17 can be compressed when the upper body 11 is pressed by the picker and can be stretched to its original length again when the picker is detached from the upper body 11. [

The picker moves upward and the upper body 11 moves upward due to the restoring force of the elastic member 17 and can return to the original position.

On the other hand, a marker M (see FIG. 6) that can be recognized by the image obtaining unit 20 is displayed on the test socket 10. The marker M may be displayed on the upper body 11 and may be formed into a predetermined shape having predetermined colors. For example, the marker M may be displayed in a rectangular shape of red color.

The lower body 11 is provided with a marker exposure control unit 15 for covering at least a part of the marker M and controlling the extent to which the marker M is exposed to the outside. The marker exposure control unit 15 may be rotatably coupled to the lower body 12. The marker exposure control unit 15 may be rotated around a rotation axis 16 provided on the lower body 12. [

The marker exposure control unit 15 can be selectively rotated in contact with the semiconductor with the inner side mounted on the lower body 11 and rotated with the outer side engaged with the upper body 11. The marker M may be displayed near the outer side of the marker exposure control unit 15 and may be selectively covered by the outer edge of the marker exposure control unit 15. [

Since the inside of the marker exposure control unit 15 moves selectively in contact with the semiconductor, the area recognized by the outside of the marker M may be changed according to the seating position of the semiconductor. In other words, the area recognized by the predetermined angle according to the seating position of the semiconductor can be changed in the marker M. A detailed description thereof will be described later.

The semiconductor marker 151 may be provided on the inner side of the marker exposure control unit 15 to press the semiconductor when the semiconductor is seated on the seating unit 121. The semiconductor pressing portion 151 may be formed in a shape protruding inward from the marker exposure control portion 15.

2, the left side shows a state when the picker presses the upper body 11, and on the right side with respect to the center line, the picker drops the semiconductor to the seating part 121 and moves to the upper part, (See Fig. 1).

2, when the picker pushes down the upper body 11, the marker exposure control unit 15 rotates counterclockwise, that is, to the outside of the upper body 11, 151 may move outwardly of the lower body 12 to open a passage through which the semiconductor can be seated in the seating part 121. When the picker presses the upper body 11 downward, the marker exposure control unit 15 is laid long in the horizontal direction and the outer edge of the marker exposure control unit 15 moves to the outside of the upper body 11 as much as possible .

2, when the picker lowers the semiconductor on the seating part 121 and then separates from the upper body 11 and moves upward, the restoring force of the elastic member 17 causes the upper body 11 The marker exposing unit 15 rotates counterclockwise, that is, the inside of the upper body 11, so that the semiconductor pressing unit 151 presses the upper portion of the semiconductor. Thus, the semiconductor can be fixed to the seating portion 121, and the semiconductor lead can be stably connected to the lead connecting portion 133 of the socket lead 13. [

On the other hand, the image obtaining unit 20 can take a role of capturing an image by taking a test socket 10. More specifically, the image acquiring unit 20 can photograph the marker M among the test sockets 10.

The image obtaining unit 20 includes a camera 21 for photographing the test socket 10, a lens 22 coupled to the camera 21 for adjusting the focal length, an illumination unit 27).

The image acquiring section 20 may also be provided with a mounting plate 25 which can be installed in a test box (not shown) in which the semiconductor is accurately mounted on the test socket 10, .

The mounting plate 25 may be formed in a wide plate shape and a camera support portion 23 for supporting the camera 21 may be coupled to the mounting plate 25. Referring to FIG. 4, the camera support portion 23 is formed in a letter shape so that the camera 21 can be separated from the installation plate 25 by a predetermined distance.

The mounting plate 25 or the camera supporting portion 23 may be provided with a lens supporting portion 24 for supporting the lens 22. [ The lens support portion 24 may be formed in a plate shape and extend substantially perpendicular to the mounting plate 25 to support the lower portion of the lens 22 to prevent the lens 22 from falling downward.

An illumination housing 28 having an illumination portion 27 on the inner circumferential surface thereof may be coupled to the lower portion of the mounting plate 25. The illumination housing 28 can be coupled to the lower portion of the mounting plate 25 by the illumination housing connection 26. The illumination housing 28 may be formed in a rectangular parallelepiped shape having open top and bottom surfaces and may be provided so that the illumination portions 27 face each other. Therefore, the light generated in the illumination unit 27 can be irradiated upward and downward. The illumination unit 27 can irradiate the marker M of the test socket 10 with light so that the marker M can be recognized more easily by the camera 21. [

The test socket 10 may be coupled to the lower portion of the illumination housing 28.

The control unit 30 compares the degree of exposure of the marker in the reference image with the degree of exposure of the marker in the image acquired in the image obtaining unit 20 to determine whether the semiconductor is seated at the specified position. Hereinafter, with reference to FIG. 5, a process for determining whether or not the semiconductor inspection apparatus according to the present invention is normally seated will be described in more detail.

5 is a block diagram showing the components of a semiconductor inspection apparatus for measuring whether or not a semiconductor is normally seated according to the present invention.

Referring to FIG. 5, the semiconductor inspection apparatus of the present invention includes a test socket 10, an image acquisition unit 20, and a control unit 30.

The test socket 10 displays a marker on which the semiconductor is seated and whose area is recognized at a predetermined angle according to the seating position of the semiconductor, and when the semiconductor is placed on the test socket 10, ≪ / RTI > The description of the test socket 10 and the image acquiring unit 20 has been described in detail with reference to FIGS. 1 to 4, and thus a detailed description thereof will be omitted.

The control unit 30 compares the degree of exposure of the marker in the reference image with the degree of exposure of the marker in the image acquired by the image obtaining unit 20 to determine whether the semiconductor is seated at the specified position

The image acquiring unit 20 may acquire an image by photographing the marker M of the test socket 10 and transmit the acquired image to the control unit 30. [ The control unit 30 stores a reference image of the shape and arrangement of the marker M when the semiconductor is accurately seated in the seating portion 121 of the test socket 10, And comparing the photographed image with the reference image, it is possible to check whether the semiconductor is normally seated according to the matching rate.

The control unit 30 may suspend the operation of the picker by transmitting a control signal to the picker when it is determined that the image transmitted from the image obtaining unit 20 deviates much from the reference image. Then, a semiconductor device which is misaligned to the test socket 10 can be properly mounted on the mount part 121 again, and then the operation signal can be transmitted so that the picker can operate normally.

The control unit 30 may include a camera setting unit 31, an image preprocessing unit 32, an area setting unit 33, a measurement setting unit 34, and a determination unit 35.

The camera setting unit 31 may set connection state information and camera parameter information for at least one or more cameras.

The connection status information may include network connection information (e.g., IP address) for at least one camera, and the identification information of at least one camera may include information for identifying at least one camera .

For example, the identification information of at least one camera is a Gigabit Ethernet (GigE) camera. An IP address, and a serial number of the camera itself. In case of a link camera, the information may include connector information of an associated grabber board or a grabber board. , A camera interface (Analog, IEEE1394, USB, GigE, Camera Link).

In addition, the camera parameter information may include identification information of at least one camera, initialization status, exposure time, and brightness.

The image preprocessing unit 32 may combine at least one image collected from at least one camera to generate a merge image. More specifically, the image preprocessing unit 32 may combine one or more images collected from at least one camera based on merging parameter information including overlap information, offset information, rotation information, scale information, and pivot information .

The overlap information includes size information of an overlapping area between adjacent cameras of at least one camera, and the offset information may include information on offset movement in a specific axial direction of the camera image.

In addition, the rotation information includes rotation information of a camera image, and the scale information includes information on the enlargement and reduction of the camera image in the horizontal and vertical directions. The pivot information may include coordinate information about a reference point (rotation center) at the time of rotation, enlargement, and reduction of the camera image.

The region setting unit 33 performs setting for detecting an offset in which at least one semiconductor is located for inspection of each of at least one or more semiconductors that are seated in the test socket.

For this, the area setting unit 33 may set a reference pattern area for the generated merge image and a search area for searching the reference pattern area. Hereinafter, the process of setting the reference pattern area and the search area through the area setting unit 33 will be described in detail with reference to FIG.

12 illustrates setting of a reference pattern region and a search region through the semiconductor placement inspection apparatus of the present invention.

The control unit 30 of the present invention may provide a user interface to the user to control the process of the semiconductor placement inspection apparatus through the display device.

The area setting unit 33 may perform setting information for detecting the offsets of the horizontal axis (X axis) and the vertical axis (Y axis) for each trigger.

12, the area setting unit 33 includes a search area B which is shifted by a range of positional change per step and a reference area B which is a reference for positional shift for each trigger in the search area B, The area C can be set.

The search area (B) and the reference pattern area (C) may be input from an examiner (user) or automatically designated as a specific area. In addition, as shown in Fig. 12D, the area setting unit 33 can set a parameter (fScore_std) for searching a reference pattern area.

Referring again to FIG. 5, the measurement setting unit 34 may set a measurement area array for the merged image generated considering the number and spacing of at least one semiconductor of the semiconductor array. More specifically, the measurement setting unit 34 sets the inspection object in consideration of the arrangement and position of the horizontal and vertical axes of the semiconductor array in the merged image. This will be described in more detail with reference to FIGS. 13 and 14. FIG.

Figs. 13 and 14 illustrate the setting of the measurement array through the semiconductor placement inspection apparatus of the present invention.

The control unit 30 of the present invention may provide a user interface to the user to control the process of the semiconductor placement inspection apparatus through the display device.

13, the user (inspector) sets LeftTop (A) as an area on the semiconductor located at the upper left side and left side in the semiconductor array through the measurement setting unit 34, edits the parameter B, (Set, C) based on the information (B) and can separately store the set information (E).

The measurement setting unit 34 sets the number of semiconductors (mArray_Num_X) arranged in the X-axis direction in the image, the number of semiconductors (mArray_Num_Y) arranged in the Y-axis direction, the interval between measurement objects in the X- nGap_X), the interval (nGap_Y) between the measurement objects in the Y-axis direction in the image, whether or not the align function is used (bROIUse_Offset), the area width setting (fSearchScale_W) The measurement array can be set based on the parameter information B including the area height setting (fSearchScale_H) to be searched.

The measurement array can be generated through the measurement setting unit 34 based on the edited parameters as shown in Fig.

Referring again to FIG. 5, the determination unit 35 may determine whether or not a normal landing has occurred by comparing the degree of exposure of the marker based on the reference image and the reference pattern area in the measurement area array. Hereinafter, the process of determining whether the determination unit 35 is normally seated will be described in detail with reference to FIG.

FIG. 15 illustrates determination of whether or not a normal seating is performed through the semiconductor placement inspection apparatus of the present invention.

The control unit 30 of the present invention may provide a user interface to the user to control the process of the semiconductor placement inspection apparatus through the display device.

Referring to FIG. 15, the user (inspector) can select the measurement function A through the determination unit 35, edit the parameter F for measurement and execute the determination unit 35 (G) , The determination result can be confirmed (H) through the viewer (H).

The parameter includes identification information (Name) of the judgment item, item and value (Item_Name, Item_value) of the result list, judgment method information (Operator) for range judgment and a judgment mode (Decide mode) .

The determination method information includes information on an allowable range based on the degree of exposure of the marker between the reference image and the reference pattern area in the measurement area array. Specifically, LOWER is determined to be normal if the value is below the specified value, UPPER to be determined to be normal if the value is above the specified value, INNER or Equal to be determined to be normal if the value is within the specified range, OUTTER May include a selection mode of. The particular value or specific range may be a value or a range derived from the matching rate of the reference image with the acquired image.

The determination mode includes a mode (AbsoluteVal) capable of determining the range using the set value as it is, a mode (RelativeVal) capable of determining the range with a relative change value based on the set value, a relative change value A mode (LanResult-OK) for setting a character value to be transmitted when determining to be normal, and a mode (LanResult-NG) for setting a character value to be transmitted when it is determined to be defective.

Referring to FIG. 5 again, the control unit 30 may further include a reference image registration unit (not shown) for setting a pattern area for determining whether a normal seating is established and registering the set pattern area as the reference image.

FIG. 6 is a schematic side view of the semiconductor device when the semiconductor device is normally mounted on the test socket, and FIG. 7 is a schematic plan view of the semiconductor device when the semiconductor device is normally mounted on the test socket.

6 and 7, when the semiconductor is normally placed on the test socket, the bottom surface of the semiconductor is completely in close contact with the seating portion 121, so that the semiconductor can be disposed side by side with the seating portion 121. When the semiconductor is normally mounted on the test socket, the marker exposure control unit 15 is rotated to the maximum extent inside the test socket 10, and the semiconductor pressing unit 151 presses the upper surface of the semiconductor, Can be prevented.

The marker exposure control unit 15 is rotated to the maximum extent so that the marker M displayed in the vicinity of the outer edge of the marker exposure control unit 15 in the upper body 11 is not blocked, And can be exposed to the outside. In other words, when the marker M is not seen at all on the marker M and the marker M is placed on the upper side of the test socket 10, the overall shape of the marker M And can be photographed by the camera 21.

The control unit 30 determines that the shape of the marker M photographed by the camera 21 is normal when the shape of the marker M is the same as that shown in FIG. 7, and continues the inspection of the semiconductor in the test socket 10 without stopping the operation of the picker. However, according to the embodiment, only a part of the markers M among the four markers M shown in FIG. 7 may be compared to determine whether or not the semiconductor is properly seated. For example, when the illumination unit 27 is located only at the upper portion or the lower portion, only the upper marker or the lower marker of FIG. 7 can be compared to determine whether or not the seating of the semiconductor is normal. In this case, the left marker and the right marker are not displayed in Fig. 7 and can not be used as a criterion for determining whether or not the seating of the semiconductor is normal.

Fig. 8 is a schematic view of the test socket in a case where the semiconductor is poorly mounted, and Fig. 9 is a schematic plan view of the test socket in a case where the semiconductor is poorly mounted.

8 and 9, when the semiconductor is not adhered to the test socket, the bottom surface of the semiconductor does not completely adhere to the seating portion 121, one end of the semiconductor contacts the seating portion 121, Can be separated from the seat part 121. In other words, the semiconductor can be disposed obliquely without being disposed side by side with the seating portion 121.

 In addition, when the semiconductor is badly adhered to the test socket, the semiconductor pushes the semiconductor pressing portion 151 outward so that the marker exposure adjusting portion 15 is rotated to the outside of the test socket 10 by a predetermined angle.

The marker exposure control unit 15 is rotated to the outside of the test socket 10 by a predetermined angle so that the outer edge of the marker exposure control unit 15 covers a part of the marker M displayed near the marker socket exposure control unit 15. Accordingly, the entire shape of the marker M is exposed to the outside, and the remaining shape not covered by the marker exposure control unit 15 is exposed to the outside.

  In other words, when the marker M is hung on the camera 21 installed on the upper portion of the test socket 10, the marker exposure control section 15 covers a part of the marker M, And can be photographed by the camera 21.

The control unit 30 determines that the position of the marker M photographed by the camera 21 is the same as that shown in FIG. 9, and then stops the operation of the picker for a moment. After the semiconductor of the test socket 10 is normally seated The inspection of the semiconductor is carried out.

Hereinafter, the operation of the semiconductor placement inspection apparatus according to the present invention will be described with reference to FIGS. 10 and 11. FIG.

10 is a flowchart showing a semiconductor placement inspection method according to the present invention.

10, the picker pushes the upper body 11 of the test socket 10 with the semiconductor being fed by vacuum suction or the like, lowering the semiconductor into the lower body 12, 11, the upper body 11 moves upward due to the restoring force of the elastic member 17, and the marker exposure control unit 15 rotates to the inside of the test socket 10 to press the semiconductor (S1010).

The image of the marker M displayed on the test socket 10 is collected through the camera 21 in step S1020 and the image photographed by the camera 21 is compared with the reference image through the control unit in step S1030.

In step S1040, the control unit 30 determines whether the semiconductor is normally seated in the test socket 10 according to the matching rate of the camera image and the reference image according to whether the marker M is exposed or not.

If it is determined in step S1050 that the semiconductor is not properly mounted on the test socket 10, the controller 30 stops the operation of the picker and normally places the semiconductor on the mounting part 121 of the test socket 10, Current is supplied to the socket lead (13) of the socket (10) so as to inspect the electrical characteristics of the semiconductor.

On the other hand, if it is determined in step S1060 that the semiconductor has been properly placed in the test socket 10, the tester tests the electrical characteristics of the semiconductor by flowing a current through the socket lead 13 of the test socket 10, The semiconductors having been inspected for their electrical characteristics are removed from the test socket 10 by pressing the upper body 11 using a picker.

11 is a flowchart showing a semiconductor placement inspection method through the semiconductor placement inspection apparatus of the present invention.

The semiconductor placement inspection method of FIG. 11 includes a test socket for displaying a marker whose area is recognized according to a seating position of a semiconductor, an image acquisition unit for acquiring an image including a marker when the semiconductor is loaded on the test socket, And a control unit for comparing the degree of exposure with the degree of exposure of the marker in the image acquired by the image acquiring unit and determining whether the semiconductor is normally seated.

Referring to FIG. 11, in step S1110, connection state information for at least one or more cameras and camera parameter information for identification information, initialization state, exposure time, and brightness of at least one camera are set through the control unit.

In step S1120, the controller combines one or more images collected from at least one camera to generate a merge image.

In step S1130, a reference pattern area and a search area for searching the reference pattern area are set for the merge image generated through the control part.

In step S1140, a measurement area array for the generated merge image is set in consideration of the number and spacing of at least one semiconductor of the semiconductor array through the control unit.

In step S1150, whether the normal seating is determined by comparing the exposure level of the marker based on the reference image and the reference pattern area in the measurement area array.

The method according to an embodiment may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions to be recorded on the medium may be those specially designed and configured for the embodiments or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, if the techniques described are performed in a different order than the described methods, and / or if the described components are combined or combined in other ways than the described methods, or are replaced or substituted by other components or equivalents Appropriate results can be achieved.

 Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (11)

delete A test socket in which a semiconductor is seated and in which a marker whose area is recognized at a predetermined angle according to a seating position of the semiconductor is displayed;
An image acquiring unit for acquiring an image including the marker when the semiconductor is mounted on the test socket; And
A control unit for comparing the degree of exposure of the marker in the reference image with the degree of exposure of the marker in the image acquired by the image acquiring unit to determine whether the semiconductor is seated at the designated position;
Lt; / RTI >
The test socket comprises:
A lower body having a seating portion on which a semiconductor can be seated;
An upper body slidably coupled to a guide bar of the lower body and having an opening through which a semiconductor can be inserted;
A marker exposure adjusting part whose one end is selectively engaged with the semiconductor mounted on the lower body and whose degree of covering the marker varies depending on the seating position of the semiconductor; And
A socket lead provided on the lower body and electrically connected to a lead of the semiconductor;
And a semiconductor substrate. 3. The method of claim 2,
Wherein the marker exposure control unit is rotatably coupled to the lower body and the other end rotates in engagement with the upper body.
The method of claim 3,
Wherein the marker exposure control unit includes a semiconductor pressing unit for pressing a semiconductor placed on the lower body,
When the upper body moves toward the lower body, the marker exposure adjusting part rotates to the outside of the test socket so that the semiconductor pressing part moves to the outside of the test socket,
Wherein when the upper body is away from the lower body, the marker exposure control part is rotated to the inside of the test socket so that the semiconductor pressing part moves to the inside of the test socket.
5. The method of claim 4,
Wherein when the semiconductor is poorly mounted on the lower body, the semiconductor pushes the semiconductor pressing portion so that the marker exposure adjusting portion is rotated to the outside of the test socket, and the marker exposure adjusting portion covers a part of the marker . A test socket in which a semiconductor is seated and in which a marker whose area is recognized at a predetermined angle according to a seating position of the semiconductor is displayed;
An image acquiring unit for acquiring an image including the marker when the semiconductor is mounted on the test socket; And
A control unit for comparing the degree of exposure of the marker in the reference image with the degree of exposure of the marker in the image acquired by the image acquiring unit to determine whether the semiconductor is seated at the designated position;
Lt; / RTI >
Wherein the image obtaining unit comprises:
At least one camera for collecting at least one image for a semiconductor array comprising at least one semiconductor;
A lens provided in each of the at least one or more cameras to adjust a focal distance; And
And an illumination unit for illuminating the marker of at least one test socket on which the at least one semiconductor is mounted to allow the camera to recognize the marker.
And a semiconductor substrate. The method according to claim 6,
The control unit
A camera setting unit for setting connection state information for the at least one camera and camera parameter information for identification information, initialization state, exposure time, and brightness of the at least one camera;
An image preprocessing unit for combining the one or more images collected from the at least one camera to generate a merge image;
An area setting unit for setting a reference pattern area for the generated merge image and a search area for searching the reference pattern area;
A measurement setting unit configured to set a measurement area array for the generated merge image in consideration of the number and spacing of at least one or more semiconductors of the semiconductor array; And
A determination unit for comparing the exposure level of the marker based on the reference image and the reference pattern area in the measurement area array to determine whether the normal landing has occurred,
And a semiconductor substrate. 8. The method of claim 7,
The control unit
A reference image registration unit for registering the set pattern area as the reference image,
Further comprising: Pressing the semiconductor mounted on the test socket with the marker exposure adjusting portion of the test socket rotating;
Collecting an image including a marker displayed on the test socket through a camera;
Comparing the collected image with a reference image through a control unit and determining whether the semiconductor is normally seated in the test socket according to the degree of matching between the camera image and the reference image according to whether the marker is exposed or not;
Wherein the control unit controls the semiconductor to perform an inspection if the semiconductor is determined to be a normal seating on the test socket and controls the picker to be a normal seating for the semiconductor when the semiconductor is determined to be a defective seating step
And a semiconductor substrate.
An image acquiring unit for acquiring an image including the marker when the semiconductor is mounted on the test socket, and an image acquiring unit for acquiring an image of the marker, And a control unit for comparing the degree of exposure of the marker in the image collected by the acquiring unit and determining whether the semiconductor is normally mounted, the method comprising the steps of:
Setting connection state information for at least one camera and camera parameter information for identification information, initialization state, exposure time, and brightness of the at least one camera through a control unit;
Generating a merged image by combining one or more images collected from the at least one camera through the control unit;
Setting a reference pattern region and a search region for searching the reference pattern region with respect to the generated merge image through a control unit;
Setting a measurement area array for the generated merge image taking into account the number and spacing of at least one semiconductor of the semiconductor array through the control part; And
Comparing the exposure of the marker based on the reference image and the reference pattern area in the measurement area array to determine whether the normal seating is established
And a semiconductor substrate. A computer-readable recording medium having recorded thereon a program for performing the method of any one of claims 9 to 10.
KR1020140007032A 2014-01-21 2014-01-21 Apparatus and method for inspecting duly reach of semiconductor KR101432007B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003247807A (en) 2002-02-25 2003-09-05 Hitachi Ltd Apparatus and method for measuring matching accuracy and method and system for manufacturing semiconductor device
KR20070080528A (en) * 2006-02-07 2007-08-10 삼성전자주식회사 Wafer atage of semiconductor manufacture apparatus
US20090226078A1 (en) 2004-07-26 2009-09-10 Yong-Ju Kim Method and apparatus for aligning a substrate and for inspecting a pattern on a substrate
JP2012109178A (en) 2010-11-19 2012-06-07 Sensata Technologies Massachusetts Inc Socket

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003247807A (en) 2002-02-25 2003-09-05 Hitachi Ltd Apparatus and method for measuring matching accuracy and method and system for manufacturing semiconductor device
US20090226078A1 (en) 2004-07-26 2009-09-10 Yong-Ju Kim Method and apparatus for aligning a substrate and for inspecting a pattern on a substrate
KR20070080528A (en) * 2006-02-07 2007-08-10 삼성전자주식회사 Wafer atage of semiconductor manufacture apparatus
JP2012109178A (en) 2010-11-19 2012-06-07 Sensata Technologies Massachusetts Inc Socket

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