KR101418520B1 - Semiconductor circuit device equipped with finite state machine for setting the order of converting the state and method using the same - Google Patents

Abstract

Disclosed is a semiconductor element and a method including a Finite State Machine (FSM) for flexibly setting a conversion order of states. A finite state machine having a finite state machine fixed by hardware, the finite state machine comprising: a user defined register for receiving and storing data for converting a state in a predetermined order; A state controller for referring to the data stored in the user-defined register, detecting the predetermined order using the referenced data, and controlling the state to be switched in the order detected; And a finite state machine for flexibly setting a state conversion order including a state converter for converting the state according to the control of the state machine. Thus, the user can arbitrarily and flexibly adjust the order of state conversion of semiconductor devices.

State, transformation, order, finite state machine, semiconductor device, pipeline, level jump

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a semiconductor device having a finite state machine for flexibly setting a state transition order of a semiconductor device,

The present invention relates to a semiconductor device having a finite state machine and a method thereof. More particularly, the present invention relates to a semiconductor device having a finite state machine and a method thereof, characterized in that the order of conversion of states is set to be fluid.

In a conventional finite state machine (FSM) implemented by software, it is possible to change the state arbitrarily according to a user's request. For example, in game software or the like, a user can change the state of an object to various arbitrary states depending on the state of an object or surrounding conditions.

However, it is different in finite state machines implemented in semiconductor devices such as Programmable Logic Arrays (PLAs) and Application Specific Integrated Circuits (ASICs). That is, since the order of state conversion is fixed as previously set, the user can not arbitrarily adjust the state conversion.

As described above, the semiconductor device designed and manufactured according to a certain purpose has a problem that it is only possible to change the state in the fixed order, and the order of changing the state of the user can not be flexibly adjusted as desired.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device having a finite state machine for flexibly setting a state change order.

It is another object of the present invention to provide a method for dynamically setting a state transition order in a semiconductor device.

According to an aspect of the present invention, there is provided a semiconductor device including a finite state machine fixed by hardware for setting a state change order, wherein the finite state machine receives data for converting states into a predetermined order A state register for referring to the data stored in the user defined register and for controlling the state to be switched in the detected order after detecting the predetermined order through the referenced data; And a state transducer for converting the state according to a control of the finite state machine, wherein the finite state machine sets the transformation order of the state to a fluid state.

Here, the state controller may include: a state sequence detector for detecting a predetermined sequence for converting the state from the data stored in the user-defined register; and a control signal generator for controlling the state to be switched according to the detected predetermined sequence And a multi-state switch for transmitting a control signal generated by the controller to each state implementation circuit in the state transducer.

According to another aspect of the present invention, there is provided a semiconductor device including a finite state machine fixed by hardware for setting a state change order, the finite state machine comprising: A user register for receiving and storing data; a state controller for detecting the predetermined order by referring to data stored in the user-defined register, and controlling the state to be converted in a pipeline manner according to the detected order; And a state transducer for transducing the state according to the control of the state controller. The finite state machine includes:

Here, the state controller may include: a state sequence detector for detecting the predetermined sequence from the data stored in the user-defined register; and a control signal for controlling the state to be switched in a pipelined manner in accordance with the detected sequence And a multi-state switch for transmitting the generated control signal to the state transducer.

Here, the state controller may further include: a state sequence detector for detecting the predetermined sequence from the data stored in the user-defined register; a level jump detector for detecting data indicating a level jump from the data stored in the user- A pipeline control unit for resetting the detected predetermined order by using the data indicating the detected level jump and generating a control signal for controlling the state to be switched in a pipeline manner in accordance with the reset order; And a multi-state switch for transmitting the generated control signal to the state transducer.

According to another aspect of the present invention, there is provided a data processing apparatus including a user-defined register for receiving and storing data for converting a state, a state controller for detecting a conversion order of the state and controlling conversion, The method comprising the steps of: receiving and storing data for transforming the state in a predetermined order; and detecting the predetermined order by referring to the stored data The method comprising: generating a control signal for controlling the state to be converted according to the detected order; and converting the state according to the generated control signal. ≪ / RTI >

At this time, in the step of generating the control signal, it may be configured to generate a control signal for controlling to convert the state in a pipelined manner.

On the other hand, when data indicating a level jump is detected in the detected data in the step of detecting the predetermined order, in the step of generating the control signal in the step of generating the control signal, And generate a control signal.

When the semiconductor device and the method including the finite state machine for flexibly setting the state change order according to the present invention as described above are used, there is an effect that the order of changing the states of the semiconductor elements can be flexibly adjusted arbitrarily by the user .

In addition, the user can flexibly adjust the order of state conversion even in the pipeline state conversion.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail.

It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing. It should be noted that the same components in the drawings are denoted by the same reference numerals and symbols as possible even if they are shown in different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The terms first, second, A, B, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. 1 is a block diagram of a semiconductor device having a finite state machine for flexibly setting a state transition sequence according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor device 100 according to the present invention includes a user-defined register 110, a state controller 120, and a state transformer 130. Here, the state controller 120 includes a state sequence detector 121, a controller 122, and a multi-state switch 123. Hereinafter, the semiconductor device 100 and each configuration will be described in detail. The multi-state switch 123 may be implemented, for example, as a MUX.

First, the semiconductor device 100 is a concept that includes both a programmable logic array (PLA), an ASIC, and the like. That is, the semiconductor device includes a memory element or a non-memory element which is implemented in hardware according to a certain purpose. This semiconductor device 100 can be said to be a finite state machine. In the case of a conventional semiconductor device, a finite number of states can be mutually converted in a fixed order according to a predetermined condition or the like. However, the semiconductor device 100 according to the present invention can be flexibly changed in accordance with a user's input value, and the state can be changed according to the order.

Here, the user-defined register 110 is a structure for receiving and storing data for converting a state into a predetermined order. That is, it is a configuration in which the user can flexibly designate the conversion order of the state arbitrarily. Here, the user designates and inputs these input values through another user interface (UI) connected to the semiconductor device 100, and the input data is finally input to the user-defined register 110 on the semiconductor device 100. [ As shown in FIG. In this case, the predetermined order may be a sequence in which the user inputs data, or may be a sequence specified by the user separately. However, the data stored in the user-defined register 110 is data specifying the order of state conversion.

The state controller 120 refers to the data stored in the status register 110 and analyzes the referenced data to detect a predetermined order. And generates a control signal for controlling the state to be changed according to the detected order, and transmits the control signal to the state converter 130. That is, it is a configuration for generating a control signal that enables the state to be converted according to a predetermined order inputted by the user. In order to implement each of these functions, the state controller 120 may include a state sequence detector 121, a controller 122, and a multi-state switch 123. The functions of each configuration are as follows.

First, the state-order detector 121 detects a conversion order of a state designated by the user from the data stored in the user-defined register 110. By referring to a register that stores data in accordance with the conversion order designated by the user. At this time, the state sequence detector 121 may be configured such that the state sequence detector 121 refers to the data using a designated address of the user register 110. On the other hand, the control unit 122 generates a control signal for converting each state using the input data of the user according to the order detected by the state sequence detector 121. Here, the control signal is a signal for controlling the state transducer 130, and controls the state to be changed according to the order desired by the user. At this time, the controller 122 transmits the control signal generated through the multi-state switch 123 to the state converter 130. Meanwhile, the state transducer 130 is a series of logic circuits implemented to convert the state of the semiconductor device 100, which is a kind of finite state machine. For example, the state transducer 130 is configured so that the state W, the state X, the state Y, and the state Z are mutually converted in a predetermined order, and each of the implementation circuits for implementing each state is configured separately . A control signal transmitted through the multi-state switch 123 may be input to each of the separated circuits.

Next, FIG. 2A is a block diagram of a semiconductor device having a finite state machine for flexibly setting the state transition sequence according to another embodiment of the present invention.

2A, a semiconductor device 200 according to the present invention includes a user-defined register 210, a state controller 220, and a state transformer 230. [ Here, the state controller 220 includes a state sequence detector 221, a pipeline controller 222, and a multi-state switch 223.

At this time, the semiconductor device 200 is basically the same as the semiconductor device 100 of FIG. 1, but has a feature of processing the state conversion by a pipelined method. That is, it is possible to set the order of conversion of the state by the user, but the state is converted by the pipeline method.

Here, the pipelined method is to process a plurality of series of operations or processes simultaneously in the semiconductor device 200, and basically includes fetching, decoding, and execution of data and instructions .

Referring to FIG. 2B, it can be seen that the state change order set by the user in the semiconductor device 200 is composed of state W, state X, state Y, and state Z. FIG. At the operation level 0 of the semiconductor device 200, data specifying the state W1 of the first operation is fetched.

Next, at the operation level 1, the state X1 of the first operation and the state W2 of the second operation are fetched. At the same time, data of the state W1 corresponding to the operation level 0 is decoded.

Next, data specifying the state Y1 of the first operation, the state X2 of the second operation, and the state W3 of the third operation are fetched at the operation level 2. At the same time, a control signal for decoding data corresponding to the state X1 and the state W2 corresponding to the operation level 1 and converting it into the state W1 corresponding to the operation level 0 is generated.

As described above, the semiconductor device 200 is configured to be flexible in the order of state conversion, and is also applicable to a plurality of operations or processes according to a pipeline method. Hereinafter, each configuration of FIG. 2A will be described in more detail.

The user-defined register 210 is a structure for receiving and storing data for converting a state in a predetermined order according to a pipeline method. That is, to allow the semiconductor device 200 to perform various operations in a pipelined manner, the user-defined register 210 stores data for setting the order of conversion of states for each operation. Where the data can be each command specifying the state to be transformed.

The state controller 220 refers to the data stored in the user-defined register 210 and controls the state to be converted according to the pipeline method using the referenced data. That is, the state is controlled to be changed according to the order set by the user. The exciter state controller 220 may include a state sequence detector 221, a pipeline controller 222, and a multi-state switch 223.

First, the state-order detector 221 detects a state change order from the data stored in the user-defined register 221. It is possible to detect the state change order in accordance with a preset method and to fetch data according to the change order. And to pass the fetched data to the pipeline control unit 222. [ The pipeline controller 222 generates a control signal for controlling the state conversion in a pipeline manner in accordance with the order detected by the state sequence detector 221. And transfers it to the state transducer 230 through the multi-state switch 223. More specifically, the pipeline controller 222 receives the fetched data according to the order detected by the state sequence detector 221, decodes the fetched data, and generates a control signal for converting the state according to the decoding And transmits it to the state converter 230. Here, the pipeline control unit 222 processes the above process according to a pipeline method, which will be described in more detail with reference to FIGS. 2C and 2D.

It is assumed that each of the states W1, X1, etc. referred to in FIG. 2B is set to a state 1, a state 3, and so on as shown in the table of FIG. 2C. In other words, the first to fourth operations are all set to the state 1, state 3, state 4, state 2, and the conversion order is set by the user.

Referring to FIG. 2D, the pipeline control unit 222 may process the first to fourth operations simultaneously according to the pipeline method. First, at operation level 0, data or command designating state 1 of the first operation is fetched from state sequence detection section 221.

Next, at operation level 1, data or command designating state 3 of the first operation and data or instruction designating state 1 of the second operation are fetched while decoding state 1 corresponding to operation level 0.

Next, at the operation level 2, a control signal for data designating the state 1 corresponding to the operation level 0 is generated and transmitted to the state converter 230, and the data for designating the state 3 corresponding to the operation level 1 and the state 1 From the state sequence detector 221, data specifying state 4 of the first operation, data specifying state 3 of the second operation, and data specifying state 1 of the third operation, while decoding the designated data .

In this way, the state controller 220 can flexibly set the state change order, and can be applied to a plurality of operations or processes according to a pipeline method.

The state transducer 230 performs the state transitions according to the control signal received from the pipeline controller 222 through the multi-state switch 223. Of course, this also means that a plurality of operations or processes will be processed in a pipelined manner.

Next, FIG. 3A is a block diagram of a semiconductor device having a finite state machine for flexibly setting a state transition sequence according to another embodiment of the present invention.

3A, a semiconductor device 300 according to the present invention includes a user-defined register 310, a state controller 320, and a state transformer 330. [ Here, the state controller 320 includes a state sequence detector 321, a level jump detector 322, a pipeline controller 323, and a multi-state switch 324. The semiconductor device 300 basically has the same function as the semiconductor device 200 of FIG. 2A, but further includes a level jump detection unit 322. The semiconductor device 300 of FIG. 3A is also configured by a pipeline method, but it is possible to reset the order by level jump when setting the state change order by the user. This will be described below in detail with reference to FIG. 3A.

First, the user-defined register 310 is configured to receive and store data for converting states into a predetermined order, and is the same as the user-defined register 21 of FIG. 2A, but includes data indicating a level jump .

The status sequence detector 321 is the same as the status sequence detector 221 of FIG. 2A. And to transmit the data or commands made up of the detected state to the level jump detector.

The level jump detection unit 322 detects data indicating a level jump among the respective data indicating this state change. Data indicating this level jump will be generated and detected according to a preset appointment or agreement. At this time, the detected result on the level jump is transmitted to the pipeline control unit 323. However, data indicating a level jump may not be detected.

The pipeline controller 323 generates a control signal according to a conversion order of the state set by the user according to the pipeline method, and transmits the control signal to the state converter 330. However, the state change order is reset by using the result detected by the level jump detection unit 322. However, as a result of the detection by the level jump detecting section 322, if there is no data for instructing the level jump, the resetting operation of the conversion order according to the level jump is omitted. Hereinafter, this will be described in detail with reference to FIG. 2 and FIG. 3B to FIG.

Referring to FIGS. 2B and 3B, it can be seen that the conversion order of the state set by the user is set differently for each operation. It can be seen here that the state X1 of the first operation is set to jump 3. If the conversion order is arranged according to the pipeline method, the state is set as shown in FIG. 3C. Here, the jump causes the state change order to be changed to the indicated operation level. This is also configured to be controlled by the pipeline control unit 323 according to the predefined or defined definition. 3C means that jump 3 of the first operation at operation level 1 moves to operation level 3, whereby both the first operation and the second operation are configured to perform the state transition indicated by operation level 3. At the operation level 3, control signals for the state change of state 2, state 4, no state and state 1, respectively, will be generated. Next, at the operation level 4, control signals for the conversion of the state 1, the state 2, and the state 3 are respectively generated. At the operation level 5, since there is the jump 3 in the first operation, the control signal for the state 2, state 4, and state 1 is generated respectively by moving to the operation level 7. At this time, since the states of the operation level 0 to the operation level 3 are continuously repeated, the jump 3 must be controlled to move to the operation level 7 corresponding to the operation level 3.

Finally, FIG. 4 is a flowchart of a method for flexibly setting the order of conversion of states in a semiconductor device according to an embodiment of the present invention. Hereinafter, each configuration will be described with reference to Fig. 4 according to the configuration of Fig. 3a.

4, the data for converting the state is received and stored in the user-defined register 310 (S100). Then, the state-order detector 321 receives the data stored in the user- (S200). The order for state conversion is detected through the data referenced here. The level jump detection unit 322 determines whether there is data indicating a level jump in the upper data (S300). The level jump detection unit 322 transfers the determination result to the pipeline control unit 323. If there is no data indicating a level jump, the pipeline control unit 323 generates a control signal for converting the state according to the conversion order of the detected state, according to a pipeline method, (S450). However, if there is data indicating the level jump, the control unit 300 resets the conversion order of the detected state according to the level jump instruction to generate the control signal. The generated control signal is transmitted to the state transformer 330 through the multi-state switch 324 (S400). The state transformer 330 transforms the state according to the control signal generated in S400 and S450. S500)

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims It can be understood that

1 is a block diagram of a semiconductor device having a finite state machine for flexibly setting a state transition sequence according to an embodiment of the present invention.

2A is a block diagram of a semiconductor device having a finite state machine for flexibly setting a state transition sequence according to another embodiment of the present invention.

FIG. 2B is a diagram illustrating a basic processing procedure according to a pipeline method according to another embodiment of the present invention.

FIG. 2C is a diagram illustrating each state of the pipeline system to explain another embodiment of the present invention.

FIG. 2D is an exemplary diagram illustrating a state in which each state is converted in a pipeline manner according to another embodiment of the present invention.

FIG. 3A is a block diagram of a semiconductor device having a finite state machine for flexibly setting a state transition sequence according to another embodiment of the present invention. FIG.

FIG. 3B is a diagram illustrating each state of the pipeline method for explaining another embodiment of the present invention.

FIG. 3C is an exemplary diagram illustrating a conversion order of each state in a pipeline manner according to another embodiment of the present invention. FIG.

FIG. 3D is an exemplary diagram showing the actual conversion order of each state in a pipeline manner according to another embodiment of the present invention.

4 is a flowchart of a method for dynamically setting the order of conversion of states in a semiconductor device according to an embodiment of the present invention.

Claims (8)

delete delete A semiconductor device comprising a finite state machine fixed by hardware for setting a transformation order of a state, the finite state machine comprising: A user-defined register for receiving and storing data for converting states into a predetermined order; A state controller for detecting the predetermined order by referring to the data stored in the user-defined register, and controlling the state to be converted in a pipelined manner according to the detected order; And And a state transducer for converting the state under the control of the state controller, Wherein the finite state machine flexibly sets the order of transformation of the state, Wherein the status controller comprises: a status sequence detector for detecting the predetermined sequence from data stored in the user-defined register; A level jump detecting unit for detecting data indicating a level jump among data stored in the user-defined register; A pipeline control unit for resetting the detected predetermined order using data indicating the detected level jump and generating a control signal for controlling the state to be switched in a pipeline manner in accordance with the reset order; And a multi-state switch for transmitting the generated control signal to the state transducer. 4. The apparatus of claim 3, A state sequence detector for detecting the predetermined sequence from the data stored in the user-defined register; A pipeline control unit for generating a control signal for controlling the conversion of the state in a pipeline manner according to the detected predetermined order; And And a multi-state switch for transmitting the generated control signal to the state transducer. delete A finite state machine having a user defined register for receiving and storing data for transforming a state, a state controller for detecting a transformation order of the state and controlling the transformation, and a state transformer for transforming the state In a semiconductor device, Receiving and storing data for converting the states into a predetermined order; Detecting the predetermined order by referring to the stored data; Generating a control signal for controlling to convert the state according to the detected order; And converting the state according to the generated control signal, A control signal for controlling the state to be converted in a pipeline manner is generated in the step of generating the control signal, When the data indicating the level jump is detected in the detected data in the step of detecting the predetermined order, the order detected in the step of generating the control signal is reset in accordance with the data indicating the level jump, Wherein the step of generating the state information comprises the steps of: delete delete

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