KR101381988B1 - Vertical light emitting diode and method of fabricating the same - Google Patents

Abstract

A method of manufacturing a vertical light emitting diode is disclosed. The method includes forming an uneven pattern on the sacrificial substrate by patterning. The first nitride semiconductor layer and the second nitride semiconductor layer are formed on the uneven pattern, and the compound semiconductor layers including the active layer are formed on the second nitride semiconductor layer. In addition, a reflective layer is formed on the compound semiconductor layers, and a conductive substrate is attached thereto, and the sacrificial substrate is separated from the semiconductor layers. The method is further characterized in that voids are formed inside the second nitride semiconductor layer.

Description

Vertical light emitting diode manufacturing method {VERTICAL LIGHT EMITTING DIODE AND METHOD OF FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical light emitting diode manufacturing method, and more particularly, to a vertical light emitting diode manufacturing method capable of easily separating a substrate and preventing bowing after separating the substrate.

In general, nitrides of Group III elements, such as gallium nitride (GaN) and aluminum nitride (AlN), have excellent thermal stability and have a direct transition energy band structure. As a lot of attention. In particular, blue and green light emitting devices using gallium nitride (GaN) have been used in various applications such as large-scale color flat panel displays, traffic lights, indoor lighting, high-density light sources, high resolution output systems and optical communication.

The nitride semiconductor layer of such a group III element, in particular, GaN, is difficult to fabricate a homogeneous substrate capable of growing it, and thus, it is difficult to fabricate a homogeneous substrate capable of growing it, such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy; MBE) and other processes. A sapphire substrate having a hexagonal system structure is mainly used as a heterogeneous substrate. However, since sapphire is an electrically insulator, it restricts the light emitting diode structure and is very stable mechanically and chemically, making it difficult to process such as cutting and shaping. In recent years, a technology for growing a nitride semiconductor layer on a heterogeneous substrate such as sapphire and then separating the heterogeneous substrate to fabricate a vertical-type LED has been researched.

1 is a cross-sectional view illustrating a method of manufacturing a vertical light emitting diode according to the prior art.

Referring to FIG. 1A, gallium nitride-based compound semiconductor layers are sequentially grown on a sacrificial substrate 11 such as a sapphire substrate. The compound semiconductor layers include a first conductivity type semiconductor layer 15, an active layer 17, and a second conductivity type semiconductor layer 19. In addition, a buffer layer 13 formed of a low temperature buffer layer and a high temperature buffer layer is interposed between the first conductivity type semiconductor layer 15 and the sacrificial substrate 11.

Referring to FIG. 1B, a conductive substrate 23 is attached to the compound semiconductor layers. The conductive substrate 23 is generally attached on the compound semiconductor layers by the bonding layer 21. On the other hand, a reflective layer (not shown) may also be interposed between the conductive substrate 23 and the compound semiconductor layers.

Referring to FIG. 1C, the sacrificial substrate 11 is separated from the compound semiconductor layers. At this time, the buffer layer 13 is also removed, and the first conductivity type compound semiconductor layer 15 is exposed. Thereafter, an electrode pad 27 is formed on the exposed first conductive compound semiconductor layer 15, and individual light emitting diode chips are completed by cutting the conductive substrate 23.

According to the prior art, by adopting the conductive substrate 23 having excellent heat dissipation performance, the light emitting efficiency of the light emitting diode can be improved, and a light emitting diode having a vertical structure can be provided.

However, since the compound semiconductor layers are firmly grown on the sacrificial substrate 11, it is difficult to separate the sacrificial substrate 11 from the compound semiconductor layers by a simple process such as wet etching, and thus laser lift-off. Relatively expensive processes such as) are being used.

In addition, after the sacrificial substrate 11 is separated, the residual stress due to lattice mismatch between the compound semiconductor layers and the sacrificial substrate 11 and the coefficient of thermal expansion between the conductive substrate 23 and the compound semiconductor layers are obtained. Due to the difference or the like, warpage of the compound semiconductor layers occurs. The warpage phenomenon of the compound semiconductor layers makes the process of depositing a metal such as the electrode pad 27 on the semiconductor layers difficult, and reduces the yield of the light emitting diode.

An object of the present invention is to provide a method of manufacturing a vertical light emitting diode that can easily separate the sacrificial substrate.

Another object of the present invention is to provide a method of manufacturing a vertical light emitting diode that can prevent warpage of a compound semiconductor layer that appears after separation of a sacrificial substrate.

In order to achieve the above technical problem, the present invention provides a vertical light emitting diode manufacturing method. The method includes patterning the sacrificial substrate to form an uneven pattern. A low temperature buffer layer is formed on the sacrificial substrate having the uneven pattern. The low temperature buffer layer is formed to cover recesses and convex portions of the concave-convex pattern. Subsequently, a high temperature buffer layer is formed on the low temperature buffer layer. The high temperature buffer layer has pores formed on the convex portions therein. Meanwhile, compound semiconductor layers including a first conductive compound semiconductor layer, an active layer, and a second conductive compound semiconductor layer are formed on the high temperature buffer layer, and a conductive substrate is formed on the compound semiconductor layers. Subsequently, the sacrificial substrate is separated from the compound semiconductor layers. As the voids are formed in the high temperature buffer layer, the sacrificial substrate can be easily separated, and the warpage phenomenon due to the lattice mismatch and the thermal expansion coefficient difference between the sacrificial substrate and the compound semiconductor layers can be prevented.

Concave portions of the concave-convex patterns may be formed to have a hemispherical shape. Meanwhile, the distance between the recesses may be relatively smaller than the diameter of the recesses.

In addition, separating the sacrificial substrate may be performed using laser lift-off or conventional wet etching techniques.

According to the embodiments of the present invention, it is possible to easily separate the sacrificial substrate, and to provide a method of manufacturing a vertical light emitting diode capable of preventing the warpage of the compound semiconductor layer appearing after the sacrificial substrate is separated.

1 is a cross-sectional view illustrating a method of manufacturing a vertical light emitting diode according to the prior art.
2 to 7 are cross-sectional views illustrating a method of manufacturing a vertical light emitting diode according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, and the like of the components may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

2 to 7 are cross-sectional views illustrating a method of manufacturing a vertical light emitting diode according to an embodiment of the present invention.

Referring to FIG. 2, a sacrificial substrate 51 suitable for growing a compound semiconductor layer is prepared. The sacrificial substrate 51 is generally a sapphire substrate, but may be another hetero substrate.

The sacrificial substrate 51 is patterned to form an uneven pattern having recesses 51a. The recessed portions 51a may be formed in a hemispherical shape as shown, but are not limited thereto, and may be formed in line patterns or mesh shapes parallel to each other.

Referring to FIG. 3, a low temperature buffer layer 53a is formed on the substrate 51 on which the uneven pattern is formed. The low temperature buffer layer 53a may be formed of Al x Ga 1-x N (0 ≦ x <1) by a process such as metal organic chemical vapor deposition (MOCVD) or molecular beam deposition (MBE). For example, a low temperature buffer layer 53a is formed at a temperature of 400 to 600 ° C. by a metal organic chemical vapor deposition method, and the low temperature buffer layer 53a covers concave portions 53a of the concave-convex pattern and convex portions between the concave portions. .

The low temperature buffer layer generally formed in the light emitting diode manufacturing process has a thickness of several tens of nm. However, such a low temperature buffer layer is relatively thin in thickness so that it does not completely cover recesses and convexities. Therefore, the low temperature buffer layer 53a is formed to have a sufficient thickness to cover all the recesses and the convex portions, and may be formed to have a thickness of 100 to 1000 nm, for example.

Referring to FIG. 4, after the low temperature buffer layer 53a is formed, the high temperature buffer layer 53 is formed by raising the temperature of the sacrificial substrate 51. The high temperature buffer layer is grown at a temperature of 800 ~ 1200 ℃, thereby growing a high temperature buffer layer 53 with less crystal defects such as dislocations and pinholes. As the high temperature buffer layer 53 grows, voids 53b are formed on the convex portions between the recessed portions 53a, and the upper surface thereof becomes flat. The voids 53b may be variously formed by controlling the shape of the uneven pattern, the distance between the recesses 53a, the growth rate of the high temperature buffer layer 53, or the growth mechanism. For example, if the growth rate of the high temperature buffer layer 53 is controlled quickly, the buffer layer grows faster than the upper portions of the concave portions 53a, thereby forming relatively large voids.

Referring to FIG. 5, compound semiconductor layers are formed on the high temperature buffer layer 53. The compound semiconductor layers include a first conductivity type compound semiconductor layer 55, an active layer 57, and a second conductivity type compound semiconductor layer 59. The compound semiconductor layers are III-N based compound semiconductor layers, and may be grown by a process such as metal organic chemical vapor deposition (MOCVD) or molecular beam deposition (MBE). The first conductivity type and the second conductivity type represent N-type and P-type, or P-type and N-type.

Referring to FIG. 6, a conductive substrate 61 is formed on the compound semiconductor layers. The conductive substrate 61 is a substrate such as Si, GaAs, GaP, AlGaINP, Ge, SiSe, GaN, AlInGaN or InGaN, but Al, Zn, Ag, W, Ti, Ni, Au, Mo, Pt, Pd, Cu It may be formed by attaching a single metal of Cr or Fe or an alloy substrate thereof on the compound semiconductor layers. In this case, the conductive substrate 61 may be attached to the compound semiconductor layers through the bonding layer 63, and a reflective layer (not shown) may be interposed between the conductive substrate 61 and the compound semiconductor layers. have. On the other hand, the conductive substrate 61 may be formed using a plating technique. That is, the conductive substrate 61 may be formed by plating a metal such as Cu or Ni on the compound semiconductor layers by using a plating technique.

Referring to FIG. 7, the sacrificial substrate 51 is separated from the compound semiconductor layers. The sacrificial substrate 51 may be separated by laser lift off (LLO) technology or other mechanical or chemical methods such as wet etching. In this case, the buffer layer 53 is also removed to expose the first conductivity type compound semiconductor layer 55.

In this embodiment, since the voids are formed in the high temperature buffer layer 53, it is easy to separate the sacrificial substrate. In particular, the sacrificial substrate 51 may be separated by a mechanical force, or may be separated using a simple process such as a conventional wet etching technique. Meanwhile, after the sacrificial substrate 51 is separated, the remaining high temperature buffer layer 53 may be removed using a polishing technique or an etching technique. In the meantime, when the high temperature buffer layer 53 is formed of an n-type compound semiconductor, the process of removing the high temperature buffer layer 53 may be omitted.

Subsequently, an electrode pad 67 is formed on the first conductivity type semiconductor layer 55. The electrode pad 67 is ohmic contacted to the first conductivity type compound semiconductor layer 55.

According to the present embodiment, voids are formed in the high temperature buffer layer 53 positioned between the sacrificial substrate 51 and the compound semiconductor layers. The pores relieve stress caused by the sacrificial substrate 51 due to the lattice mismatch and thermal expansion coefficient difference between the compound semiconductor layers. Accordingly, after the sacrificial substrate 51 is separated, bending of the compound semiconductor layers caused by residual stress is prevented.

Claims (11)

The uneven pattern is formed on the sacrificial substrate by patterning,
Forming a first nitride semiconductor layer on the uneven pattern,
Forming a second nitride semiconductor layer on the first nitride semiconductor layer,
Forming compound semiconductor layers including an active layer on the second nitride semiconductor layer,
Forming a reflective layer on the compound semiconductor layers and attaching a conductive substrate,
Separating the sacrificial substrate from the compound semiconductor layers,
Voids are formed in the second nitride semiconductor layer,
The sacrificial substrate is separated from the compound semiconductor layers using a wet etching technique using the pores or is separated by applying a mechanical force to the pores. The method according to claim 1,
The uneven pattern is a vertical light emitting diode manufacturing method, characterized in that formed in a parallel line pattern or mesh shape. The method of claim 2,
The recess of the concave-convex pattern is a vertical light emitting diode manufacturing method, characterized in that the cross-section is a semicircular shape. The method of claim 2,
The voids are formed in the vertical light emitting diode manufacturing method, characterized in that formed on the upper portion of the uneven pattern. delete The method of claim 4,
The first nitride semiconductor layer is a vertical light emitting diode manufacturing method, characterized in that formed at a temperature of 400 ~ 600 ℃. The method of claim 6,
The second nitride semiconductor layer is a vertical light emitting diode manufacturing method, characterized in that formed at a temperature of 800 ~ 1200 ℃. The method of claim 7,
After removing the sacrificial substrate from the semiconductor layers, removing the remaining portion of the second nitride semiconductor layer. The method of claim 8,
Removing the residues is performed using polishing or etching. The method according to claim 1,
The first nitride semiconductor layer is a vertical light emitting diode manufacturing method, characterized in that formed in 100 ~ 1000nm thickness. The method of claim 10,
The first nitride semiconductor layer is a vertical light emitting diode manufacturing method, characterized in that formed to a thickness covering all the uneven pattern.

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