KR101375185B1 - Method for manufacturing lead frame and method for manufacturing semiconductor package using the same - Google Patents

Abstract

It is an object of the present invention to provide a method of manufacturing a leadframe to simplify the manufacturing process of a semiconductor package. In order to achieve the above object, the present invention provides a method for manufacturing a lead frame comprising a die pad on which a semiconductor chip is mounted, a plurality of lands formed around the die pad, and a plurality of tie bars supporting the plurality of lands. (a) etching a lower portion of the plurality of tie bars to a specific thickness; (b) filling a lower portion of the etched tie bars and the void space between the plurality of lands and the die pad with resin; And (c) provides a method for producing a lead frame comprising the step of removing the plurality of tie bars.

Description

Method for manufacturing lead frame and method for manufacturing semiconductor package using same {Method for manufacturing lead frame and method for manufacturing semiconductor package using the same}

The present invention relates to a lead frame, and more particularly, to a method of manufacturing a lead frame and a method of manufacturing a semiconductor package using the same.

Generally, a leadframe for a semiconductor implements a large number of leads for processing a plurality of signals. However, it is difficult to implement many leads with a limited size of the lead frame. In contrast, multi-row is implemented in the structure of quad flat no leads (QFN). Multirow is to implement a second row in the row immediately behind the first row of lands around the pad. However, in order to manufacture such a lead frame, when three or more rows are connected, lands that are electrically connected by forcing a saw-bar which fixes the lands of each row in the semiconductor manufacturing process are forced to saw. The process of cutting off is needed. For example, in the case of dual-row QFN, in order to saw one unit, a sawing process of the unit and the unit, and a sawing process of the first row and the second row in one unit are additionally required. Done.

In addition, as a method of implementing a lead frame for a semiconductor having a microcircuit using a raw material of a copper single layer, a vertical etching depth control technique along with a horizontal etching technique is absolutely essential. Therefore, in order to manufacture a lead frame having a microcircuit using a laminated material, a total etching process including selective etching of upper copper, selective etching of an intermediate nickel layer, and back etching of the remaining copper layer after molding the semiconductor package is performed. Three steps of etching process are required.

 As described above, the manufacturing process of the lead frame implementing a plurality of conventional leads is not only complicated, but also includes a high cost of the lead frame according to a high manufacturing price, and technical matters that are difficult to solve according to each model.

It is an object of the present invention to provide a method of manufacturing a leadframe to simplify the manufacturing process of a semiconductor package.

Another object of the present invention is to provide a method of manufacturing a semiconductor package, in which the process is simplified.

According to an aspect of the present invention,

A method of manufacturing a lead frame comprising a die pad on which a semiconductor chip is mounted, a plurality of lands formed around the die pad, and a plurality of tie bars supporting the plurality of lands, the method comprising: (a) Etching the lower portion to a specific thickness; (b) filling a lower portion of the etched tie bars and the void space between the plurality of lands and the die pad with resin; And (c) provides a method for producing a lead frame comprising the step of removing the plurality of tie bars.

In order to achieve the above another object, the present invention,

(a) preparing a lead frame manufactured by the manufacturing method of any one of claims 1 to 9; (b) mounting a semiconductor chip on the lead frame; (c) bonding a plurality of lands formed on the semiconductor chip and the lead frame with a plurality of wires; (d) sealing the semiconductor chip, the plurality of lands and the plurality of bonding wires; And (e) the leadframe includes a plurality of leadframe units, and separately separating the plurality of semiconductor packages formed on the leadframe units by sawing the sealed plurality of leadframe units. A method for manufacturing a semiconductor package is provided.

According to the present invention, since the plurality of tie bars are removed in the manufacturing process of the lead frame, the sawing process is greatly shortened in the semiconductor manufacturing process.

Therefore, the manufacturing cost of the semiconductor package is reduced, and the productivity of the semiconductor package is improved.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.

1 to 9 are views for explaining a method of manufacturing a lead frame according to an embodiment of the present invention. A method of manufacturing a lead frame will be described in detail with reference to FIGS. 1 to 9.

Referring to the drawings, a method of manufacturing a leadframe according to the present invention includes a raw material preparation step, a bottom etching step, a filling step, and an upper etching step.

In the first step of preparing the raw material, the raw material of the lead frame 101 shown in FIGS. 1 and 2 is prepared. FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG. 1. 1 and 2, the leadframe 101 includes a plurality of leadframe units, each of which includes a rail 111, a die pad 121, and a plurality of leadframe units. Lands 131, a plurality of tie bars 141, and a plurality of edges 151 are provided. The lead frame 101 is implemented by patterning a metal substrate. The metal substrate may be composed of one of various metals such as copper, nickel and aluminum. In order to pattern the metal substrate, a chemical method such as etching or a mechanical method such as stamping or punching may be used, but the present invention is not limited thereto.

The die pad 121 is where the semiconductor chip 911 of FIG. 10 is mounted during the manufacturing process of the semiconductor package 901 of FIG. 11.

The plurality of lands 131 may also be referred to as leads. The plurality of lands 131 are arranged side by side at regular intervals along the periphery of the die pad 121, and are connected to electrode pads formed on the semiconductor chip (911 of FIG. 10) during the semiconductor manufacturing process. 911 of 10) and an external device to send and receive electrical signals. The plurality of lands 131 are supported by the plurality of tie bars 141.

The plurality of tie bars 141 support the plurality of lands 131 and are supported by the plurality of edges 151.

The rail 111 supports a plurality of leadframe units.

In the second etching step, the lower part of the plurality of tie bars 141 and the plurality of edge parts 151 is etched to a specific thickness, as shown in FIG. 3. That is, half etching is performed to etch only the lower portions of the plurality of tie bars 141 and the plurality of edge portions 151. Here, a multi-row having two or more rows is also designed using a plurality of tie bars 141. Also, the plurality of tie bars 141 are also half-etched to remove the lower part by etching the upper part. The remaining portion of the die supports the plurality of lands 131 and the die pad 121.

In the lower etching step, one or more side holes 115 are formed in the lower portion of the rail 111 as shown in FIG. 4. The side holes 115 are formed by half etching. Resin is injected into the half etched portion of the lead frame through the side holes 151. At this time, the half etching direction of the side holes 115 is formed in the direction of the half etching portion of the plurality of lands 131 because the resin must be injected in the direction in which the half etching is performed on the plurality of lands 131.

In the third step, the filling step, as shown in FIG. 5, the upper and lower portions of the lead frame 101 are placed between the mold tools 511 while being covered with the tapes 521. Resin, that is, an insulating polymer material, is injected into the lower portion of the lead frame 101 through the side hole 115 of FIG. 4. Then, the bottom of the plurality of tie bars (141 of FIG. 3), the bottom of the plurality of rims (151 of FIG. 1), and between the plurality of lands (131 of FIG. 3) and the die pad (121 of FIG. 3) Empty space is filled with resin.

There are many ways to fill the resin, and the method shown in FIG. 5 shows a method of filling the resin using a 2-side tape mold. Referring to FIG. 5, the tapes 521 are placed on both sides of the mold tools 511, and the lead frame 101 is positioned therebetween. Then, the mold tools 511 are closed up and down to completely adhere the upper and lower portions of the lead frame 101 to the tapes 521. In this state, the resin is filled through the side hole (115 in FIG. 4) of the rail (111 in FIG. 4). In this case, the side hole (115 of FIG. 4) may be formed on the rail opposite to the rail (111 of FIG. 4) where the resin is injected so that the resin may be easily injected into the lower part of the lead frame 101. In addition, a vacuum may be used to more easily inject the resin into the lower portion of the lead frame 101. That is, by making the inside of the lead frame 101 into a vacuum, the resin can be easily sucked into the inside of the lead frame 101. Alternatively, by using a low viscosity resin, the resin can be more easily filled into the lead frame 101.

After the resin is filled into the inside of the lead frame 101, the resin is cured. As a method for curing the resin, a method such as thermosetting or UV (UltraViolet) curing may be used. However, in order to implement a rapid continuous process, it is preferable to use a fast cure method using an electron beam. After the resin inside the lead frame 101 is cured, the mold tools 511 are opened to remove the tapes 521 of the upper and lower parts of the lead frame 101. Then, as shown in FIG. 6, the resin does not remain where the tapes 521 are pasted, and the resin is filled only in the half-etched portion and the empty space of the lower part of the lead frame 103.

Accordingly, the shape of the upper and lower portions of the lead frame 103 is different. That is, referring to FIG. 6, the upper part of the lead frame 103 may include a land 131 and a land 131, a plurality of edge parts 151, a die pad 121, and a lead by a plurality of tie bars 141. Although the unit and the unit of the frame are connected, the lower portion of the lead frame 103 is exposed only the plurality of lands 131 and the die pad 121, and the plurality of half-etched edges (151 of FIG. 1) The plurality of tie bars 141 are filled with resin.

Here, surface treatment, that is, plating may be performed on the lead frame 103 for soldering and wire bonding. The plating may be performed before the resin is filled in the lead frame 103, or may be performed after the resin is filled in the lead frame 103. In the present invention, an example in which plating is performed before resin is filled in the lead frame 103 will be described. As shown in FIG. 3, plating is performed for soldering and wire bonding to the lead frame 101 on which the plurality of lands 131 and the lower portions of the plurality of edge parts 151 are etched. For plating, reel to reel type plating is also possible, and plating may be performed in units of units. The plating conditions at this time are AU / NI / Cu material / NI / AU, AU / NI / CU material / AG, SN / CU material / NI / AU, SN / CU material / AG, Au-Ag (or Au-Pd) A combination of / Pd or Pd alloy / Cu material / Ni (or rough Ni) / Pd or Pd alloy / Au-Ag (or Au-Pd) is possible. The plated lead frame (101 in FIG. 1) is filled with resin through various methods. The structure of the lead frame 103 filled with the resin is shown in FIG. 6.

The lead frame formed as described above (103 in FIG. 6) is very easy to handle because of its strength which is much stronger than the raw material of the lead frame (101 in FIG. 1) before the initial etching by hardened resin. In addition, since the plurality of lands 131 of FIG. 6 are fixed by the resin, the role of the plurality of tie bars 141 of FIG. 6 becomes unnecessary. If the plating process is performed after resin filling, a plurality of tie bars (141 of FIG. 6) are required until the plating process is completed. This is because the plurality of tie bars (141 of FIG. 6) may be plated on the upper and lower portions of the plurality of lands (131 of FIG. 6) and the die pad (121 of FIG. 6). If a plurality of tie bars (141 of FIG. 6) do not exist, electroless plating should be performed since plating is impossible due to electrical disconnection. However, electroless plating requires a long plating time because the plating speed is lower than the electroplating and the required plating thickness is high. According to the present invention, electroplating is preferably performed using a plurality of tie bars (141 in FIG. 6), but if necessary, electroless after removal of the plurality of tie bars (141 in FIG. 6) after resin filling. Plating may also be performed. In any case, if plating is performed after resin filling, the plurality of tie bars (141 of FIG. 6) may be removed. If necessary, after removing the plurality of tie bars (141 of FIG. 6), the resin and the copper material, which is a material of the lead frame (103 of FIG. 6), do not show excellent adhesion, and thus the plurality of lands (131 of FIG. 6) are made of resin. You can also exit from. To prevent this, the thickness of the copper or copper + plating layer, the surface roughness information of the copper surface or the plating layer, and the surface chemical information of the copper surface or the plating layer play an important role. To this end, the thickness of the copper or the plating layer may be additionally increased, and a forced surface roughness may be formed on the copper or the plating layer. Moreover, surfactant etc. which can improve the adhesive force with resin can also be previously applied to a copper surface or a plating layer.

In the fourth etching, the upper etching step, a plurality of tie bars, i.e., except the upper part of the lead frame (105 in FIG. 8), that is, the plurality of lands (131 in FIG. 7) and the die pad (121 in FIG. 7) may be used. (141 in FIG. 7), the plurality of edges (151 in FIG. 1) and the rail (111 in FIG. 1) are removed.

Referring to FIG. 7, different masking patterns 711 are applied to upper and lower portions of the lead frames 121, 131, 141, and 611 for etching the upper parts of the lead frames 121, 131, 141, 611. That is, the upper part of the lead frames 121, 131, 141 and 611 is selectively masked, and the lower part of the lead frames 121, 131, 141 and 611 is totally masked. In detail, the upper portions of the lead frames 121, 131, 141, and 611 cover the plurality of lands 131 and the die pad 121 with the mask 711, and the lower portions of the lead frames 121, 131, 141, 611 are covered with the mask 711. In this state, when the upper portions of the lead frames 121, 131, 141, and 611 are etched, as shown in FIGS. 8 and 9, the plurality of tie bars (141 of FIG. 7) and the plurality of edges (151 of FIG. 1) are all etched. And removed. FIG. 8 illustrates a leadframe 105 having a plurality of lands 131 formed in one row, and FIG. 9 illustrates a leadframe 107 having two lands 131, 132 formed in two columns.

As described above, according to the present invention, a process of sawing a plurality of tie bars 141 between the land 131 and the land 131 which is performed in the semiconductor manufacturing process is carried out in the manufacturing process of the lead frame, The etching process can replace the sawing process to be carried out several times.

However, although a portion of the plating layer or the copper surface may be damaged during the etching process, this may serve as a mechanical roughness that may improve adhesion to the polymer material additionally injected during the semiconductor manufacturing process.

10 and 11 are diagrams for describing a method of manufacturing a semiconductor package using the method of manufacturing a lead frame according to FIGS. 1 to 9.

10 and 11, a method of manufacturing a semiconductor package 901 includes a semiconductor chip mounting step, a wire bonding step, a sealing step, and a sawing step.

In the semiconductor chip mounting step, the semiconductor chip 911 is mounted on the die pad 121. At this time, the semiconductor chip 911 is bonded onto the die pad 121 by an adhesive material. Thus, the semiconductor chip 911 is firmly fixed on the die pad 121.

In the wire bonding step, the electrode pads and the plurality of lands 131 and 132 formed on the semiconductor chip 911 are bonded to the wires 921. Therefore, the semiconductor chip 911 is electrically connected to the plurality of lands 131 and 132. More specifically, in the wire bonding step, one end of the metal wire 921, which is a connection member mainly made of gold (Au), is bonded to the electrode pads exposed to the upper surface of the semiconductor chip 911. In addition, the other end of the metal wire 921, which is a connection member extending from the electrode pads of the semiconductor chip 911, is bonded to the tips of the plurality of lands 131 and 132. Accordingly, an interconnection of an electrical signal is formed between the semiconductor chip 911 and the lead frames 121, 131, 132, and 611. In this case, the plating layer formed at the front end of the plurality of lands 131 and 132 forms an end portion of the metal wire 921 and a heat-sealed portion, thereby forming highly reliable contacts.

In the sealing step, the semiconductor chip 911, the plurality of lands 131 and 132, and the plurality of bonding wires 921 are sealed using a molding resin. Accordingly, the semiconductor chip 911, the plurality of lands 131 and 132, and the plurality of bonding wires 921 are protected from the external environment. In the sealing step, the lead frames 121, 131, 132, and 611 on which the semiconductor chips 911 are mounted are accommodated in a resin molding die, and then, for example, an epoxy molding compound (EMC) is injected and curing is performed at an appropriate high temperature. At this time, the semiconductor chip 911 is sealed by the inflow of the molding resin MC covering the entire upper layer except for the bottom of the lead frames 121, 131, 132, and 611, and the semiconductor package 901 is integrated with the semiconductor chip 911 and the lead frames 121, 131, 132, 611. ).

 In the sawing step, the plurality of interconnected semiconductor package units are sawed in the direction of an arrow (FIG. 9) using a sawing apparatus to manufacture individual semiconductor packages 901.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

1 to 9 are views for explaining a method of manufacturing a lead frame according to an embodiment of the present invention.

10 and 11 are diagrams for describing a method of manufacturing a semiconductor package using the method of manufacturing a lead frame according to FIGS. 1 to 9.

Description of the Related Art

101/103/105/107; Leadframe 111; rail

121; Die pads, 131,132; rand

141; Tie bars, 151; Rim

115; Side hole 511; Mold tools

521; Tapes, 611; Resin

901; Semiconductor package 911; Semiconductor chip

921; wire,

Claims (10)

A method for manufacturing a lead frame comprising a die pad on which a semiconductor chip is mounted, a plurality of lands formed around the die pad, and a plurality of tie bars supporting the plurality of lands, (a) etching a lower portion of the plurality of tie bars to a specific thickness; (b) filling a lower portion of the etched tie bars and the void space between the plurality of lands and the die pad with resin; And (c) removing the plurality of tie bars. The method of claim 1, wherein half etching is performed on the bottoms of the plurality of tie bars in half size. delete delete The method of claim 1, wherein the lead frame further comprises a rail for supporting the plurality of tie bars, forming one or more side holes in the lower portion of the rail, and the resin is injected through the one or more side holes Method for producing a lead frame, characterized in that. The method of claim 1, wherein step (b) (b-1) covering the plurality of lands, the die pads, and the front surface of the lower portion of the lead frame with a tape; (b-2) injecting the resin into the lower part of the lead frame; And (b-3) The method of manufacturing a lead frame comprising the step of curing the resin injected into the lower portion of the lead frame. delete delete The method of claim 1, wherein the step (c) comprises masking the plurality of lands and the die pads on the upper part of the lead frame, and etching the plurality of tie bars while masking the entire surface of the lower part of the lead frame. Method for producing a lead frame, characterized in that the removal. Claim 10 has been abandoned due to the setting registration fee. (a) preparing a leadframe manufactured by the method of any one of claims 1, 2, 5, 6 or 9; (b) mounting a semiconductor chip on the lead frame; (c) bonding a plurality of lands formed on the semiconductor chip and the lead frame with a plurality of wires; (d) sealing the semiconductor chip, the plurality of lands and the plurality of bonding wires; And (e) the lead frame includes a plurality of lead frame units, and the semiconductor package includes a step of sawing the sealed plurality of lead frame units to separately separate the plurality of semiconductor packages formed on the lead frame units. Method of preparation.

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