KR101374322B1 - Semiconductor device and method of fabricating the same - Google Patents

Abstract

A method of manufacturing a semiconductor device is provided. A method of manufacturing a semiconductor device includes forming a trench in a semiconductor substrate of a first conductivity type, forming a trench dopant-containing film including a dopant of a second conductivity type on sidewalls and bottom surfaces of the trench, and forming a trench dopant-containing film in the trench. Diffusing the dopant into the semiconductor substrate, and removing the trench dopant containing film.

Description

Semiconductor device and method of manufacturing the same

The present invention relates to a semiconductor device and a manufacturing method thereof.

Semiconductor devices included in various electronic devices, including home appliances, are a major configuration for determining the quality of electronic devices. BACKGROUND With the trend toward larger capacities, multifunctions and / or miniaturization of electronic devices, there is an increasing demand for semiconductor devices having improved reliability and other characteristics. To meet this demand, various techniques for improving the characteristics of semiconductor devices have been introduced.

Double diffused metal oxide semiconductor field effect transistor (DMOS) is a type of semiconductor device and refers to a type of MOSFET (metal oxide semiconductor field effect transistor) using diffusion to form a transistor region, and is a high voltage power integrated circuit Typically used as power transistors for DMOS is a power transistor capable of driving high current and fast switching capability even at low gate voltages.

One technical problem to be solved by the present invention is to provide a highly reliable semiconductor device and a method of manufacturing the same.

Another technical problem to be solved by the present invention is to provide a semiconductor device with a minimized on resistance and a method of manufacturing the same.

Another technical problem to be solved by the present invention is to provide a semiconductor device having a high breakdown voltage and a method of manufacturing the same.

The present invention provides a method for manufacturing a semiconductor device to provide the above technical problem. The method for manufacturing the semiconductor device includes forming a trench in a semiconductor substrate of a first conductivity type, forming a trench dopant-containing film including a dopant of a second conductivity type on sidewalls and bottom surfaces of the trench, and forming the trench. Diffusing a dopant in the dopant-containing film into the semiconductor substrate to form a doped region, and removing the trench dopant-containing film.

The method of manufacturing the semiconductor device includes forming a recessed region in the semiconductor substrate, forming a body dopant-containing spacer including the second conductivity type dopant on the sidewall of the recessed region, and containing the body dopant. The method may further include forming a body region by diffusing a dopant in a spacer into the semiconductor substrate.

The method of manufacturing the semiconductor device may further include removing the body dopant containing spacer, forming a gate insulating film covering the bottom surface and the sidewall of the recess region, and forming a gate electrode filling the recess region. Can be.

Forming the trench includes forming a sub trench in one side of the body region, and forming a main trench by etching a bottom surface of the sub trench, wherein the method of manufacturing the semiconductor device forms the main trench. The method may further include forming a ground region extending into the body region by injecting the dopant of the second conductivity type into the bottom surface of the sub trench.

The concentration of the dopant of the second conductivity type may be higher than that of the body region.

The dopant in the trench dopant containing film may be diffused into the semiconductor substrate by heat treatment.

The method of manufacturing the semiconductor device may further include forming an epitaxial film on the sidewall and the bottom surface of the trench by performing an epitaxial process.

The method of manufacturing the semiconductor device may include forming a source region by injecting a dopant of the first conductivity type into an upper portion of the epitaxial film, an upper portion of the body region, and an upper portion of the ground region, and a lower portion of the semiconductor substrate. The method may further include forming a drain region by implanting the dopant of the first conductivity type into a surface.

The method of manufacturing the semiconductor device may further include forming a gap fill insulating pattern filling the trench after forming the epitaxial layer.

The trench dopant-containing film may include any one of boron silica glass (BSG) or phosphorus silica glass (PSG).

The semiconductor substrate may include a base substrate and an epitaxial substrate on the base substrate, wherein the trench may be formed in the epitaxial substrate.

The doped region may be in contact with the base substrate.

The doped region may be interposed between the base substrate and a portion of the epitaxial substrate so that the doped region does not contact the base substrate.

In order to solve the above technical problem, the present invention provides a method of manufacturing a semiconductor device according to another embodiment. The method of manufacturing the semiconductor device may include forming a first trench in a semiconductor substrate of a first conductivity type, and forming a first trench dopant-containing film including a second conductivity type dopant on sidewalls and bottom surfaces of the first trench. Forming a first doped region by diffusing a dopant in the first trench dopant-containing film into the semiconductor substrate, forming a second trench by etching the bottom surface of the first trench, and forming the second trench. Forming a second trench dopant-containing film including the second conductivity type dopant on sidewalls and bottom of the trench, and diffusing the dopant in the second trench dopant-containing film into the semiconductor substrate to form a second doped region. And removing the second trench dopant-containing film.

The method of manufacturing the semiconductor device may further include forming an epitaxial film on the sidewall and the bottom surface of the second trench by performing an epitaxial process.

The method of manufacturing the semiconductor device may remove the first trench dopant-containing film on the bottom surface of the first trench and form the first trench dopant-containing film on the sidewall of the first trench before forming the second trench. It may further comprise remaining.

The width of the lower region of the second trench may be smaller than the width of the upper region of the second trench.

In order to solve the above technical problem, the present invention provides a semiconductor device. The semiconductor device may include gap fill insulating patterns filling trenches formed in a substrate, a semiconductor pillar defined between the gap fill insulating patterns and doped with a dopant of a first conductivity type, and a gate electrode disposed in a recess region formed in the semiconductor pillar. A doped region formed under the trenches and doped with a dopant of a second conductivity type, and a body region formed in the semiconductor pillar and surrounding a sidewall of the recess region; Doped with a second conductivity type dopant, the width of the upper region of the trenches may be wider than the width of the lower region of the trenches.

Sidewalls of the trenches may have a stepped structure.

The doped region includes a first doped region adjacent to a boundary between the upper region and the lower region of the trenches, and a second doped region except the first doped region, wherein the second conductivity type of the first doped region is The concentration of the dopant may be higher than the concentration of the dopant of the second conductivity type in the second doped region.

According to an exemplary embodiment of the present invention, a trench dopant-containing film including a dopant of a second conductivity type is formed on sidewalls and bottom surfaces of a trench formed in a semiconductor substrate of a first conductivity type, and the dopant in the trench dopant-containing film is formed as described above. The doped region is formed by diffusing into the semiconductor substrate. Accordingly, the concentration of the dopant of the second conductivity type in the doped region is uniform, so that a highly reliable semiconductor device can be implemented.

1A to 1I are diagrams for describing a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
2 is a diagram for describing a method of manufacturing a semiconductor device in accordance with a modification of the first embodiment of the present invention.
3A to 3C are diagrams for describing a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
4 is a diagram for describing a method of manufacturing a semiconductor device in accordance with a modification of the second embodiment of the present invention.
5A to 5F are diagrams for describing a method of manufacturing a semiconductor device according to the third embodiment of the present invention.
6 is a diagram for describing a method of manufacturing a semiconductor device in accordance with a modification of the third embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more readily apparent from the following description of preferred embodiments with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In this specification, when it is mentioned that a film (or layer) is on another film (or layer) or substrate, it may be formed directly on another film (or layer) or substrate, or a third film (Or layer) may be interposed. In the drawings, the sizes and thicknesses of the structures and the like are exaggerated for the sake of clarity. It should also be understood that although the terms first, second, third, etc. have been used in various embodiments herein to describe various regions, films (or layers), etc., It should not be. These terms are merely used to distinguish any given region or film (or layer) from another region or film (or layer). Thus, the membrane referred to as the first membrane in one embodiment may be referred to as the second membrane in another embodiment. Each embodiment described and exemplified herein also includes its complementary embodiment. The expression 'and / or' is used herein to include at least one of the components listed before and after. Portions denoted by like reference numerals denote like elements throughout the specification.

A method of manufacturing a semiconductor device according to a first embodiment of the present invention is described.

1A to 1I are diagrams for describing a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

Referring to FIG. 1A, semiconductor substrates 100 and 102 are provided that include a base substrate 100 and an epitaxial substrate 102 on the base substrate 100. The base substrate 100 may be doped with a dopant of a first conductivity type, and the epitaxial substrate 102 may be formed on the base substrate 100 by performing an epitaxial process. The epitaxial substrate 102 may be doped with the same conductivity type dopant as the base substrate 100. For example, the base substrate 100 and the epitaxial substrate 102 may be doped with an N-type dopant. The semiconductor substrates 100 and 102 may be silicon substrates or germanium substrates.

The semiconductor substrate 100 may include a cell region A and an electrode region B. FIG. A thick oxide film 104 and a nitride film 106 may be formed on the epitaxial substrate 102. Recess regions 108a and 108b may be formed in the cell region A by sequentially etching the nitride layer 106, the thick oxide layer 104, and the epitaxial substrate 102. The nitride layer 106, the thick oxide layer 104, and the epitaxial substrate 102 may be etched by an anisotropic etching process. The base substrate 100 may not be etched. Bottom surfaces of the recess regions 108a and 108b may be formed as the epitaxial substrate 102.

After the recess regions 108a and 108b are formed, an oxide layer may be formed on the inner surfaces of the recess regions 108a and 108b and the oxide layer may be removed by a wet etching method.

Referring to FIG. 1B, a body dopant containing spacer 110 may be formed on sidewalls of the recess regions 108a and 108b. The body dopant-containing spacer 110 may include a dopant of a conductive type different from that of the semiconductor substrates 100 and 102. For example, when the semiconductor substrates 100 and 102 are doped with the first conductivity type dopant, the body dopant-containing spacer 110 may include a second conductivity type dopant. The body dopant-containing spacer 110 may be formed by forming a body dopant-containing film including the second conductive dopant on the semiconductor substrate 100 and 102 and anisotropically etching the body dopant-containing film. As a result, the bottom surfaces of the recessed areas 108a and 108b may be exposed. The body dopant-containing film may be either boron silica glass (BSG) or phosphorus silica glass (PSG) formed using plasma chemical vapor deposition (PECVD).

Referring to FIG. 1C, a heat treatment process may be performed. As a result, the dopants of the second conductivity type that were included in the body dopant-containing spacer 100 may pass through sidewalls of the recess regions 108a and 108b and diffuse into the epitaxial substrate 102. have. A portion of the epitaxial substrate 102 adjacent to sidewalls of the recess regions 108a and 108b may be counter doped with a dopant of the second conductivity type to form a body region 112. The body region 112 may surround sidewalls of the recess regions 108a and 108b.

After the body region 112 is formed, the nitride layer 106 may be removed. Alternatively, the nitride layer 106 may be removed before the first dopant-containing spacer 110 is heat-treated.

Referring to FIG. 1D, the body dopant-containing spacer 110 may be removed. The body dopant-containing spacer 110 may be removed by a wet etching method. After the body dopant-containing spacer 110 is removed, bottom surfaces of the recess regions 108a and 108b may be etched. As a result, the depth of the recess regions 108a and 108b may be deeper. After etching the bottom surfaces of the recess regions 108a and 108b, an oxide layer may be formed on the bottom surfaces and sidewalls of the recess regions 108a and 108b, and the oxide layer may be removed.

First and second gate insulating layers 113a and 113b may be formed on the bottom and sidewalls of the recess regions 108a and 108b. The gate insulating layers 113a and 113b may include a TEOS (Tetra-ethyl-ortho-silicate) oxide film formed by a thermal oxide film and / or a chemical vapor deposition method.

After the gate insulating layers 113a and 113b are formed, a first gate electrode 114a may be formed to fill the first recess region 108a, and a second gate may fill the second recess region 108b. The electrode 114b may be formed. The second gate electrode 114b may include a body portion filling the second recess region 108b and a contact portion extending in a direction parallel to an upper surface of the base substrate 100 at one end of the body portion. . The gate electrodes 114a and 114b may include a conductive material including the dopant of the first conductivity type. For example, the gate electrodes 114a and 114b may include polycrystalline silicon including phosphorous and / or arsenic.

After the gate electrodes 114a and 114b are formed, capping insulating layers 116a and 116b may be formed to cover the gate electrodes 114a and 114b, respectively. The capping insulating layers 116a and 116b may be silicon oxide layers formed by thermal oxidation.

Referring to FIG. 1E, a hard mask layer may be formed on the semiconductor substrates 100 and 102, and the hard mask layer may be patterned to form a hard mask pattern 118. Using the hard mask pattern 118 as an etch mask, the thick oxide layer 104 and the epitaxial substrate 102 may be etched to form sub trenches 120. For example, the sub trenches 120 may be formed between the gate electrodes 114a and 114b, on one side of the first gate electrode 114a, and on the electrode region B. FIG. The one side of the first gate electrode 114a may face the other side of the first gate electrode 114a adjacent to the second gate electrode 114b. The bottom surface of the sub trenches 120 may be located at a level higher than the bottom surfaces of the gate electrodes 114a and 114b based on the top surface of the base substrate 100.

After forming the sub trench 120, the second conductive dopant ions 122 may be implanted using the hard mask pattern 118 as an ion implantation mask. The dopant ions 122 of the second conductivity type may be implanted into the bottom surface of the sub trench 120. Thereafter, the second conductivity type dopant ions 122 implanted into the bottom surface of the sub trench 120 may be diffused to form a ground region 124. The ground region 124 may overlap the body region 112. The concentration of the dopant of the second conductivity type in the ground region 124 may be higher than the concentration of the dopant of the second conductivity type in the body region 112.

Referring to FIG. 1F, the bottom surfaces of the sub trenches 120 may be further etched to form main trenches 121. The bottom surfaces of the sub trenches 120 may be etched by an anisotropic etching process using the hard mask pattern 118 as an etching mask. As a result, the ground region 124 under the bottom surfaces of the sub trenches 120 may be etched to form a ground region 124a divided into both sides of the main trenches 121. Bottom surfaces of the main trenches 121 may be formed of the epitaxial substrate 102.

After the main trenches 121 are formed, a trench dopant containing layer 130 may be formed on the semiconductor substrates 100 and 102. The trench dopant containing layer 130 may include a dopant of the second conductivity type. The trench dopant containing layer 130 is conformally formed on the bottom surfaces and the sidewalls of the main trenches 121 so as to be surrounded by the trench dopant containing layer 130 in the main trenches 121. Empty interior spaces can be defined. The trench dopant containing layer 130 may be either boron silica glass (BSG) or phosphorus silica glass (PSG) formed using plasma chemical vapor deposition (PECVD).

A heat treatment process can be performed. As a result, the dopants of the second conductivity type in the trench dopant containing layer 130 may pass through the sidewalls and the bottom surfaces of the main trenches 121 and may be diffused into the epitaxial substrate 102. have. Portions of the epitaxial substrate 102 adjacent to the sidewalls and bottom surfaces of the main trenches 121 may be counter doped with the dopant of the second conductivity type to form a doped region 132. . The doped region 132 may be in contact with the base substrate 100.

As the dopant of the trench dopant containing layer 130 is diffused to form the doped region 132, the concentration of the dopant of the second conductivity type in the doped region 132 may be uniform. As a result, the turn-on resistance of the semiconductor device is reduced, so that the reliability of the semiconductor device can be improved. If the doped region is formed by the ion implantation method, the concentration of the dopant of the second conductivity type in the doped region may be non-uniform due to the depth of the main trench 121, thereby lowering the reliability of the semiconductor device. Can be. However, as described above, the doped region 132 is formed by forming a trench dopant-containing layer 130 in the main trench 121 and heat-treating the trench dopant-containing layer 130 to thereby form the doped region ( The concentration of the dopant of the second conductivity type in 132 may be uniform.

The concentration of the dopant of the second conductivity type in a portion of the body region 112 adjacent to the sidewalls of the main trenches 121 is a dopant of the second conductivity type in another portion of the body region 112. It may be higher than the concentration of. The concentration of the dopant of the second conductivity type in a portion of the ground region 124a adjacent to the sidewalls of the main trenches 121 is a dopant of the second conductivity type in another portion of the ground region 124a. It may be higher than the concentration of.

Referring to FIG. 1G, after forming the doped region 132, the trench dopant containing layer 130 may be removed. The trench dopant containing layer 130 may be removed by a wet etching method. After the trench dopant-containing layer 130 is removed, gap fill insulating patterns 142a may be formed to fill the internal spaces in the main trenches 121. In example embodiments, sidewalls and bottom surfaces of the gapfill insulating patterns 142a may be in contact with the doped region 132.

The gap fill insulating patterns 142a may form an insulating layer filling the main trenches 121 on the semiconductor substrates 100 and 102, and may etch the insulating layer using the hard mask pattern 118 as an etch stop layer. Can be formed. After the gap fill insulating patterns 142a are formed, the hard mask pattern 118 may be removed.

The semiconductor pillar 144 may be defined between the gap fill insulating patterns 142a adjacent to each other. The semiconductor pillar 144 may be doped with a dopant of the first conductivity type. The semiconductor pillar 144 may be a portion of the epitaxial substrate 102 disposed between the gap fill insulating patterns 142a adjacent to each other.

Referring to FIG. 1H, a mask layer 150 covering the electrode region B may be formed. The mask film 150 may be a photoresist film. The mask layer 150 covers a portion of the second gate electrode 114b adjacent to the electrode region B, the semiconductor pillar 144, the body region 112, the ground region 124a, and The gapfill insulating patterns 142a may not be covered.

The dopant ions of the first conductivity type may be implanted using the mask layer 150 as an ion implantation mask. In this case, the insulating film 104 may be used as a buffer film for implanting the dopant ions of the first conductivity type. Upper portions of the body region 112 and the ground region 124a may be counter-doped with the dopant of the first conductivity type. The dopant ions of the first conductivity type may not be implanted into the body region 112 under the contact portion of the second gate electrode 114b.

Dopant ions of the first conductivity type are implanted into the upper portion of the body region 112, the upper portion of the ground region 124a, and the upper portion of the epitaxial layer 140. A source region 154 doped with a conductive dopant may be formed. The source region 154 may be formed at both sides of upper regions of the main trenches 121. The source region 154 may be formed at both sides of the first gate electrode 114a and at one side of the second gate electrode 114b adjacent to the first gate electrode 114a.

Referring to FIG. 1I, an interlayer insulating layer 160 may be formed on the semiconductor substrates 100 and 102. A first wiring 162 in contact with the source region 154, a second wiring 164 in contact with the second gate electrode 114b, and a third wiring 166 on the electrode region B are formed. Can be. The first to third wirings 162, 164, and 166 may be formed by patterning the interlayer insulating layer 160 and the buffer insulating layer 104 to form a portion of the source region 154 and the gap fill insulating patterns. Forming openings exposing a top surface of 142a and a portion of the contact portion of the second gate electrode 114b, removing upper portions of the gap fill insulating patterns 142a, the openings and the gap fill The method may include forming a conductive film filling an upper region of the trench 121 from which the insulating patterns 142a have been removed, and patterning the conductive film. The conductive film may include a metal.

A drain region 168 doped with the first conductivity type dopant may be formed on a lower surface of the base substrate 100. The drain region 168 may be formed by implanting the dopant of the first conductivity type into the bottom surface of the base substrate 100. The bottom surface of the base substrate 100 may face the top surface of the base substrate 100 in contact with the epitaxial substrate 102.

A semiconductor device formed according to the method of manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIG. 1I.

Referring to FIG. 1I, semiconductor substrates 100 and 102 including a cell region A and an electrode region B are provided. The semiconductor substrates 100 and 102 may include a first conductive base substrate 100 and a first conductive epitaxial substrate 102 disposed on the base substrate 100.

A plurality of trenches 121 may be disposed in the epitaxial substrate 102. Each of the trenches 121 may be filled with gap fill insulating patterns 142a. According to an embodiment, the gap fill insulating patterns 142a may fill the inside of the trenches 121. Thus, the gap fill insulating patterns 142a may be in contact with inner surfaces of the trenches 121. The semiconductor pillar 144 may be defined between the gap fill insulating patterns 142a adjacent to each other. The semiconductor pillar 144 may be a portion of the epitaxial substrate 102 interposed between the gap fill insulating patterns 142a adjacent to each other.

Recess regions 108a and 108b may be formed in the epitaxial substrate 102 on one side of the trenches 121. For example, the recess regions 108a and 108b may include a first recess region 108a formed in the semiconductor pillar 144 defined by the gap fill insulating patterns 142a, and the electrode region B. The second recess region 108b may be formed at one side of the trench 121 adjacent to the trench 121. The bottom surfaces of the recessed regions 108a and 108b may be located at a level higher than the bottom surfaces of the trenches 121 based on the top surface of the base substrate 100.

The first gate insulating layer 113a covers the bottom and side surfaces of the first recessed region 108a, and the first gate electrode 114a covers the first gate insulating layer 113a in the first recessed region 108a. You can fill the inner space surrounded by). The second gate insulating layer 113b covers the bottom and side surfaces of the second recessed region 108b, and the second gate electrode 114b is the second gate insulating layer 113b in the second recessed region 108b. You can fill the inner space surrounded by). The second gate electrode 114b may include a body portion filling the second recess region 108b and a contact portion extending in parallel with an upper surface of the base substrate 100 at one end of the body portion. An upper surface of the first gate electrode 114a and a contact portion of the second gate electrode 114b may be covered with first and second capping insulating layers 116a and 116b, respectively.

The body region 112 may surround sidewalls of the recess regions 108a and 108b. The body region 112 may surround upper portions of the sidewalls of the recess regions 108a and 108b. Lower portions and bottom surfaces of the sidewalls of the recess regions 108a and 108b may be formed of the epitaxial substrate 102. The body region 112 may be a portion of the epitaxial substrate 102 adjacent to the upper portions of the sidewalls of the recess regions 108a and 108b by counter doping with a dopant of the second conductivity type. have.

The ground region 124a may surround the upper portion of the sidewall of the trench 121. The ground region 124a may be a portion in which the epitaxial substrate 102 adjacent to the upper portion of the sidewall of the trench 121 is counter doped with a dopant of the second conductivity type. The concentration of the dopant of the second conductivity type in the ground region 124a may be higher than the concentrations of the dopant of the second conductivity type in the body region 112.

A doped region 132 may be formed under the inner surface of the trench 121. In the doped region 132, a portion of the epitaxial substrate 102 adjacent to the bottom surface of the trench 121 and the remaining portion except the upper portion of the sidewall is counter-doped with the dopant of the second conductivity type. It may have been. The doped region 132 formed under the bottom surface of the trench 121 may contact the base substrate 100. The concentration of the dopant of the second conductivity type in the doped region 132 may be lower than the concentration of the dopant of the second conductivity type in the ground region 124a. According to an embodiment, the doped region 132 may be in direct contact with the gapfill insulating patterns 142a.

A source region 154 may be disposed in the epitaxial substrate 102 on both sides of the trenches 121. The source region 154 may be disposed between the first recessed region 108a and the trenches 121. The source region 154 may be a top portion of the body region 112 adjacent to the top surface of the epitaxial substrate 102 and a top portion of the ground region 124a doped with a dopant of the first conductivity type. Can be.

A drain region 168 doped with a dopant of the first conductivity type may be disposed on a bottom surface of the base substrate 100. The drain region 168 may be formed by implanting dopant ions of the first conductivity type into the bottom surface of the base substrate 100.

The first wiring 162, the interlayer insulating layer 160, and the second layer penetrating the thick oxide film 104 and the interlayer insulating layer 160 formed on the epitaxial substrate 102 to contact the source region 154. The second wiring 164 penetrating the capping insulating layer 116b and contacting the second gate electrode 114b, and the third wiring 166 on the interlayer insulating layer 160 of the electrode region B may be disposed. Can be.

According to the first embodiment of the present invention described above, the doped region 132 under the bottom surface of the trench 121 is in contact with the base substrate 100. On the contrary, according to the modified example of the first embodiment of the present invention, the doped region may not be in contact with the base substrate 100. This will be described with reference to FIG. 2.

2 is a diagram for describing a semiconductor device according to a modification of the first embodiment of the present invention.

Referring to FIG. 2, the semiconductor device according to the modified example of the first embodiment of the present invention is similar to the semiconductor device described with reference to FIG. 1I. However, the doped region 132a formed under the bottom surface of the trench 121 may not contact the upper surface of the base substrate 100. As a result, the semiconductor pillar 144 and the epitaxial substrate 102 may be connected to each other.

Unlike the method of manufacturing the semiconductor device according to the first embodiment of the present invention described above, an epitaxial layer may be formed between the trench and the gap fill insulating pattern. This will be described with reference to FIGS. 3A and 3B.

3A and 3B are diagrams for describing a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention. The semiconductor device according to the present exemplary embodiments may include all the contents described with reference to FIGS. 1A to 1F in the above-described exemplary embodiment.

Referring to FIG. 3A, after the doped region 132 is formed, the trench dopant containing layer 130 may be removed. The trench dopant containing layer 130 may be removed by a wet etching method. After the trench dopant-containing layer 130 is removed, an epitaxial process may be performed to form an epitaxial layer 140 on the bottom surfaces and the sidewalls of the main trenches 121. The epitaxial layer 140 is conformally formed on inner surfaces of the main trenches 121 to define empty internal spaces surrounded by the epitaxial layer 140 in the main trenches 121. Can be. The epitaxial layer 140 may be doped with a dopant of the second conductivity type. In contrast, the epitaxial layer 140 may not be doped with the dopant of the second conductivity type.

Gap fill insulation patterns 142 may be formed to fill the internal spaces in the main trenches 121. The gapfill insulating patterns 142 may be formed by the same method as forming the gapfill insulating patterns 142a in the above-described first embodiment.

The semiconductor pillar 144 may be defined between the gap fill insulating patterns 142 adjacent to each other. The semiconductor pillar 144 may be doped with a dopant of the first conductivity type. The semiconductor pillar 144 may be a portion of the epitaxial substrate 102 disposed between the gap fill insulating patterns 142 adjacent to each other.

Referring to FIG. 3B, a mask layer 150 covering the electrode region B may be formed. The mask layer 150 covers a portion of the second gate electrode 114b adjacent to the electrode region B, and the semiconductor pillar 144, the body region 112, the ground region 124a, and the The epitaxial layer 140 and the gap fill insulating patterns 142 may not be covered.

The dopant ions of the first conductivity type may be implanted using the mask layer 150 as an ion implantation mask. In this case, the insulating film 104 may be used as a buffer film for implanting the dopant ions of the first conductivity type. Upper portions of the body region 112 and the ground region 124a may be counter-doped with the dopant of the first conductivity type. The dopant ions of the first conductivity type may not be implanted into the body region 112 under the contact portion of the second gate electrode 114b.

Dopant ions of the first conductivity type are implanted into the upper portion of the body region 112, the upper portion of the ground region 124a, and the upper portion of the epitaxial layer 140. A source region 154 doped with a conductive dopant may be formed. The source region 154 may be formed at both sides of upper regions of the main trenches 121. The source region 154 may be formed at both sides of the first gate electrode 114a and at one side of the second gate electrode 114b adjacent to the first gate electrode 114a.

Referring to FIG. 3C, an interlayer insulating layer 160 may be formed on the semiconductor substrates 100 and 102. A first wiring 162 in contact with the source region 154, a second wiring 164 in contact with the second gate electrode 114b, and a third wiring 166 on the electrode region B are formed. Can be. Forming the first to third wirings 162, 164, and 166 may be formed by the same method as described in the above-described first embodiment. The first to third wires 162, 164, and 166 may include metal.

A drain region 168 doped with the first conductivity type dopant may be formed on a lower surface of the base substrate 100. The drain region 168 may have the same shape as that described in the above-described first embodiment, and may be formed by the same method.

A semiconductor device formed according to the method of manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to FIG. 3C.

Referring to FIG. 3C, semiconductor substrates 100 and 102 including a cell region A and an electrode region B are provided. The semiconductor substrates 100 and 102 may include a first conductive base substrate 100 and a first conductive epitaxial substrate 102 disposed on the base substrate 100.

A plurality of trenches 121 may be disposed in the epitaxial substrate 102. Each of the trenches 121 may be filled with an epitaxial layer 140 and gap fill insulating patterns 142. The epitaxial layer 140 covers bottom surfaces and sidewalls of the trenches 121, and the gapfill insulating patterns 142 are surrounded by the epitaxial layer 140 in the trenches 121. You can fill the spaces. The semiconductor pillar 144 may be defined between the gap fill insulating patterns 142 adjacent to each other. The semiconductor pillar 144 may be a portion of the epitaxial substrate 102 interposed between the gap fill insulating patterns 142 adjacent to each other.

Recess regions 108a and 108b may be disposed in the epitaxial substrate 102 on one side of the trenches 121. The recess regions 108a and 108b may include all of the details described above in the first embodiment.

The first gate insulating layer 113a covers the bottom and side surfaces of the first recessed region 108a, and the first gate electrode 114a covers the first gate insulating layer 113a in the first recessed region 108a. You can fill the inner space surrounded by). The second gate insulating layer 113b covers the bottom and side surfaces of the second recessed region 108b, and the second gate electrode 114b is the second gate insulating layer 113b in the second recessed region 108b. You can fill the inner space surrounded by). The second gate electrode 114b may have the same shape as described above in the first embodiment. An upper surface of the first gate electrode 114a and a contact portion of the second gate electrode 114b may be covered with first and second capping insulating layers 116a and 116b, respectively.

The body region 112 may surround sidewalls of the recess regions 108a and 108b. The ground area 124a may be disposed to surround the upper portion of the sidewall of the trench 121. The body region 112 and the ground region 124a may include the same shape and / or the same characteristic as described in the first embodiment.

The doped region 132 may be disposed under the inner surface of the trench 121. The doped region 132 may include the same shape and / or the same characteristics as described in the first embodiment.

A source region 154 may be disposed in the epitaxial substrate 102 on both sides of the trenches 121. The source region 154 may be disposed between the first recessed region 108a and the trenches 121. The source region 154 is adjacent to the upper surface of the epitaxial substrate 102, the upper portion of the epitaxial film 140, the upper portion of the body region 112, and the upper portion of the ground region 124a. It may be doped with a dopant of the first conductivity type.

A drain region 168 doped with a dopant of the first conductivity type may be disposed on a bottom surface of the base substrate 100. The drain region 168 may be formed by implanting dopant ions of the first conductivity type into the bottom surface of the base substrate 100.

The first wiring 162, the interlayer insulating layer 160, and the second layer penetrating the thick oxide film 104 and the interlayer insulating layer 160 formed on the epitaxial substrate 102 to contact the source region 154. The second wiring 164 penetrating the capping insulating layer 116b and contacting the second gate electrode 114b, and the third wiring 166 on the interlayer insulating layer 160 of the electrode region B may be disposed. Can be.

According to the present embodiment, the doped region 132 under the bottom surface of the trench 121 is in contact with the base substrate 100. On the contrary, according to the modified example of the present embodiment, the doped region may not contact the base substrate 100. This will be described with reference to FIG. 4.

4 is a diagram for describing a semiconductor device according to a modification of the second embodiment of the present invention.

Referring to FIG. 4, the semiconductor device according to the modified example of the first embodiment of the present invention is similar to the semiconductor device described with reference to FIG. 3C. However, the doped region 132a formed under the bottom surface of the trench 121 may not contact the upper surface of the base substrate 100. As a result, the semiconductor pillar 144 and the epitaxial substrate 102 may be connected to each other.

Unlike the manufacturing method of the semiconductor device according to the first and second embodiments of the present invention described above, the trench may be formed by a plurality of etching processes. This will be described with reference to FIGS. 5A to 5F.

5A to 5F are diagrams for describing a method of manufacturing a semiconductor device according to the third embodiment of the present invention. The semiconductor device according to the present exemplary embodiments may include all the contents described with reference to FIGS. 1A to 1F in the above-described exemplary embodiment.

Referring to FIG. 5A, the first trenches 120a may be formed by etching the bottom surfaces of the sub trenches 120. The bottom surfaces of the sub trenches 120 may be etched using the hard mask pattern 118 as an etch mask until the epitaxial substrate 102 is exposed by an anisotropic etching process. Thus, bottom surfaces of the first main trenches 120a may be formed as the epitaxial substrate 102. While etching the sea surfaces of the sub trenches 120, the ground region 124 under the bottom surfaces of the sub trenches 120 is etched, such that the ground region 124a is formed in the first main trench. It may be divided into both sides of the field (120a).

After the first main trenches 120a are formed, a first trench dopant containing layer 131 may be formed on the semiconductor substrates 100 and 102. The first trench dopant containing layer 131 may include a second conductivity type dopant. The first trench dopant containing layer 131 is conformally formed on the bottom surfaces and the sidewalls of the first main trenches 120a to form the first trenches 120a in the first trenches 120a. Empty internal spaces surrounded by the dopant containing layer 131 may be defined. The first trench dopant containing layer 131 may be formed using the same material and the same method as the trench dopant containing layer 130 described with reference to FIG. 1F.

A heat treatment process can be performed. As a result, the dopants of the second conductivity type in the first trench dopant-containing film 131 pass through the bottom surfaces and the sidewalls of the first main trenches 120a, thereby forming the epitaxial substrate 102. Can spread to. As a result, a portion of the epitaxial substrate 102 adjacent to the bottom surfaces and the sidewalls of the first main trenches 120a is counter-doped with the dopant of the second conductivity type to form the first doped region 133. ) May be formed, and the concentration of the dopant of the second conductivity type in the portion of the ground region 124a and the portion of the body region 112 adjacent to the sidewalls of the first main trenches 120a Can increase.

Referring to FIG. 5B, the first trench dopant-containing film 131 is anisotropically etched to remove the first trench dopant-containing film 131 on the bottom surfaces of the first main trenches 120a. The first trench dopant containing layer 131 on the sidewalls of the first main trenches 120a may remain. By using the hard mask pattern 118 and the remaining first trench dopant containing layer 131 as an etch stop layer, the bottom surfaces of the first main trenches 120a are etched to form second main trenches. 120b may be formed. As a result, the first doped region 133 under the bottom surfaces of the first main trenches 120a may be removed. Bottom surfaces of the second main trenches 120b may be formed as the epitaxial substrate 102.

Each of the second main trenches 120b may include an upper region 120U and a lower region 120L. The width W1 of the upper regions 120U of the second main trenches 120b may be wider than the width W2 of the lower regions 120L of the second main trenches 120b. The upper regions 120U of the second main trenches 120b may be regions in which the remaining first trench dopant containing layer 131 is disposed on sidewalls of the second main trenches 120b. .

Referring to FIG. 5C, a second trench dopant containing layer 135 may be formed on the semiconductor substrates 100 and 102. The second trench dopant containing layer 135 may include a second conductivity type dopant. The second trench dopant containing layer 135 is conformally formed on the bottom surfaces and the sidewalls of the second main trenches 120b to form the second trenches in the second main trenches 120b. Empty internal spaces surrounded by the dopant containing layer 135 may be defined. The second trench dopant containing layer 135 may be formed using the same material and the same method as the first trench dopant containing layer 131 described with reference to FIG. 3A.

The second trench dopant containing layer 135 may be heat treated. As a result, the dopants of the second conductivity type in the second trench dopant containing layer 135 may be diffused to the sidewalls and the bottom surfaces of the second main trenches 120b. Portions of the epitaxial substrate 102 adjacent the sidewalls and bottom surfaces of the second main trenches 120b are counter-doped to form a second doped region 137 doped with a dopant of the second conductivity type. ) May be formed. The second doped region 137 under the bottom surfaces of the second main trenches 120b may contact the base substrate 100. The second conductivity type dopant in the second trench dopant containing layer 135 is diffused into the first doped region 133 so that the concentration of the second conductivity type dopant in the first doped region 133 is The second doped region 137 may be higher than the concentration of the dopant of the second conductivity type.

Referring to FIG. 5D, the second trench dopant containing layer 135 and the remaining first trench dopant containing layer 131 may be removed. The second trench dopant containing layer 135 and the remaining first trench dopant containing layer 131 may be removed by a wet etching method.

An epitaxial process may be performed to form an epitaxial layer 141 on the bottom surfaces and sidewalls of the second main trenches 120b. The epitaxial layer 141 is conformally formed on the inner surface of the second main trench 120b and is vacant inside surrounded by the epitaxial layer 141 in the second main trenches 120b. You can define spaces. The epitaxial layer 141 may be doped with a dopant of the second conductivity type. Alternatively, the epitaxial layer 141 may not be doped with the dopant of the second conductivity type.

Gap fill insulation patterns 143 may be formed to fill the internal spaces of the second main trenches 120b. A width of a lower portion of the gap fill insulating pattern 143 filling the lower region of the second main trench 120b is an upper portion of the gap fill insulating pattern 143 filling the upper region of the second main trench 120b. It may be narrower than the width of. The gapfill insulating patterns 143 may be formed in the same manner as the method of forming the gapfill insulating patterns 142 described with reference to FIG. 3A in the above-described second embodiment. Unlike shown, according to an embodiment, the epitaxial layer 141 may be omitted. In this case, the gapfill insulating patterns 143 may be in direct contact with the second doped region 137.

The semiconductor pillar 145 may be defined between the gapfill insulating patterns 143 adjacent to each other. The semiconductor pillar 145 may be doped with a dopant of the first conductivity type. The semiconductor pillar 145 may be a portion of the epitaxial substrate 102 disposed between the gap fill insulating patterns 143 adjacent to each other.

Referring to FIG. 5E, a mask layer 151 covering the electrode region B may be formed. The mask layer 151 may be a photoresist layer. The mask layer 151 covers a portion of the second gate electrode 114b adjacent to the electrode region B, and the semiconductor pillar 144, the body region 112, the ground region 124a, and the The epitaxial layer 141 and the gap fill insulating patterns 143 may not be covered.

The dopant ions 152 of the first conductivity type may be implanted using the mask layer 151 as an ion implantation mask. In this case, the insulating film 104 may be used as a buffer film for implanting the dopant ions of the first conductivity type. Upper portions of the body region 112 and the ground region 124a may be counter-doped with the dopant of the first conductivity type. The dopant ions of the first conductivity type may not be implanted into the body region 112 under the contact portion of the second gate electrode 114b.

The dopant ions 152 of the first conductivity type are implanted into the upper portion of the body region 112, the upper portion of the ground region 124a, and the upper portion of the epitaxial layer 141. A source region 155 doped with a conductive dopant may be formed. The source region 155 may be formed at both sides of an upper region of the second main trench 120b. The source region 155 may be formed at both sides of the first gate electrode 114a and at one side of the second gate electrode 114b adjacent to the first gate electrode 114a.

Referring to FIG. 5F, an interlayer insulating layer 161 may be formed on the semiconductor substrates 100 and 102. The first wiring 162, the interlayer insulating layer 160, and the second capping insulating layer 116b penetrate through the thick oxide layer 104 and the interlayer insulating layer 160 to contact the source region 154. A second wiring 164 in contact with the second gate electrode 114b and a third wiring 166 on the interlayer insulating layer 160 of the electrode region B may be formed. The first to third wirings 162, 164, and 166 are the same as the method of forming the first to third wirings 162, 164, and 166 described with reference to FIG. 1I in the above-described first embodiment. It can be formed as.

A semiconductor device formed according to the method of manufacturing a semiconductor device according to the third embodiment of the present invention will be described with reference to FIG. 5F.

Referring to FIG. 5F, semiconductor substrates 100 and 102 including a cell region A and an electrode region B are provided. The semiconductor substrates 100 and 102 may include a base substrate 100 of a first conductivity type and an epitaxial substrate 102 of the first conductivity type, which are sequentially stacked.

A plurality of trenches 120b may be formed in the epitaxial substrate 102. Each of the trenches 120b may be filled with an epitaxial layer 141 and gap fill insulating patterns 143. The epitaxial layer 141 covers the bottom surfaces and sidewalls of the trenches 120b, and the gapfill insulating patterns 143 are surrounded by the epitaxial layer 141 in the trenches 120b. You can fill the spaces.

Each of the trenches 120b may include a lower region having a first width and an upper region having a first width greater than the first width. The epitaxial film 141 may have a substantially uniform thickness. Accordingly, the widths of the lower portions of the gap fill insulating patterns 143 filling the lower regions of the trenches 120b may correspond to the gap fill insulating patterns 143 filling the upper regions of the trenches 120b. It may be narrower than the width of the top of the).

The semiconductor pillar 145 may be defined between the gap fill insulating patterns 143 adjacent to each other. The semiconductor pillar 144 may be a portion of the epitaxial substrate 102 interposed between the gap fill insulating patterns 143 adjacent to each other.

Recess regions 108a and 108b may be formed in the epitaxial substrate 102 on one side of the trenches 120b. For example, the recess regions 108a and 108b may include a first recess region 108a formed in the semiconductor pillar 114 and a second region formed on one side of the trench 120b adjacent to the electrode region B. FIG. It may include a recess region 108b. The bottom surfaces of the recessed regions 108a and 108b may be located at a level higher than the bottom surfaces of the trenches 120b based on the top surface of the base substrate 100.

The gate insulating layers 113a 113b and the gate electrodes 114a and 114b may fill the recess regions 108a and 108b as described with reference to FIG. 1I in the above-described first embodiment. As described with reference to FIG. 1I in the above-described first embodiment, the second gate electrode 114b may include a body portion and a contact portion, and the capping insulating layers 116a and 116b may include the gate electrodes 114a, 114b).

The body region 112 may surround sidewalls of the recess regions 108a and 108b. The body region 112 surrounds upper portions of the sidewalls of the recess regions 108a and 108b, and lower portions and bottom surfaces of the sidewalls of the recess regions 108a and 108b are epitaxial. Earl substrate 102 may be formed. The body region 112 may be counter-doped with a portion of the epitaxial substrate 102 adjacent to the sidewalls of the recess regions 108a and 108b with the dopant of the second conductivity type.

A ground region 124a may surround sidewalls of the upper region of the trench 120b. A portion of the epitaxial substrate 102 adjacent to the sidewall of the trench 120b and the upper region may be counter-doped with the dopant of the second conductivity type. The concentration of the dopant of the second conductivity type in the ground region 124a may be higher than the concentrations of the dopant of the second conductivity type in the body region 112.

First and second doped regions 133 and 137 may be formed under the inner surface of the trench 120b. The first doped region 133 may be counter-doped with a portion of the epitaxial substrate 102 adjacent to a boundary between the upper region and the lower region of the trench 120b with the dopant of the second conductivity type. have. The second doped region 137 may be a counter-doped portion of the epitaxial substrate 102 adjacent to the bottom and sidewalls of the lower region of the trench 120b with the dopant of the second conductivity type. .

The second doped region 137 below the bottom surface of the trench 120b may contact the base substrate 100. The concentration of the second conductivity type dopant in the first doped region 133 may be higher than that of the second conductivity type dopant in the second doped region 137. The concentration of the second conductivity type dopant in the doped regions 133 and 137 may be lower than that of the second conductivity type dopant in the ground region 124a.

A source region 155 may be disposed in the epitaxial substrate 102 on both sides of the trenches 120b. The source region 155 may be disposed between the first recessed region 108a and the trenches 120b. The source region 154 is adjacent to an upper surface of the epitaxial substrate 102, an upper portion of the epitaxial film 141, an upper portion of the body region 112, and an upper portion of the ground region 124a. It may be doped with a dopant of the first conductivity type.

A drain region 168 doped with a dopant of the first conductivity type may be disposed on a bottom surface of the base substrate 100. The drain region 168 may be formed by implanting dopant ions of the first conductivity type into the bottom surface of the base substrate 100.

The first wiring 162, the interlayer insulating layer 161, and the second layer penetrating the thick oxide film 104 and the interlayer insulating layer 161 formed on the epitaxial substrate 102 to contact the source region 155. The second wiring 164 penetrating the capping insulating layer 116b and contacting the second gate electrode 114b, and the third wiring 166 on the interlayer insulating layer 160 of the electrode region B may be disposed. Can be.

According to the present embodiment described above, the first doped region 137 under the bottom surface of the trench 120b is in contact with the base substrate 100. On the contrary, according to the modified example of the present embodiment, the doped region may not contact the base substrate 100. This will be described with reference to FIG. 6.

6 is a diagram for describing a semiconductor device according to a modification of the third embodiment of the present invention.

Referring to FIG. 6, a semiconductor device according to a modified example of the third embodiment of the present invention is similar to the semiconductor device described with reference to FIG. 5F. However, the second doped region 137a formed under the bottom surface of the trench 120b may not contact the top surface of the base substrate 100. As a result, the semiconductor pillar 145 and the epitaxial substrate 102 may be connected to each other.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

100: base substrate
102: epitaxial substrate
104: thick oxide film
106: nitride film
108a, 108b: recessed areas
110: dopant containing spacer
112: body area
113a and 113b: gate insulating films
114a and 114b: gate electrodes
116a and 116b: capping insulating films
118: hard mask pattern
120: sub trench
120a: first main trenches
120b: second main trenches
120U: upper region
120L: lower region
121: trench
124: ground zone
130: trench dopant-containing film
132: doped region
142, 142a, 143: gap fill insulation patterns
154: source region
162, 164, and 166: first to third wires

Claims (20)

Forming a trench in the first conductive semiconductor substrate;
Forming a trench dopant-containing film including a dopant of a second conductivity type on sidewalls and bottom surfaces of the trench;
Diffusing a dopant in the trench dopant containing film into the semiconductor substrate to form a doped region;
Removing the trench dopant containing film; And
And performing an epitaxial process to form an epitaxial film on the sidewalls and the bottom surface of the trench. The method according to claim 1,
Forming a recessed region in the semiconductor substrate;
Forming a body dopant containing spacer on the sidewall of the recess region, the body dopant containing spacer of the second conductivity type;
And diffusing a dopant in the body dopant-containing spacer into the semiconductor substrate to form a body region. The method of claim 2,
Removing the body dopant containing spacer;
Forming a gate insulating film covering a bottom surface and a sidewall of the recess region;
Forming a gate electrode filling the recess region. The method of claim 2,
Forming the trench includes forming a sub trench in one side of the body region, and forming a main trench by etching the bottom surface of the sub trench,
And forming a ground region extending into the body region by injecting a dopant of the second conductivity type into the bottom surface of the sub trench before forming the main trench. 5. The method of claim 4,
And a concentration of the dopant of the second conductivity type is higher than that of the body region. The method according to claim 1,
And the dopant in the trench dopant-containing film diffuses into the semiconductor substrate by heat treatment. delete 5. The method of claim 4,
Implanting a dopant of the first conductivity type into an upper portion of the epitaxial film, an upper portion of the body region, and an upper portion of the ground region to form a source region; And
And injecting a dopant of the first conductivity type into a lower surface of the semiconductor substrate to form a drain region. The method according to claim 1,
And forming a gap fill insulating pattern filling the trench after forming the epitaxial film. The method according to claim 1,
The trench dopant containing film may include any one of boron silica glass (BSG) or phosphorus silica glass (PSG). The method according to claim 1,
The semiconductor substrate includes a base substrate and an epitaxial substrate on the base substrate,
And the trench is formed in the epitaxial substrate. 12. The method of claim 11,
And the doped region is in contact with the base substrate. 12. The method of claim 11,
And wherein the doped region is interposed between the base substrate and a portion of the epitaxial substrate so that the doped region does not contact the base substrate. Forming a first trench in the first conductivity type semiconductor substrate;
Forming a first trench dopant-containing film including a second conductivity type dopant on sidewalls and bottom surfaces of the first trenches;
Diffusing a dopant in the first trench dopant-containing film to the semiconductor substrate to form a first doped region;
Etching the bottom surface of the first trench to form a second trench;
Forming a second trench dopant-containing film including the second conductivity type dopant on sidewalls and bottom surfaces of the second trench;
Diffusing a dopant in the second trench dopant-containing film to the semiconductor substrate to form a second doped region; And
And removing the second trench dopant-containing film. 15. The method of claim 14,
Performing an epitaxial process to form an epitaxial film on the sidewalls and the bottom surface of the second trench. 15. The method of claim 14,
Before forming the second trench,
Removing the first trench dopant-containing film on the bottom surface of the first trench, and leaving the first trench dopant-containing film on the sidewall of the first trench. 17. The method of claim 16,
The width of the lower region of the second trench is narrower than the width of the upper region of the second trench. Gapfill insulating patterns filling trenches formed in the substrate;
A semiconductor pillar defined between the gap fill insulating patterns and doped with a dopant of a first conductivity type;
A gate electrode disposed in a recessed region formed in the semiconductor pillar;
A doped region formed under the trenches and doped with a dopant of a second conductivity type;
A body region formed in the semiconductor pillar and surrounding a sidewall of the recess region;
The body region is doped with a dopant of the second conductivity type,
The width of the upper region of the trench is wider than the width of the lower region of the trench. 19. The method of claim 18,
The sidewalls of the trench has a stepped structure. 19. The method of claim 18,
The doped region includes a first doped region adjacent to a boundary between the upper region and the lower region of the trenches, and a second doped region except the first doped region,
The concentration of the dopant of the second conductivity type in the first doped region is higher than the concentration of the dopant of the second conductivity type in the second doped region.

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