KR101346941B1 - flat panel display device and manufacturing method thereof - Google Patents

Abstract

According to an aspect of the present invention, there is provided a flat panel display including: a pixel area capable of displaying an image and a pad area provided at an edge of the pixel area; A plurality of pad lines provided in the pad area and formed at a predetermined distance apart from each other; And an insulating film covering the pad line and having at least one isolation hole in the separation region.

Accordingly, the flat panel display device of the present invention can reduce the defective line occurrence rate of the flat panel display device generated by the defective pad pattern by providing an isolation hole in the pad area, and also by forming the isolation hole in the spaced area. The step of repairing the defective pad pattern can be reduced. By forming the isolation hole, there is an effect of reducing the outflow due to the bad pad pattern.

Description

Flat panel display device and manufacturing method

1 is a plan view of a conventional liquid crystal display device.

2 is an enlarged view of a region A '.

3A and 3B illustrate line defects occurring in a conventional pad area.

4 is a plan view showing a flat panel display device according to the present invention.

5 is an enlarged view of area A of FIG. 4;

6 is a cross-sectional view taken along line II ′, II-II ′, and III-III ′ of FIG. 5.

7A to 7F are flowcharts illustrating a method of manufacturing a flat panel display device according to the present invention.

Description of the Related Art

   1: liquid crystal display 5: pixel area

  10: substrate 20: gate line

  30: first insulating film 40: channel layer

  50: data line 70: second insulating film

  75 passivation 90 pixel electrode

 105: pad area 120: gate pad line

120a: bad pad pattern 150: data pad line

 175: pad hole 190: pad electrode

 200: isolation hole

The present invention relates to a liquid crystal display device and a method for manufacturing the same, which can prevent pad line defects by forming isolation holes in the pad region.

As semiconductor products are miniaturized and highly integrated, interest in patterning techniques for forming patterns is increasing. Lithography for patterning has been developed as a core technology of semiconductor manufacturing.

1 is a plan view of a conventional liquid crystal display, and FIG. 2 is an enlarged view of a region A '.

As shown in FIG. 1, the liquid crystal display device 1 includes a pixel area 505 capable of displaying an image and a pad area 605 that transmits a signal to the pixel area 505.

The pixel region 505 includes a plurality of thin film transistors that can serve as circuit lines and switching roles.

The pad region 605 includes a plurality of pad lines 620 and 650 that are connected to a plurality of circuit lines of the pixel region 505 and transmit signals to the circuit lines.

Pad electrodes 690 are provided at end portions of the pad lines 620 and 650 so that the test and control signals of the liquid crystal display 501 can be applied later.

As shown in an enlarged view of the pad region 605 shown in FIG. 2, the pad region 605 includes a plurality of pad lines 620 and 650 and pad electrodes 690 provided at ends of the pad lines 620 and 650. Is formed.

In the pixel region 505, a plurality of gate lines 520 and data lines 550 are provided as circuit lines. A thin film transistor is provided in an area where the gate line 520 and the data line 550 cross each other.

In this case, an autoprobe test is performed to determine whether the pattern of the gate line 520, the data line 550, and the thin film transistor, which are circuit lines of the pixel region 505, is good or bad.

Thus, the inspection equipment contacts the pad electrode 690 with the equipment to transmit a signal under the same condition in the liquid crystal display device 501 and checks whether the device is defective or good.

The autoprobe device is a device for inspecting the subpixels of the pixel area 505. In other words, each of the pixels is a device for checking whether driving is good.

Therefore, when the equipment is used, defects such as circuit lines and thin film transistors in the pixel region 505 can be confirmed. However, the failure of the pad line and the like can be inferred and checked.

That is, the defects generated in the pixel region 505 may be checked to determine defects such as pixels provided in the pixel region 505. Here, the lines connected to the defective pixel are checked.

In addition, a plurality of pixels provided in the pixel area 505 may be checked to find and repair a defect. However, if the defect is not generated in the pixel, the defect may be a defect in the pad lines 620 and 650 formed in the pad area 605.

Here, since the autoprobe equipment is a device for inspecting a defect of the pixel region 505, the defect inspection of the pad lines 620 and 650 is cumbersome to detect the defect with the naked eye of an operator.

Therefore, since the defect of the pad area 605 has to be inspected by a person using a microscope or the like, it takes a lot of work time to detect the defect.

In addition, the minute pad lines 620 and 650 may be difficult to visually identify the defective area due to the fact that a person needs to directly identify the defective area along the line of the pixel.

That is, since the defects occurring in the pad lines 620 and 650 are to be detected by the human eye, the defect detection operation is inefficient and it is difficult to detect the defects.

For this reason, the liquid crystal display device 501, which can be shipped as a good product only by repair, can be determined as a defective product and discarded, which may cause an increase in defects.

3A and 3B illustrate line defects occurring in a conventional pad area.

As shown in FIGS. 3A and 3B, the gate pad line 620 connected to the gate line 620 of the pad lines 620 and 650 will be described with reference to a cited example.

The pad region 605 is connected to the circuit line of the pixel region 505, and the circuit line is connected to the gate line 520 and the data line 550.

The gate line 520 is formed on the substrate 510, and the gate insulating layer 530 is formed on the gate line 520.

In this case, a channel layer formed on the gate electrode 525 integrally formed on the gate line 520 and a source / drain electrode integrally formed with the data line may be formed on the pixel region 505 to form a thin film transistor. .

A passivation layer 570 is formed on the thin film transistor to protect the thin film transistor and the data line.

In this case, since the thin film transistor is not formed in the gate pad region 605a, a passivation layer 570 is formed on the gate insulating layer 530.

The protective layer may be etched to form a transparent conductive layer connected to the gate pad line 620 to form a pad electrode 690.

3A, when the pad line 620 is formed, the gate metal material is etched to pattern the shape of the pad line 620.

However, when the pad line 620 is patterned or the like, the pad line 620 may be subjected to a mask process or the like, and line defects may occur in the process of remaining photoresist and gate metal material.

That is, the pad lines 620 should be formed to be spaced apart at predetermined intervals, but a bad pad line 620a in which the pad lines 620 are connected to each other may occur.

As described above, the bad pad line 620a formed by connecting the pad line 620 to the adjacent pad line 620 may cause an image defect in the liquid crystal display 501.

As shown in FIG. 3B, in order to form the pad electrode 690, a transparent conductive material is deposited to form a transparent conductive film, and the transparent conductive film is etched through a mask process to pattern the transparent conductive film.

Here, the shape of the pad line 620 may be patterned through a process such as etching the transparent conductive material. The pad electrode 690 may be connected to the adjacent pad electrode 690 due to a poor etching process or a poor photoresist residue.

The bad pad electrode 690a having the pad electrode 690 and the pad line 620 connected to an adjacent line is a pixel area 505 that displays an image by applying a bad signal to the pixel area 505. It is possible to cause a defect.

In addition, a defect in which the pad line 620 and the pad electrode 690 are connected to an adjacent line may be difficult to detect in an inspection step.

That is, a failure in connecting the pad line 620 and the pad electrode 690 may be difficult to detect by an autoprobe device. Since the autoprobe device is a device for inspecting the pixel region 505, a defect of the pixel region 505 can be detected, but a defect of the pad region 105 can be difficult to detect. Therefore, in order to detect the defect, the defect can be detected and confirmed directly by the naked eye of the operator to repair the defect.

As such, when a line defect occurs in which the pad line 620 generated in the pad region 605 is connected to an adjacent line, it may be difficult to detect the line defect.

In addition, since the worker has to visually check the defective line to detect the line defect, a problem that requires a lot of detection work time may occur.

The present invention provides a pad line spaced at a predetermined interval in the pad area and a separation hole in the spaced area, thereby reducing the work inspection time due to the bad pad pattern and reducing the defective rate caused by the bad. It is an object to provide a display device.

In addition, the isolation hole may be formed in a process of forming a pass hole and a pixel electrode, and thus another object of the present invention is to provide a method for manufacturing a flat panel display device which can reduce line defects caused by the bad pad pattern without an additional process.

According to an aspect of the present invention, there is provided a flat panel display device including: a pixel area capable of displaying an image and a pad area provided at an edge of the pixel area; A plurality of pad lines provided in the pad area and formed at a predetermined distance apart from each other; And an insulating film covering the pad line and having at least one isolation hole in the separation region.

As a means for achieving the present invention, a method of manufacturing a flat panel display device according to the present invention comprises the steps of preparing a substrate; Forming a gate pad line in the gate pad region and a gate line in the pixel region on the substrate; Forming a first insulating film on the entire surface of the substrate; Forming a data pad line in a data pad area and a data line in a pixel area on the first insulating layer; Forming a second insulating film on the entire surface of the substrate; Forming a pass hole formed through the second insulating layer through the pixel region, a pad hole formed through the second insulating layer in the pad region, and an isolation hole formed between the pad holes; Forming a transparent conductive film on an entire surface of the substrate on which the pad hole, the pass hole, and the isolation hole are formed; Etching the transparent conductive film to form a pixel electrode in a pixel region and a pad electrode in the pad region.

Hereinafter, a flat panel display and a method of manufacturing the same according to the accompanying drawings will be described in detail with reference to the following examples, and those skilled in the art can implement many other embodiments using the teachings of the present invention. It is noted that the flat panel display device and its manufacturing method are for illustrative purposes and are not limited to the following embodiments.

The present invention relates to a shape (pattern) of a pad area which can prevent a phenomenon in which a pad line formed in the pad area is shorted.

4 is a plan view illustrating a flat panel display device according to an exemplary embodiment of the present invention.

In the present invention, a representative liquid crystal display among flat panel displays is described as an embodiment.

As shown in FIG. 4, the liquid crystal display device 1 is a flat panel display device that can display an image by forming a liquid crystal layer between two substrates to drive a liquid crystal of the liquid crystal layer.

The liquid crystal display device 1 includes a pixel area 5 capable of displaying an image and a pad area 105 that transmits a signal for controlling the pixel area 5.

The pad region 105 is provided with a plurality of isolation holes 200 to isolate the plurality of pad lines 120 and 150 from the pad lines 120 and 150.

The pad lines 120 and 150 are formed in plural with a predetermined distance. In addition, an isolation hole 200 is provided in an area of the separation distance. That is, an isolation hole 200 is provided in an area between the pad lines 120 and 150 and the adjacent pad lines 120 and 150 to prevent the pad lines 120 and 150 from shorting.

5 is an enlarged view of region A of FIG. 4, and FIG. 6 is a cross-sectional view taken along lines II ′, II-II ′, and III-III ′ of FIG. 5.

As shown in the enlarged view of FIG. 5, a plurality of lines are provided in the pixel region 5 and the pad region 105.

In the pixel region 5, a switching element is formed in an area where the gate line 20 and the data line 50 cross each other. As such, the pixel electrode 70 of the transparent conductive film is formed in an area where the gate line 20 and the data line 50 cross each other to form a subpixel.

The data line 50 and the gate line 20 are connected to pad lines 120 and 150 formed in the pad region 105, respectively.

The pad region 105 may include a gate pad region 105a having a gate pad line 120 connected to the gate line 20, and a data pad having a data pad line 150 connected to the data line 50. The area 105b is provided.

Gate / data pad electrodes 190a and 190b connected to a control circuit for applying a control signal to the gate / data pad lines 120 and 150 are formed at each end of the gate / data pad lines 120 and 150. It is. The pad electrodes 190a and 190b are hereinafter referred to as the pad electrode 190 by combining the date pad electrode 190b and the gate pad electrode 190a.

The pad electrode 190 is formed to cover the pad lines 120 and 150. Since the pad lines 120 and 150 may be exposed to the outside, the pad lines 120 and 150 may be formed of oxides such as ITO and IZO to protect the pad lines 120 and 150 from foreign matter or moisture.

The pad lines 120 and 150 may be spaced apart from each other by a predetermined interval. In addition, the spaced apart gap area is provided with an isolation hole 200 that insulates each of the pad lines 120 and 150.

The isolation hole 200 may be prevented from being connected to an adjacent pad line. In other words, the pad lines 120 and 150 have a tendency that the pitch of the pad lines 120 and 150 is gradually narrowed due to high resolution. For this reason, a short may occur between the pad lines 120 and 150 due to the fine pattern in the process of forming the pad lines 120 and 150.

Accordingly, the isolation hole 200 may be provided in a narrow pitch (separation interval) area of the pad lines 120 and 150 to prevent a short from the adjacent pad lines 120 and 150.

As shown in FIG. 6, in the pixel region 5, the switching element TR is formed in an area where the gate line 20 and the data line 50 cross each other.

The switching element TR is formed on the substrate 10 to correspond to the region of the first insulating layer 30 and the gate electrode 25 on the gate electrode 25 formed integrally with the gate line 20. A layer 40, a source electrode 50a integrally formed with the data line 50, and a drain electrode 50b formed spaced apart from the source electrode 50a by a predetermined distance are provided.

Here, a second insulating film 70 that protects the switching element TR is formed on the entire surface of the substrate 10, and a pass hole 75 is formed in a predetermined region of the second insulating film 70 to drain the electrode 50b. ) And the pixel electrode 90 can be formed.

On the other hand, the pad region 105 includes a gate pad region 105a on which the gate pad line 120 is formed and a data pad region 150b on which the data pad line 150 is formed.

The gate pad line 120 is connected to the gate line 20, and the data pad line 150 is connected to the data line 50.

The first insulating layer 30 is formed on the gate pad line 120 in the gate pad region 105a, and the second insulating layer 70 is formed on the first insulating layer 30.

The gate pad line 120 may include a gate pad electrode 190 at an end of the gate pad line 120 to transmit a signal such as a control signal to the switching element TR. The gate pad electrode 190 penetrates the first insulating layer 30 and the second insulating layer 70 to connect the gate pad electrode 190 to be connected to an end of the gate pad line 120.

The data pad line 150 is formed on the first insulating layer 30. The data pad line 150 is connected to the data line 50, but since the data line 50 is formed on the first insulating layer 30, the data pad line 150 may be formed on the same layer. The second insulating layer 70 is formed on the data pad line 150.

In addition, the data pad electrode 190 is connected to the data pad line 150 by drilling the second insulating layer 70.

The gate pad line 120 and the data pad line 150 may provide an isolation hole 200 in a spaced area P spaced apart from an adjacent line.

The isolation hole 200 may prevent a short from occurring between the pad lines 120 and 150 formed at a fine pitch (separation area P).

As such, by providing the isolation hole 200 in the separation area P, which is a distance between the pad lines 120 and 150, the pad line 120 and 150 may be prevented from shorting. .

Therefore, it is possible to prevent line defects generated in the pad region 105 and to reduce the time for repairing the line defects.

7A to 7F are flowcharts illustrating a method of manufacturing a flat panel display device according to the present invention. Here, the pixel region and the gate pad region will be described for ease of understanding and explanation.

As illustrated in FIG. 7A, a gate electrode 25 integrally formed with the gate line 20 may be formed on the substrate 10 in the pixel region 5.

The gate pad line 120 may be formed simultaneously with the gate line 20 in the gate pad region 105.

The gate line 20 and the gate pad line 120 may be formed at a predetermined interval at a predetermined distance. Herein, the distance from which the pad line is spaced is defined as a separation area P. FIG. The gate pad line 120 and the gate line 20 are later connected.

The gate pad line 120 may be shorted between adjacent gate pad lines 120 by forming a fine pattern such as a fine pitch in the process of forming the pad line by a photomask method. That is, as shown in the figure, the bad pad pattern 120a may be formed.

The pattern formed later on the gate line 20 and the like may be formed using a photomask.

Briefly describing the photomask method, after forming the substrate layer by sputtering, chemical vapor deposition, etc., the photoresist is coated on the substrate layer. The photoresist is exposed and etched using a mask having a predetermined pattern to form a photoresist pattern. The substrate layer is etched using the photoresist pattern as a protective film.

When the photoresist pattern is stripped, the substrate layer may be etched to form patterns such as the gate line 20 and the data line 50.

As shown in FIG. 7B, the first insulating layer 30 may be formed on the entire surface of the substrate 10 on which the gate line 20 and the gate pad line 120 are formed.

A source / drain electrode 50a is formed in the pixel region 5 to form the channel layer 40 on the gate electrode 25 to form the switching element TR and partially overlap the channel layer 40. , 50b). The source electrode 50a may be integrally formed with the data line 50.

Meanwhile, a data pad line 150 connected to the data line 50 may be formed in the data pad region 105b. 6, the data line 50, the source / drain electrodes 50a and 50b, and the data pad line 150 may be formed by a photomask method.

As such, the switching element TR may be formed in the pixel region 5. The data pad line 150 may be formed on the first insulating layer 30 in the data pad region 105b (not shown). Like the gate pad line 120, the data pad line 150 also does not etch in the process of forming the pad line, or an undesired bad pad due to the photoresist remaining in the process of forming a pattern with the photoresist. The pattern 120a may be formed.

As illustrated in FIG. 7C, a plurality of lines are formed by forming a second insulating layer 70 on the entire surface of the substrate 10 on which the switching element TR and the gate pad line 120 formed in the pixel region 5 are formed. The plurality of switching elements TR are protected. The second insulating layer 70 may be formed of an organic layer or the like.

As shown in FIG. 7D, a pass hole 75 for connecting the pixel electrode 90 may be formed on the drain electrode 50b.

The pass hole 75 may be formed using a mask. Here, when forming the pass hole 75, a pad hole 175 may be simultaneously formed in the pad region 105.

In addition, the isolation hole 200 may be simultaneously formed in the spaced area P of the pad line 120.

As such, when the second insulating layer 70 of the pixel region 5 is etched to form the pass hole 75, the drain electrode 50b may be exposed from the second insulating layer 70.

When the pad hole 175 is formed in the pad region 105, the gate pad line 120 may be exposed from the second insulating layer 70 and the first insulating layer 30.

In addition, the defective pad pattern 120a may be exposed from the second insulating layer 70 and the first insulating layer 30 by forming the isolation hole 200 in the separation area P. FIG.

As shown in FIG. 7E, transparent conduction is formed on the entire surface of the substrate 10 on which the pass hole 75, the pad hole 175 of the pad area 105, and the isolation hole 200 are formed. A film 90a is deposited.

The transparent conductive film 90a may be formed of a transparent and conductive material such as ITO, IZO, or the like.

As illustrated in FIG. 7F, the transparent conductive film 90a may be etched using a photomask method to form the pixel electrode 90 and the pad electrode 190.

In order to form the pad electrode 190 and the pixel electrode 90, an pattern may be formed using an etchant. Thus, the transparent conductive film 90a formed in the isolation hole 200 may be etched because it is exposed to the etchant.

In addition, the defective pad pattern 120a formed in the isolation hole 200 may also be exposed by being exposed to the etchant.

That is, the defective pad pattern 120a may be etched by forming the isolation hole 200 in the separation area P. FIG. As a result, the defective pad pattern 120a that may be formed in the pad region 105 may be reduced in the process.

As described above, in the process of forming the liquid crystal display of the present invention, the isolation hole 200 may be formed in the separation area P to etch the defective pad pattern 120a without an additional process.

Accordingly, it is possible to reduce the occurrence rate of the defective line of the liquid crystal display device 1 generated by the defective pad pattern 120a and to form the isolation hole 200 in the separation area P. Repairing the pad pattern 120a can be reduced.

Therefore, the work time for inspecting the bad pad pattern 120a can be reduced, and the time for repairing the bad pad pattern 120a can be reduced. That is, by forming the isolation hole 200, it is possible to reduce the defect outflow due to the failure pad pattern 120a.

As described above, the flat panel display device of the present invention can provide isolation holes in the pad area to reduce the defective line occurrence rate of the flat panel display device generated by the defective pad pattern, and also form the isolation holes in the spaced area. As a result, the repairing of the defective pad pattern may be reduced.

Therefore, the work time for inspecting the bad pad pattern can be reduced, and the time for repairing the bad pad pattern can be reduced. That is, by forming the isolation hole has an effect that can reduce the outflow caused by the failure pad pattern.

In addition, when the isolation hole and the pixel electrode are formed at the same time in the pixel region, the isolation pad pattern can be reduced without additional processing.

Those skilled in the art through the above description will be capable of various changes and modifications without departing from the spirit of the present invention.

Claims (7)

A pixel area capable of displaying an image and a pad area provided at an edge of the pixel area; A plurality of pad lines provided in the pad area and having a spaced area spaced at a predetermined interval; And An insulating film covering the pad line and having at least one isolation hole in the separation region; A bad pad pattern for electrically connecting the pad lines is formed between pad lines formed at a predetermined interval, and the isolation hole electrically separates the pad lines by removing a part of the bad pad pattern. . The method according to claim 1, And the pad line is connected to a plurality of circuit lines provided in the pixel area. The method according to claim 1, And a pad electrode capable of receiving a signal at an end of the pad line. Providing a substrate; Forming a gate line simultaneously with the gate pad line in the gate pad line and the defective gate pad pattern for electrically connecting the gate pad line adjacent to each other with the gate pad region on the substrate; Forming a first insulating film on the entire surface of the substrate; Simultaneously forming a data pad line adjacent to each other in the data pad area on the first insulating layer, and a data line in the defective data pad pattern and pixel area electrically connecting the adjacent data pad lines to the data pad line; Forming a second insulating film on the entire surface of the substrate; Forming a pass hole formed through the second insulating layer through the pixel region, a pad hole formed through the second insulating layer through the pad region, and an isolation hole formed between the pad hole; Forming a transparent conductive film on an entire surface of the substrate on which the pad hole, the pass hole, and the isolation hole are formed; And Etching the transparent conductive film to form a pixel electrode, a gate pad electrode and a data pad electrode in the gate pad region and the data pad region in a pixel region; And the isolation hole electrically separates the pad lines by removing portions of the bad gate pad pattern and the bad data pad pattern. 5. The method of claim 4, And forming a source / drain electrode on the first insulating layer, the source / drain electrodes being formed simultaneously with the channel layer and the data line. 6. The method of claim 5, And the pass hole is formed in a region corresponding to the drain electrode. 5. The method of claim 4, And the pad hole is formed in an area corresponding to the gate pad electrode and the data pad electrode.

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