KR101341060B1 - Display Substrate And Method of Fabricating The Same And Liquid Crystal Display Apparatus Having The Same - Google Patents

Abstract

A sustain electrode formed over the first and second regions on a substrate having a pixel region divided into a first region and a second region, a transparent insulating layer pattern formed on the sustain electrode, and the first and second portions on the transparent insulating layer pattern A display substrate including first and second pixel electrodes respectively formed in a second area, a method of manufacturing the same, and a liquid crystal display device having the same are provided. A recess is formed in either one of the first and second pixel electrodes, or the opening is formed in the transparent insulating layer pattern including a first opening formed in a first region on the sustain electrode and a second opening formed in a second region. . Electrical shorting of the first and second pixel electrodes in the manufacturing process may be prevented by the recess or opening.

Description

Display Substrate And Method Of Fabricating The Same And Liquid Crystal Display Apparatus Having The Same}

The present invention relates to a display substrate, a method for manufacturing the same, and a liquid crystal display device having the same. More particularly, the present invention relates to a display substrate, a method for manufacturing the same, and a method for manufacturing the same, and a liquid crystal display device having the same. It is about.

In general, a display device for displaying an image, such as a liquid crystal display, a plasma display, and an organic light emitting display, includes a substrate. A plurality of pixel areas is defined on the substrate. The pixel area represents a minimum unit for displaying an image, and the plurality of pixel areas are defined to be distinguished from each other in each display device.

Each pixel area has the same structure, and one pixel area includes a pixel electrode to which a voltage corresponding to an image to be displayed is applied. The pixel electrode is formed by depositing a transparent conductive film on the substrate and then patterning the transparent conductive film. Interlayers such as an insulating film may be interposed between the substrate and the pixel electrode. When the intermediate film is not flat and a step is formed on the surface, the step may cause a defect in which the pixel electrode is formed differently from the first designed. Can be.

An object of the present invention is to provide a display substrate that can prevent a process error.

Another object of the present invention is to provide a method of manufacturing the display substrate.

Another object of the present invention is to provide a liquid crystal display device which can display a high quality image by using the display substrate.

The display substrate according to the exemplary embodiment of the present invention includes a storage electrode, a transparent insulating layer pattern, and first and second pixel electrodes. The sustain electrode is formed over the first and second regions on a substrate having a first region and a second region. The transparent insulating layer pattern is formed to cover the substrate on the storage electrode, and has an opening in a region where the storage electrode is formed. The first and second pixel electrodes are formed on the transparent insulating layer pattern and are positioned in the first and second regions, respectively. At least one of the first and second pixel electrodes is formed with at least one recess on an area where the sustain electrode is formed.

In another exemplary embodiment, the display substrate includes a storage electrode, a transparent insulating layer pattern, and first and second pixel electrodes. The sustain electrode is formed over the first and second regions on a substrate having a first region and a second region. The transparent insulating film pattern is formed on the storage electrode, and has a first opening on the storage electrode of the first region and a second opening on the storage electrode of the second region. The first and second pixel electrodes are formed on the transparent insulating layer pattern and are positioned in the first and second regions, respectively.

A method of manufacturing a display substrate according to an embodiment of the present invention includes the following process. On the substrate having the first region and the second region, a sustain electrode positioned over the first and second regions is formed. A gate electrode is formed on the substrate to be spaced apart from the sustain electrode, and a source electrode and a drain electrode are spaced apart from each other on the gate electrode. A transparent insulating layer pattern having an opening is formed on the source electrode and the drain electrode in a region where the sustain electrode is formed. A first pixel electrode and a second pixel electrode are formed in the first and second regions on the transparent insulating film pattern, respectively. At least one of the first and second pixel electrodes is formed with at least one recess on an area where the sustain electrode is formed.

A method of manufacturing a display substrate according to another embodiment of the present invention includes the following process. On the substrate having the first region and the second region, a sustain electrode positioned over the first and second regions is formed. A gate electrode is formed on the substrate to be spaced apart from the sustain electrode, and a source electrode and a drain electrode are spaced apart from each other on the gate electrode. A transparent insulating film pattern having a first opening on the sustain electrode of the first region and a second opening on the sustain electrode of the second region is formed on the source electrode and the drain electrode. A first pixel electrode and a second pixel electrode are formed in the first and second regions on the transparent insulating film pattern, respectively.

The liquid crystal display according to the exemplary embodiment of the present invention includes a first substrate and a second substrate, a liquid crystal layer, a sustain electrode, a transparent insulating layer pattern, a pixel electrode, and a common electrode. The first and second substrates face each other. The liquid crystal layer is interposed between the first and second substrates and the liquid crystals are arranged. The sustain electrode is formed on the first substrate. The transparent insulating layer pattern is formed on the sustain electrode and is opened in a region where the sustain electrode is formed. The pixel electrode is formed on the transparent insulating film pattern. The common electrode is formed on the second substrate and has direction control means for controlling the arrangement direction of the liquid crystal. The direction control means is located at an edge of the sustain electrode, and is formed in a pair parallel to the longitudinal direction of the sustain electrode and symmetrical to each other.

According to the exemplary embodiments of the present invention, an operation characteristic of the display device may be improved by forming pixel electrodes separated from each other. In addition, in the process of forming the divided pixel electrodes, there is an effect that can prevent them from being electrically shorted to each other due to a process error.

1A is a plan view of a display substrate according to an exemplary embodiment of the present invention.
FIG. 1B is a cross-sectional view taken along the line II ′ of FIG. 1A.
FIG. 1C is a cross-sectional view taken along the line II-II 'of FIG. 1A.
2A through 2D are cross-sectional views illustrating a process of manufacturing the display substrate of FIG. 1C.
3A is a plan view of a display substrate according to another exemplary embodiment of the present invention.
FIG. 3B is a cross sectional view taken along line III-III ′ of FIG. 3A.
4A through 4G are cross-sectional views illustrating a method of manufacturing the display substrate of FIG. 3B.
5 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.
6 is an equivalent circuit diagram of two subpixels of a liquid crystal display according to an exemplary embodiment of the present invention.
7 is an equivalent circuit diagram of one pixel of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.
8 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.
9 to 11 are cross-sectional views of the liquid crystal panel assembly shown in FIG. 4 taken along the lines IV-IV 'V-V' and VI-VI ', respectively.
FIG. 12 is a layout view of a pixel electrode and a common electrode of the liquid crystal panel assembly shown in FIG. 4.
13A to 13C are plan views of the electrode pieces serving as the basis of the respective subpixel electrodes shown in FIG. 12.
14 is a layout view illustrating a part of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.
15 is a layout view illustrating a portion of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein, but may be applied in various forms and modified. Rather, the embodiments described below are provided so that the technical idea disclosed by the present invention will be more clearly understood and the technical idea of the present invention will be fully conveyed to those skilled in the art having the average knowledge in the field of the present invention. Therefore, the scope of the present invention should not be construed as being limited by the above-described embodiments. It should also be noted that, in the Figures shown together with the following examples, the sizes of the layers and regions are simplified or somewhat exaggerated to emphasize a clear description, wherein like reference numerals designate like elements.

1A is a plan view of a display substrate according to an exemplary embodiment of the present invention.

Referring to FIG. 1A, a substrate 1 having a first area A1 and a second area A2 is provided. The storage electrode 20 and the pixel electrode 60 are formed on the substrate 1. The storage electrode 20 is formed over the first area A1 and the second area A2.

The pixel electrode 60 is spaced apart from each other and includes a first pixel electrode 61 and a second pixel electrode 62 positioned in the first area A1 and the second area A2, respectively. The pixel electrode 60 corresponds to the pixel area which is the minimum unit in which an image is displayed. The first and second pixel electrodes 61 and 62 may belong to different pixel areas or may belong to the same pixel area. When belonging to different pixel areas, different voltages corresponding to different image information are applied to the first and second pixel electrodes 61 and 62, respectively. When belonging to the same pixel area, different voltages are applied to the first and second pixel electrodes 61 and 62 so as to correspond to the same image information but to complement each other to display a high quality image.

When the longitudinal direction of the storage electrode 20 is referred to as the first direction D1, the pixel electrode 60 is inclined with respect to the first direction D1 and bent in the symmetrical second and third directions D2 and D3. Is formed. At the boundary between the first area A1 and the second area A1, the first pixel electrode 61 has a convex side convex in the first direction D1 and the second pixel electrode 62 corresponds to the convex side. The concave side is concave in the first direction D1. In the concave side of the second pixel electrode 62, recesses 70 concave in the first direction D1 are formed. The recesses 70 are formed in pairs facing each other at the edge of the sustain electrode 20.

Here, the first pixel electrode 61 may have a concave side on which the recessed part 70 is formed, and the second pixel electrode 62 may have a convex side. In addition, it is sufficient that at least one recess 70 is formed on the sustain electrode 20, and there is no limitation according to the shape or number thereof. However, in the case where the display substrate of this embodiment is used in the liquid crystal display device, it is advantageous for the arrangement control of the liquid crystal to form a pair of recesses 70 at the edge of the sustain electrode 20. Details thereof will be described later with reference to embodiments of the liquid crystal display.

FIG. 1B is a cross-sectional view taken along the line II ′ of FIG. 1A.

Referring to FIG. 1B, an insulating film is formed on the storage electrode 20. The insulating layer is formed of a double layer, and the lower layer layer is formed of a transparent inorganic layer 25 covering the sustain electrode 20. The upper layer film is formed of a transparent organic film 45 patterned to have an opening 50 on the sustain electrode 20. The pixel electrode 60 is formed on the organic layer 45.

FIG. 1C is a cross-sectional view taken along the line II-II 'of FIG. 1A.

The first pixel electrode 61 and the second pixel electrode 62 are spaced apart from each other on the storage electrode 20, and the spaced interval is further increased by the recessed part 70. As described above, since the gap is increased by the recessed part 70, the first and second pixel electrodes 61 and 62 may be prevented from being electrically shorted to each other when the pixel electrode 60 is formed. Details of these effects will be described below with reference to the manufacturing method of the display substrate having the above structure.

2A through 2D are cross-sectional views illustrating a process of manufacturing the display substrate of FIG. 1C.

Referring to FIG. 2A, the storage electrode 20 is formed on the substrate 1. The sustain electrode 20 is formed by depositing a copper, aluminum, silver, or chromium-based metal or an alloy thereof to form a conductive film, and then etching the conductive film.

An inorganic film 25 is formed on the sustain electrode 20. The inorganic film 25 is formed of, for example, a silicon nitride film so as to cover the entire surface of the substrate 1 by using plasma chemical vapor deposition. The organic film 45 is formed on the inorganic insulating film 25. The organic film 45 is formed to have an opening 50 by, for example, applying an acrylic resin and then patterning the resin.

Referring to FIG. 2B, a transparent conductive film 60 ′ is formed on the organic layer 45. The transparent conductive film 60 ′ may be formed by sputtering zinc indium oxide or tin indium oxide. In this case, the transparent conductive film 60 'is formed to have a uniform thickness, but the surface height is not constant due to the step in the region where the opening 50 is formed.

The photosensitive film 80 'is apply | coated on the transparent conductive film 60'. The photoresist film 80 'is applied by a spin coating method. In this case, the photoresist film 80' is formed to be generally flat regardless of the height of the surface of the transparent conductive film 60 ', so that the thickness is not constant for each region.

Exposure to the photosensitive film 80 'proceeds. In the case where the photosensitive film 80 'is of a positive type, the photosensitive film 80' of a region corresponding to a portion to be removed from the transparent conductive film 60 'is exposed. In the exposed area, the intensity of light reaching the photosensitive film 80 '(indicated by an arrow) is constant, whereas the thickness of the photosensitive film 80' in the corresponding area is not constant. Therefore, light may not reach the bottom surface of the photoresist 80 'in the exposed region, in a region where the photoresist 80' is thick.

For example, the path through which light should reach the region where the organic layer 45 is formed corresponds to 'L1', and the path through which the light reaches through the region where the opening 50 is formed becomes 'L2' longer than 'L1'. .

Referring to FIG. 2C, an exposed portion of the photoresist film 80 ′ is removed by development to form a photoresist pattern 80. By the photosensitive film pattern 80, a part of the sustain electrode 20 and the transparent conductive film 60 ′ formed adjacent thereto are exposed.

The dotted line in FIG. 2C shows a portion where the light may not reach during exposure and may remain partially different from the photosensitive film 80 '.

Referring to FIG. 2D, the pixel electrode 60 including the first and second pixel electrodes 61 and 62 spaced apart from each other by etching the transparent conductive layer 60 ′ using the photoresist pattern 80 as an etching mask. Is formed. A recess 70 is formed during the etching, and a gap between the first and second pixel electrodes 61 and 62 is widened to form the recess 70.

The dotted line in FIG. 2D indicates a portion where the transparent conductive film 80 ′ may remain due to remaining partially different from the set photosensitive film 80 ′ because the light does not reach during exposure. The above portion overlaps with the region in which the recess 70 is formed. From this, it can be seen that when the recessed part 70 is not formed, the first and second pixel electrodes 61 and 62 may be connected to each other and electrically shorted. That is, when the pixel electrode 60 is formed, the recess 70 blocks a short circuit between the first and second pixel electrodes 61 and 62 to prevent a process defect.

3A is a plan view of a display substrate according to another exemplary embodiment of the present invention.

Referring to FIG. 3A, a substrate 1, a gate line 10, a data line 40, thin film transistors T1 and T2, and a pixel electrode 60 are provided. The gate line 10 and the data line 40 cross each other on the substrate 1 and are formed in plural. A plurality of pixel areas PA is defined while the plurality of gate lines 10 and the data lines 40 cross each other. Since each of the plurality of pixel areas PA has the same structure, the following description will be made based on one pixel area PA.

The pixel area PA is divided into a first area PA1 and a second area PA2, and the pixel electrode 60 corresponds to the first area PA1 and the second area PA2 so that the pixel electrode 60 is the first pixel electrode 61 and the second pixel electrode 62. It includes. The first pixel electrode 61 is positioned in the first area PA1, and the second pixel electrode 62 is positioned apart from the first pixel electrode 61 in the second area PA2. A predetermined region of the first pixel electrode 61 is cut, and the pixel electrode 60 is formed by the cutout pattern 65 by a spaced interval between the cut portion and the first and second pixel electrodes 61 and 62. Will have

Voltage is applied to the pixel electrode 60, and different voltages are applied to the first and second pixel electrodes 61 and 62 so as to complement operating characteristics thereof. To this end, the first thin film transistor T1 and the second thin film transistor T2 are provided to correspond to the first and second pixel electrodes 61 and 62, respectively.

The first thin film transistor T1 includes a first gate electrode 11g, a first source electrode 41s, and a first drain electrode 41d. The first gate electrode 11g is formed branching from the first gate line 11. The first source electrode 41s is branched from the data line 40. The first drain electrode 41d is spaced apart from the first source electrode 41s and is electrically connected to the first pixel electrode 61 through the first contact hole h1.

The second thin film transistor T2 includes a second gate electrode 12g, a second source electrode 42s, and a second drain electrode 42d. The second gate electrode 12g is formed branching from the second gate line 12. The second source electrode 42s is formed to branch off from the data line 40. The second drain electrode 42d is spaced apart from the second source electrode 42s and is electrically connected to the second pixel electrode 62 through the second contact hole h2.

The storage electrode 20 is formed in the center of the pixel area PA. The storage electrode 20 is integrally formed over the first pixel area PA1 and the second pixel area PA2. A transparent insulating film pattern (see 50 in FIG. 3B) is formed on the storage electrode 20 to cover the entire surface of the substrate 1. Openings 51 and 52 are formed in the transparent insulating layer pattern. The openings 51 and 52 are formed in the first opening 51 formed on the storage electrode 20 of the first area PA1 and the second openings formed on the storage electrode 20 of the second area PA2. 52). The transparent insulating layer pattern covers the storage electrode 20 in a predetermined region including a boundary between the first and second pixel electrodes 61 and 62 except for a region where the openings 51 and 52 are formed.

FIG. 3B is a cross sectional view taken along line III-III ′ of FIG. 3A.

Referring to FIG. 3B, the first gate electrode 11g, the storage electrode 20, and the second gate electrode 12g are formed in predetermined regions on the substrate 1, respectively. The gate insulating film 21 is formed on the first gate electrode 11g, the storage electrode 20, and the second gate electrode 12g to cover the entire surface of the substrate 1.

The first semiconductor pattern 31, the first source electrode 41s, and the first drain electrode 41d are formed on the gate insulating layer 21 to cover the first gate electrode 11g. T1) is formed. The first semiconductor pattern 31 includes the first active pattern 31a and the first ohmic contact pattern 31b thereon, and the first ohmic contact pattern 31b includes the first source electrode 41s and the first source pattern 31b. It is formed to be separated from each other along the drain electrode 41d.

In addition, a second semiconductor pattern 32, a second source electrode 42s, and a second drain electrode 42d are formed on the gate insulating layer 21 to cover the second gate electrode 12g. (T2) is formed. The second semiconductor pattern 32 includes the second active pattern 32a and the second ohmic contact pattern 32b thereon, and the second ohmic contact pattern 32b includes the second source electrode 42s and the second. It is formed to be mutually separated along the drain electrode 42d.

The passivation layer 43 is formed on the first thin film transistor T1 and the second thin film transistor T2 to cover the entire surface of the substrate 1, and the transparent insulating layer pattern 50 is formed on the passivation layer 43. The passivation layer 43 and the transparent insulating layer pattern 50 have first and second contact holes h1 and h2. The predetermined region of the first drain electrode 41d is exposed through the first contact hole h1, and the predetermined region of the second drain electrode 42d is exposed through the second contact hole h2.

The pixel electrode 60 is formed on the transparent insulating film pattern 50. The first pixel electrode 61 is formed in the first region PA1 and is electrically connected to the first thin film transistor T1. The second pixel electrode 62 is formed in the second area PA2 and is electrically connected to the second thin film transistor T2. The first and second pixel electrodes 61 and 62 form a boundary at a portion covered with the transparent insulating film pattern 50 on the storage electrode 20.

The storage capacitor is formed by the storage electrode 20, the first and second pixel electrodes 61 and 62, the gate insulating film 21 and the protective film 43 therebetween. The transparent insulating film pattern 50 is formed to a few micrometers thick, and the transparent insulating film pattern 50 is removed in the region where the openings 51 and 52 are formed, so that the storage electrode 20 and the first and second pixel electrodes 61, The separation distance between 62 is reduced. As a result, the capacitance value of the holding capacitor can be increased to improve operating characteristics.

However, a portion of the sustain electrode 20 is covered by the transparent insulating film pattern 50, which is used to prevent the electrical short between each other in forming the first and second pixel electrodes 61 and 62. will be.

Details thereof will be described below with reference to the manufacturing method of the display substrate having the above structure.

4A through 4G are cross-sectional views illustrating a method of manufacturing the display substrate of FIG. 3B.

Referring to FIG. 4A, a gate conductive layer is formed on the substrate 1 and then patterned to form a first gate electrode 11g, a storage electrode 20, and a second gate electrode 12g. The gate conductive layer may be formed by depositing a copper, aluminum, silver, or chromium-based metal or an alloy thereof, and the gate conductive layer may be etched by a wet etching method using an etchant.

Referring to FIG. 4B, a gate insulating layer 21 is formed on the first gate electrode 11g, the storage electrode 20, and the second gate electrode 12g. The gate insulating layer 21 may be formed to cover the entire surface of the substrate 1 using an inorganic compound, for example, a silicon nitride film, using plasma chemical vapor deposition.

The semiconductor film 30 'and the data conductive film 40' are formed on the gate insulating film 21. The semiconductor film 30 ′ is an amorphous silicon film and may be formed to cover the entire surface of the substrate 1 by using plasma chemical vapor deposition. The semiconductor film 30 'includes an active film 30a' and an ohmic contact film 30b 'thereon. The ohmic contact film 30b 'includes impurity ions. The data conductive layer 40 'may be formed in the same manner as the gate conductive layer.

The first photosensitive film pattern 91 is formed on the data conductive film 40 '. The first photoresist layer pattern 91 is formed by coating a photoresist layer of a photoresist component on the data conductive layer 40 'and then exposing and developing the photoresist layer.

The first photoresist pattern 91 has a different thickness depending on the position. The first photoresist layer pattern 91 has a first thickness t1 on the first and second gate electrodes 11g and 12g, and may be formed at the edges of the first and second gate electrodes 11g and 12g and adjacent to the first photoresist pattern 91. It has a second thickness t2 thicker than the first thickness t1. The data conductive layer 40 ′ formed on the sustain electrode 20 is exposed by the first photoresist layer pattern 91.

As described above, a slit mask or a halftone mask is used as the photomask during exposure to the photosensitive film so as to have a different thickness for each region. The slit mask or halftone mask has an intermediate transmissive region in addition to the transmissive region and the opaque region. In the intermediate light-transmitting region, part of the light is transmitted by adjusting the spacing of the slits or using a material having an intermediate tone to expose the photosensitive film. When the photoresist film is a positive type, a pattern having an intermediate thickness of the entire photoresist film may be formed at a portion corresponding to the intermediate light transmission region.

Referring to FIG. 4C, the data conductive layer 40 ′ and the semiconductor layer 30 ′ are etched using the first photoresist layer pattern 91 as an etching mask. The data conductive film 40 'may be etched in the same manner as the gate conductive film, and as a result, a data conductive film pattern 40 "is formed. Then, the semiconductor film 30' is etched to form a preliminary semiconductor film pattern. 30 "is formed. The preliminary semiconductor film pattern 30 "includes a preliminary active pattern 30a" and a preliminary ohmic contact pattern 30b ". The preliminary semiconductor film pattern 30" and the data conductive film pattern 40 "have the same pattern. And overlap each other on a plane.

The first photoresist pattern 91 is uniformly removed by the first thickness t1 to form a second photoresist pattern 92. The second photoresist layer pattern 92 has a thickness corresponding to a difference between the second thickness t2 and the first thickness t1 and covers the first and second gate electrodes 11g and 12g. 40 ").

Referring to FIG. 4D, the data conductive layer pattern 40 ″ is etched using the second photoresist layer pattern 92 as an etching mask. As a result, the first source electrode 41s and the first source electrode 11g are etched on the first gate electrode 11g. A drain electrode 41d is formed, and a second source electrode 42s and a second drain electrode 42d are formed on the second gate electrode 12g. The preliminary semiconductor film pattern 30 " is etched again. The first semiconductor pattern 31 and the second semiconductor pattern 32 are formed. When the etching is performed again, the first ohmic contact pattern 31b separated into two parts from the first semiconductor pattern 31 is formed and the second ohmic contact pattern 32b separated into two parts from the second semiconductor pattern 32. Is formed.

As described above, the first thin film transistor T1 and the second thin film transistor T2 are completed while the first and second semiconductor patterns 31 and 32 are formed. In completing the first and second thin film transistors T1 and T2, the first and second semiconductor patterns 31 and 32, the first and second source electrodes 41s and 42s, and the first and second drain electrodes are formed. 41d and 42d are formed using the same photo mask, so that the process procedure and the cost thereof can be reduced.

Referring to FIG. 4E, the passivation layer 43 and the transparent insulating layer pattern 50 are formed on the first thin film transistor T1 and the second thin film transistor T2. The passivation layer 43 may be formed in the same manner as the gate insulating layer 21. The transparent insulating film pattern 50 may be formed by applying an organic film, for example, an acrylic resin, and then patterning the resin.

The passivation layer 43 and the transparent insulating layer pattern 50 are patterned to have first and second contact holes h1 and h2. In addition, the transparent insulating layer pattern 50 is patterned to have first and second openings 51 and 52 on the sustain electrode 20.

The passivation layer 43 and the transparent insulation layer pattern 50 may be formed using the same photo mask as follows. That is, after the protective film 43 and the organic film are applied, photographs and development are performed, but the entire thickness of the transparent insulating film is removed so that the protective film 43 is exposed in the region where the first and second contact holes h1 and h2 are to be formed. In the region where the first and second openings 51 and 52 are to be formed on the storage electrode 20, the transparent insulating film is left to have a predetermined thickness so that the protective film 43 is not exposed. After the dry etching, the exposed protective layer 43 is removed to form first and second contact holes h1 and h2. At the same time, the openings 51 and 52 are formed on the sustain electrode 20 while the transparent insulating film having the predetermined thickness remains.

Referring to FIG. 4F, a transparent conductive film 60 ′ is formed on the transparent insulating film pattern 50. The transparent conductive film 60 'may be formed by evaporation by sputtering. In the deposition, the transparent conductive film 160' is formed to have a uniform thickness so that the surface height is not constant.

The photosensitive film 93 'is apply | coated on the transparent conductive film 60'. The photosensitive film 93 'is applied by a spin coating method, and the photosensitive film 93' is formed to be substantially flat regardless of the surface height of the transparent conductive film 60 '. As a result, the thickness of the photosensitive film 93 'is different without being constant for each region.

Exposure to the photosensitive film 93 'proceeds. When the photosensitive film 93 'is of a positive type, the photosensitive film 93' corresponding to the portion to be removed from the transparent conductive film 60 'is exposed. In the exposed area, the intensity of light (indicated by an arrow) reaching the photosensitive film 93 'is constant, whereas the thickness of the photosensitive film 93' in the corresponding area is not constant. Therefore, light may not reach the bottom surface of the photosensitive film 93 'in the exposed region in the thick photosensitive film 93'.

For example, in a region covered by the transparent insulating film pattern 50 on the storage electrode 20, a path through which light is to be reached is 'L1'. If the transparent insulating film pattern 50 in the region is opened, the path through which light should reach will be increased by 'L2'.

Referring to FIG. 4G, the exposed portion of the photosensitive film 93 ′ is developed and removed, and the transparent conductive film 60 ′ is etched using the remaining portion as an etching mask to form the pixel electrode 60. The pixel electrode 60 includes first and second pixel electrodes 61 and 62, and the first and second pixel electrodes 61 and 62 form a boundary on the sustain electrode 20 and are separated from each other.

However, as shown in FIG. 4F, light may not reach the bottom surface of the photoresist 93 ′ in the exposed region of the photoresist 93 ′, leaving the photoresist 93 ′ remaining. have. In the region where the photosensitive film 93 'remains, the transparent conductive film 60' below it remains. If the transparent insulating film pattern 50 on the sustain electrode 20 is completely opened, the photosensitive film 93 'may not be completely exposed in the corresponding region, and thus the transparent conductive film 60' may remain.

In the above case, the first and second pixel electrodes 61 and 62 may be electrically shorted to each other during the etching. In the present exemplary embodiment, the first and second pixel electrodes may be covered with the transparent insulating film pattern 50 in a predetermined region corresponding to the boundary between the first and second pixel electrodes 61 and 62. 61, 62 to prevent the electrical short between each other.

On the other hand, within the range in which the above short circuit does not occur, the size of the region in which the transparent insulating film pattern 50 covers the sustain electrode 20 can be made smaller. In this case, the capacitance value of the storage capacitor may be further improved to improve operating characteristics. Specifically, the thickness of the transparent insulating layer pattern 50 may be slightly reduced in the covered area or the first and second openings may be formed in the corresponding area. Various methods may be used in which the transparent insulating layer pattern 50 is gently inclined along the 51 and 52.

Hereinafter, a liquid crystal display device, which is one of display devices using the display substrate as described above, will be described.

5 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 6 is an equivalent circuit diagram of two subpixels of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 5, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 700, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 700 includes a plurality of signal lines (not shown) and a plurality of pixels PX connected to the plurality of signal lines (not shown) and arranged in a substantially matrix form when viewed in an equivalent circuit. 6, the liquid crystal panel assembly 700 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 300 interposed therebetween and arranged with liquid crystals.

The signal line includes a plurality of gate lines (not shown) that transmit gate signals (also referred to as "scan signals") and a plurality of data lines (not shown) that transmit data signals. The gate lines extend approximately in the row direction and are substantially parallel to each other, and the data lines extend approximately in the column direction and are substantially parallel to each other.

Each pixel PX includes a pair of subpixels, and each subpixel includes liquid crystal capacitors Clca and Clcb. At least one of the two subpixels includes a switching element (not shown) connected to the gate line, the data line, and the liquid crystal capacitors Clca and Clcb.

The liquid crystal capacitor Clca / Clcb has two terminals of the subpixel electrode PEa / PEb of the lower panel 100 and the common electrode CE of the upper panel 200, and the subpixel electrodes PEa / PEb and the common electrode. The liquid crystal layer 300 between the (CE) functions as a dielectric. The pair of subpixel electrodes PEa and PEb are separated from each other and form one pixel electrode PE. The common electrode CE is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. The liquid crystal layer 300 has negative dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer 300 may be aligned such that their major axes are perpendicular to the surfaces of the lower and upper panels 100 and 200 in the absence of an electric field.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of primary colors (space division), or each pixel PX alternately displays a basic color (time division) So that the desired color is recognized by the spatial and temporal sum of these basic colors. Examples of the primary colors include three primary colors of light such as red, green, and blue. FIG. 6 illustrates that each pixel PX includes a color filter CF representing one of the primary colors in an area of the upper panel 200 as an example of spatial division. Unlike FIG. 6, the color filter CF may be formed above or below the subpixel electrodes PEa and PEb of the lower panel 100.

Polarizers (not shown) are attached to the outer surfaces of the display panels 100 and 200, respectively, and polarization axes of the two polarizers may be orthogonal to each other. In this case, the light incident on the liquid crystal layer 300 when the electric field is not formed is not transmitted to the outside. In the case of a reflective liquid crystal display, one of the two polarizers may be omitted.

Referring again to FIG. 5, the gray voltage generator 800 generates a plurality of gray voltages (or reference gray voltages) related to the transmittance of the pixel PX.

The gate driver 400 is connected to the gate line of the liquid crystal panel assembly 700 to apply a gate signal Vg formed by a combination of the gate on voltage Von and the gate off voltage Voff to the gate line.

The data driver 500 is connected to the data line of the liquid crystal panel assembly 700, selects the gray voltage from the gray voltage generator 800, and applies the gray voltage to the data line as a data signal. However, when the gradation voltage generator 800 provides only a predetermined number of reference gradation voltages instead of providing all the voltages for all gradations, the data driver 500 divides the reference gradation voltage and supplies the gradation voltage And selects a data signal among them.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 400, 500, 600, and 800 may be mounted directly on the liquid crystal panel assembly 700 in the form of at least one integrated circuit chip, or may be mounted on a flexible printed circuit film (not shown). It may be mounted and attached to the liquid crystal panel assembly 700 in the form of a tape carrier package (TCP), or may be mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 400, 500, 600, and 800 may be integrated in the liquid crystal panel assembly 700. In addition, the drivers 400, 500, 600, 800 may be integrated into a single chip, in which case at least one of them, or at least one circuit element constituting them, may be outside of a single chip.

Next, a liquid crystal panel assembly according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 7 to 13C and FIGS. 5 and 6 described above.

7 is an equivalent circuit diagram of one pixel of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

Referring to FIG. 7, a signal line including a plurality of pairs of gate lines GLa and GLb, a plurality of data lines DL, and a plurality of storage lines SL, and a plurality of pixels PX connected thereto are provided.

Each pixel PX includes a pair of subpixels PXa and PXb, and each subpixel PXa / PXb is a switching element connected to a corresponding gate line GLa / GLb and a data line DL, respectively. Qa / Qb, a liquid crystal capacitor Clca / Clcb connected thereto, and a storage capacitor Csta / Cstb connected to the switching element Qa / Qb and the storage electrode line SL.

Each switching element Qa / Qb is a three-terminal element of a thin film transistor or the like provided in the lower panel 100, and a control terminal thereof is connected to a gate line GLa / GLb, and an input terminal is a data line DL. ) And the output terminal is connected to the liquid crystal capacitor Clca / Clcb and the storage capacitor Csta / Cstb.

The storage capacitor Csta / Cstb, which serves as an auxiliary role of the liquid crystal capacitor Clca / Clcb, is formed by overlapping the storage electrode line SL and the pixel electrode PE provided in the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the storage electrode line SL. However, the storage capacitors Csta and Cstb may be formed such that the subpixel electrodes PEa and PEb overlap the front gate line directly above the insulator.

Since the liquid crystal capacitors Clca and Clcb have been described above, detailed descriptions thereof will be omitted.

In the liquid crystal display device including the liquid crystal panel assembly, the signal controller 600 receives the input image signals R, G, and B for one pixel PX and outputs the two subpixels PXa and PXb. The image signal DAT may be converted and transmitted to the data driver 500. Alternatively, the gray voltage generator 800 separately sets the gray voltage sets for the two subpixels PXa and PXb and alternately provides them to the data driver 500, or alternately selects them in the data driver 500. Different voltages may be applied to the subpixels PXa and PXb. However, at this time, it is preferable to correct the image signal or to create a set of gray voltages so that the composite gamma curve of the two subpixels PXa and PXb is close to the reference gamma curve at the front. For example, the composite gamma curve at the front side matches the reference gamma curve at the front side determined to be most suitable for this liquid crystal panel assembly, and the composite gamma curve at the side side is closest to the reference gamma curve at the front side.

An example of the liquid crystal panel assembly illustrated in FIG. 7 will be described in detail with reference to FIGS. 8 to 11 and FIG. 7 described above.

FIG. 8 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention, and FIGS. 9 to 11 are lines IV-IV ′, V-V ′, and VI-VI ′ of the liquid crystal panel assembly illustrated in FIG. 8, respectively. It is a cross-sectional view cut along.

8 to 11, the liquid crystal panel assembly according to the present exemplary embodiment includes a lower panel 100 and an upper panel 200 facing each other, and a liquid crystal layer 300 interposed between the two display panels 100 and 200. It includes.

First, the lower panel 100 will be described.

A plurality of pairs of first and second gate lines 121a and 121b and a plurality of storage electrode lines 131 on an insulating substrate 110 made of transparent glass or plastic. A gate conductor is formed.

The first and second gate lines 121a and 121b transmit gate signals and mainly extend in the horizontal direction, and are positioned above and below, respectively.

The first gate line 121a includes a plurality of first gate electrodes 124a protruding upward and a wide end portion 129a for connection with another layer or the gate driver 400. The second gate line 121b includes a plurality of second gate electrodes 124b protruding downward and a wide end portion 129b for connection with another layer or the gate driver 400. When the gate driver 400 is integrated on the substrate 110, the gate lines 121a and 121b may extend to be directly connected to the gate driver 400.

The storage electrode line 131 receives a predetermined voltage such as the common voltage Vcom, and mainly extends in the horizontal direction. The storage electrode line 131 is positioned between the first gate line 121a and the second gate line 121b, respectively. Each storage electrode line 131 includes a plurality of storage electrodes 137 extending up and down. However, the shape and arrangement of the storage electrode line 131 including the storage electrode 137 may be modified in various forms.

The gate conductors 121a, 121b, and 131 may be formed of aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper-based metals such as copper (Cu) or copper alloys, and molybdenum (Mo). ) And molybdenum-based metals such as molybdenum alloys, chromium (Cr), tantalum (Ta) and titanium (Ti). However, they may have a multilayer structure including two conductive films (not shown) having different physical properties. One of the conductive films is made of a metal having a low resistivity, for example, an aluminum-based metal, a silver-based metal, or a copper-based metal to reduce signal delay and voltage drop. In contrast, the other conductive film is made of a material having excellent physical, chemical and electrical contact properties with other materials, in particular zinc indium tetraoxide and indium tin oxide, such as molybdenum-based metals, chromium, tantalum, titanium and the like. A good example of such a combination is a chromium bottom film, an aluminum (alloy) top film, an aluminum (alloy) bottom film and a molybdenum (alloy) top film. However, the gate conductors 121a, 121b, and 131 may be made of various other metals or conductors.

Side surfaces of the gate conductors 121a, 121b, and 131 are inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30 ° to about 80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate conductors 121a, 121b, and 131.

On the gate insulating layer 140, a plurality of first and second island-like semiconductors 154a and 154b made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si), polycrystalline silicon, or the like are formed. It is. The first and second island semiconductors 154a and 154b are positioned on the first and second gate electrodes 124a and 124b, respectively.

Isometric ohmic contacts 163a and 165a are formed on the island semiconductors 154a and 154b. The ohmic contacts 163a and 165a may be made of a material such as n + hydrogenated amorphous silicon in which n-type impurities such as phosphorus are heavily doped, or may be made of silicide. The first and second islands of ohmic contact 163a and 165a are arranged in pairs and disposed on islands of semiconductors 154a and 154b.

Side surfaces of the semiconductors 154a and 154b and the ohmic contacts 163a and 165a are also inclined with respect to the surface of the substrate 110, and the inclination angle is about 30 ° to 80 °.

Data including a plurality of data lines 171 and a plurality of pairs of first and second drain electrodes 175a and 175b on the ohmic contacts 163a and 165a and the gate insulating layer 140. A conductor is formed.

The data line 171 transmits a data signal and mainly extends in the vertical direction to cross the gate lines 121a and 121b and the storage electrode line 131. Each data line 171 is not in a straight line throughout and is bent at least twice.

Each data line 171 may have a different layer or data driver 500 than a plurality of pairs of first and second source electrodes 173a and 173b extending toward the first and second gate electrodes 124a and 124b, respectively. It includes a wide end portion 179 for the connection with the). When the data driver 500 is integrated on the substrate 110, the data line 171 may extend to be directly connected to the data driver 500.

The first and second drain electrodes 175a and 175b are separated from each other and also separated from the data line 171.

The first and second drain electrodes 175a and 175b face the first and second source electrodes 173a and 173b around the first and second gate electrodes 124a and 124b, and the rod-shaped ends are bent. It is partially surrounded by the first and second source electrodes 173a and 173b.

The first and second gate electrodes 124a and 124b, the first and second source electrodes 173a and 173b, and the first and second drain electrodes 175a and 175b are formed of the first and second semiconductors 154a and 154b. Together with the first and second thin film transistors (Qa / Qb), the channels of the first and second thin film transistors (Qa / Qb) are formed of the first and second source electrodes ( The first and second semiconductors 154a and 154b are formed between 173a and 173b and the first and second drain electrodes 175a and 175b.

The data conductors 171, 175a, and 175b are preferably made of a refractory metal such as molybdenum, chromium, tantalum, and titanium, or an alloy thereof, and include a refractory metal film (not shown) and a low resistance conductive film (not shown). It may have a multi-layer structure including). Examples of the multilayer structure include a double film of a chromium or molybdenum (alloy) lower film and an aluminum (alloy) upper film, a molybdenum (alloy) lower film, an aluminum (alloy) intermediate film and a molybdenum (alloy) upper film. However, the data conductors 171, 175a, and 175b may be made of various other metals or conductors.

The data conductors 171, 175a, and 175b also preferably have their side surfaces inclined at an inclination angle of about 30 ° to about 80 ° with respect to the surface of the substrate 110.

The ohmic contacts 163a and 165a exist only between the semiconductors 154a and 154b below and the data conductors 171, 175a and 175b above and lower the contact resistance therebetween. The semiconductors 154a and 154b have portions exposed between the data electrodes 171, 175a and 175b, as well as between the source electrodes 173a and 173b and the drain electrodes 175a and 175b.

A passivation layer 180 formed of a transparent insulating layer pattern is formed on the data conductors 171, 175a and 175b and the exposed semiconductors 154a and 154b. The protective film 180 is made of an inorganic insulating material or an organic insulating material and may have a flat surface. The organic insulator preferably has a dielectric constant of 4.0 or less, and may have photosensitivity. However, the passivation layer 180 may have a double layer structure of the lower inorganic layer and the upper organic layer so as not to damage the exposed portions of the semiconductors 154a and 154b while maintaining excellent insulating properties of the organic layer.

The passivation layer 180 includes a plurality of contact holes 182, 185a, and 185b respectively exposing end portions 179 of the data line 171 and one portions of the first and second drain electrodes 175a and 175b, respectively. ) Is formed, and a plurality of contact holes 181a and 181b respectively exposing the end portions 129a and 129b of the gate lines 121a and 121b are formed in the passivation layer 180 and the gate insulating layer 140. In addition, the passivation layer 180 has an opening 186 formed on the sustain electrode 137.

A plurality of pixel electrodes 191 and a plurality of contact assistants 981a, 981b, and 982 are formed on the passivation layer 180. They may be made of transparent conductive materials or reflective metals such as aluminum, silver, chromium or alloys thereof.

Each pixel electrode 191 includes a pair of first and second subpixel electrodes 191a and 191b separated from each other.

The first subpixel electrode 191a is connected to each of the first drain electrodes 175a through the contact hole 185a, respectively, and the second subpixel electrode 191b is formed through the contact hole 185b. It is connected to the 2 drain electrode 175b.

The pixel electrode 191 overlaps the data line 171 with the passivation layer 180 interposed therebetween. One data line 171 overlaps all of the neighboring pixel electrodes 191.

Next, a detailed structure of the pixel electrode of the liquid crystal panel assembly will be described with reference to FIGS. 12, 13A, 13B, and 13C.

12 is a schematic layout view of one pixel electrode in a liquid crystal panel assembly according to various embodiments of the present disclosure, and FIGS. 13A to 13C are plan views of electrode pieces that are the bases of the subpixel electrodes illustrated in FIG. 12.

As shown in FIG. 12, each pixel electrode 191 of the liquid crystal panel assembly according to the exemplary embodiment of the present invention is a pair of first and second subpixel electrodes 191a and 191b separated from each other. It includes. The first subpixel electrode 191a and the second subpixel electrode 191b are adjacent in the row direction and have cutouts 991a and 991b. The common electrode 270 (see FIG. 6) has cutouts 971a and 971b facing the first and second subpixel electrodes 191a and 191b.

Each of the first and second subpixel electrodes 191a and 191b includes at least one parallelogram electrode piece 196 shown in FIG. 13A and one parallelogram electrode piece 197 shown in FIG. 13B. When the electrode pieces 196 and 197 shown in FIGS. 13A and 13B are connected up and down, the base electrodes 198 shown in FIG. 13C are formed, and each of the subpixel electrodes 191a and 191b connects the base electrodes 198. It has a structure based on.

As shown in FIGS. 13A and 13B, each of the electrode pieces 196 and 197 has a pair of oblique edges 196o and 197o and a pair of transverse edges 196t and 197t and is approximately Parallelogram. Each of the oblique sides 196o and 197o forms an oblique angle with respect to the horizontal sides 196t and 197t, and the size of the oblique angle is preferably about 45 degrees to 135 degrees. For convenience, it is divided according to the inclined direction ("inclination direction") in the vertical state with respect to the bases 196t and 197t forward, and the case inclined to the right as shown in FIG. 13A is called "right inclination" and left as shown in FIG. 13B. The case of tilting is called "left slope".

The lengths of the horizontal sides 196t and 197t of the electrode pieces 196 and 197, that is, the distance between the width W and the horizontal sides 196t and 197t, that is, the height H may be freely determined according to the size of the display panel assembly 700. Can be. In addition, the horizontal edges 196t and 197t of each of the electrode pieces 196 and 197 may be deformed or bent in consideration of a relationship with other portions, and will be referred to as a parallelogram in the future.

The common electrodes 270 are formed with cutouts 961 and 962 facing the electrode pieces 196 and 197, and the electrode pieces 196 and 197 have two subregions (centered around the cutouts 961 and 962). S1, S2). Incisions 961 and 962 have at least one notch. The cutouts 961 and 962 form obtuse angles with the oblique portions 961o and 962o and the oblique portions 961o and 962o parallel to the hypotenuses 196o and 197o of the electrode pieces 196 and 197, respectively. Horizontal portions 196t and 962t overlapping the horizontal sides 196t and 197t of the substrate.

Each of the subregions S1 and S2 has two primary edges defined by the oblique portions 961o and 962o of the cutouts 961 and 962 and the hypotenuses 196t and 197t of the electrode pieces 196 and 197. ) The distance between the periphery, i.e. the width of the subregion, is preferably about 25-40 mu m.

The basic electrode 198 shown in FIG. 13C is formed by combining the right inclined electrode piece 196 and the left inclined electrode piece 197. The angle formed by the right inclined electrode piece 196 and the left inclined electrode piece 197 is preferably approximately right angle, and the connection between the two electrode pieces 196 and 197 is made only in part. The unconnected portion forms the cutout 990 and is located at the recessed side. However, the cutout 990 may be omitted.

Outer horizontal sides 196t and 197t of the two electrode pieces 196 and 197 form a horizontal side 198t of the basic electrode 198, and corresponding hypotenuses 196o and 197o of the two electrode pieces 196 are connected to each other. Curved edges 198o1 and 198o2 of the basic electrode 198 are formed.

Curved edges 198o1 and 198o2 meet convex edges 198o1 and transverse sides 198t and obtuse angles such as about 135 ° and acute angles, for example about 45 °. And a concave edge 198o2. The curved sides 198o1 and 198o2 are formed by a pair of hypotenuse sides 196o and 197o at approximately right angles, and thus the angle of bending is approximately right angles.

The cutout 960 extends from the concave vertex CV on the concave side 198o2 to the center of the base electrode 198 toward the convex vertex VV on the convex side 198o1.

In addition, the cutouts 961 and 962 of the common electrode 270 are connected to each other to form one cutout 960. At this time, the horizontal parts 961t and 962t overlapped by the cutouts 961 and 962 are combined to form one horizontal part 960t1. This new type of cutout 960 can be described again as follows.

The cutout 960 is connected to both ends of the bent portion 960o having the bending point CP, the central horizontal portion 960t1 connected to the bending point CP of the bending portion 960o, and the bent portion 960o. And a pair of end cross sections 960t2. The bent portion 960o of the incision 960 consists of a pair of diagonal portions that meet at right angles, and is substantially parallel to the bend sides 198o1 and 198o2 of the base electrode 198, and the base electrode 198 is left and right half. Divide into wealth The central horizontal portion 960t1 of the incision 960 forms an obtuse angle, for example about 135 °, with the bend 960o and extends toward the convex vertex VV of the basic electrode 198. The terminal horizontal portion 960t2 is aligned with the horizontal side 198t of the base electrode 198 and forms an obtuse angle with the bend portion 960o, for example, about 135 °.

The base electrode 198 and the cutout 960 are approximately inverted symmetric with respect to an imaginary straight line (referred to as a "horizontal center line" forward) connecting the convex vertex (VV) and the concave vertex (CV) of the base electrode 198.

In each pixel electrode 191 illustrated in FIG. 12, the size of the first subpixel electrode 191a is smaller than that of the second subpixel electrode 191b. In particular, the height of the second subpixel electrode 191b is higher than the height of the first subpixel electrode 191a, and the widths of the two subpixel electrodes 191b are substantially the same. The number of electrode pieces of the second subpixel electrode 191b is larger than the number of electrode pieces of the first subpixel electrode 191b.

The first subpixel electrode 191a includes a left inclined electrode piece 197 and a right inclined electrode piece 196, and has a structure substantially the same as that of the basic electrode 198 illustrated in FIG. 13C.

The second subpixel electrode 191b is formed of a combination of two or more left inclined electrode pieces 197 and two or more right inclined electrode pieces 196, and is coupled to the basic electrode 198 illustrated in FIG. 13C. Left and right inclined electrode pieces 196 and 197 are included.

The second subpixel electrode 191b illustrated in FIG. 12 includes six electrode pieces 191b1-191b6, and two of the electrode pieces 191b5 and 191b6 are disposed above and below the first subpixel electrode 191a. It is arranged. The pixel electrode 191b has a structure that is bent three times, and has a better vertical line expression than the structure that is curved once. In addition, the cutout portion 961 of the common electrode 270 where the electrode pieces 191a1 and 191a2 of the first subpixel electrode 191a and the electrode pieces 191b5 and 191b6 of the second subpixel electrode 191b are adjacent to each other. Since the horizontal portions 961t and 962t of 962 are combined to form one horizontal portion, the aperture ratio is further increased.

The heights of the intermediate electrode pieces 191a1, 191a2, 191b1, and 191b2 and the electrode pieces 191b3-191b6 disposed above and below are different from each other. For example, the heights of the upper and lower electrode pieces 191b3-191b6 are about 1/2 of the intermediate electrode pieces 191a1, 191a2, 191b1, and 191b2, and thus, the first subpixel electrode 191a and the second subpixel electrode. The area ratio of 191b is approximately 1: 2. Thus, by adjusting the height of the upper and lower electrode pieces 191b3-191b6, a desired area ratio can be obtained.

In FIG. 12, the positional relationship and the bending directions of the first and second subpixel electrodes 191a and 191b may be changed, and the pixel electrode 191 of FIG. 12 may be deformed by inverting symmetry or rotating in the vertical direction. .

Referring back to FIGS. 8 to 13C, the first and second subpixel electrodes 191a and 191b and the common electrode 270 of the upper panel 200 are respectively formed with a portion of the liquid crystal layer 300 therebetween. The second liquid crystal capacitor Clca / Clcb is formed to maintain the applied voltage even after the thin film transistors Qa / Qb are turned off.

The first and second subpixel electrodes 191a and 191b overlap the storage electrode 137 with the gate insulating layer 140 therebetween to form first and second storage capacitors Csta and Cstb, respectively. The second storage capacitor Csta / Cstb enhances the voltage holding capability of the first / second liquid crystal capacitor Clca / Clcb. In this case, since the opening 186 is formed in the passivation layer 180, only the gate insulating layer 140 exists between the pixel electrode 191 and the storage electrode 137, and a distance between the pixel electrode 191 and the storage electrode line 131. Is shortened, so the voltage holding capability is improved.

The contact auxiliary members 981a, 981b, and 982 are end portions 129a and 129b of the gate lines 121a and 121b and end portions 179 of the data line 171 through the contact holes 181a, 181b, and 182, respectively. Connected with The contact auxiliary members 981a, 981b, and 982 compensate for and protect the adhesion between the ends 129a and 129b of the gate lines 121a and 121b and the ends 179 of the data line 171 and an external device. do.

A vertical structure of the upper panel 200 will be described with reference to FIGS. 9 and 10.

A light blocking member 220 is formed on an insulating substrate 210 made of transparent glass or plastic. The light blocking member 220 covers a portion corresponding to the boundary of the pixel electrode 191 and a portion corresponding to the thin film transistor, and defines an opening area that blocks light leakage between the pixel electrode 191 and faces the pixel electrode 191. do.

A plurality of color filters 230 is also formed on the substrate 210 and the light blocking member 220. The color filter 230 is mostly present in an area surrounded by the light blocking member 220, and may extend long along the column of pixel electrodes 191. Each color filter 230 may display one of primary colors such as three primary colors of red, green, and blue.

An overcoat 250 is formed on the color filter 230 and the light shielding member 220. The cover film 250 can be made of (organic) insulation and prevents the color filter 230 from being exposed and provides a flat surface. The cover film 250 may be omitted.

A common electrode 270 is formed on the lid 250.

A plurality of cutouts 971a and 971b are formed in the common electrode 270.

Alignment layers 911 and 921 are formed on inner surfaces of the display panels 100 and 200, and they may be vertical alignment layers.

Polarizers 912 and 922 are provided on the outer surfaces of the display panels 100 and 200, and the polarization axes of the two polarizers 912 and 922 are orthogonal to each other, and one of the polarization axes is provided with respect to the gate lines 121a and 121b. Side by side is preferred. In the case of a reflective liquid crystal display, one of the two polarizers 912 and 922 may be omitted.

The LCD may include polarizers 912 and 922, phase retardation layers, display panels 100 and 200, and a backlight unit (not shown) that supplies light to the liquid crystal layer 300.

The liquid crystal layer 300 has negative dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer 300 are aligned such that their major axes are perpendicular to the surfaces of the two display panels 100 and 200 in the absence of an electric field.

Next, the operation of the liquid crystal display device will be described in detail.

The signal controller 600 receives an input image signal R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown), and processes the input image signal according to an operating condition of the liquid crystal panel assembly 700. The gate control signal CONT1 and the data control signal CONT2 are generated and then output to the gate driver 400 and the data driver 500, respectively.

The gate driver 400 applies a gate-on voltage Von to the gate line according to the gate control signal CONT1 from the signal controller 600 to turn on the switching element connected to the gate line. Then, the data signal applied to the data line is applied to the pixel PX through the turned-on switching element.

In this case, the first subpixel electrode 191a and the second subpixel electrode 191b constituting the pixel electrode 191 are connected to separate switching elements, so that the two subpixels are connected to each other through the same data line at different times. A separate data voltage is applied. In contrast, the first subpixel electrode 191a and the second subpixel electrode 191b are connected to separate switching elements, and may receive separate data voltages through different data lines at the same time. In addition, when the first subpixel electrode 191a is connected to a switching element (not shown) and the second subpixel electrode 191b is capacitively coupled to the first subpixel electrode 191a, the first subpixel electrode 191a is connected to the switching element (not shown). Only the subpixel including the pixel electrode 191a is applied with a data voltage through the switching element, and the subpixel including the second subpixel electrode 191b changes according to the voltage change of the first subpixel electrode 191a. May have a voltage. In this case, the voltage of the first subpixel electrode 191a having a relatively small area is higher than the voltage of the second subpixel electrode 191b having a relatively large area.

The difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies according to the magnitude of the pixel voltage, and thus the polarization of light passing through the liquid crystal layer 300 is changed. This change in polarization is caused by a change in the transmittance of light by the polarizer attached to the display panel assembly 300, whereby the pixel PX displays the luminance represented by the gray level of the image signal DAT.

The angle at which the liquid crystal molecules are inclined depends on the intensity of the electric field. Since the voltages of the two liquid crystal capacitors Clca and Clcb are different from each other, the angles at which the liquid crystal molecules are inclined are different and thus the luminance of the two subpixels is different. Therefore, if the voltage of the first liquid crystal capacitor Clca and the voltage of the second liquid crystal capacitor Clcb are properly adjusted, the image viewed from the side may be as close as possible to the image viewed from the front, that is, the side gamma curve may be front gamma curve. As close as possible to this, side visibility can be improved.

In addition, when the area of the first subpixel electrode 191a to which a high voltage is applied is smaller than the area of the second subpixel electrode 191b, the side gamma curve may be closer to the front gamma curve. In particular, when the area ratios of the first and second subpixel electrodes 191a and 191b are approximately 1: 2 to 1: 3, the side gamma curve becomes closer to the front gamma curve, thereby improving side visibility.

The direction in which the liquid crystal molecules are inclined is primarily determined by the horizontal component in which the cutouts 971a and 971b of the field generating electrodes 191 and 270 and the sides of the subpixel electrodes 191a and 191b distort the main electric field. The horizontal component of this main electric field is substantially perpendicular to the sides of the cutouts 971a and 971b and the sides of the subpixel electrodes 191a and 191b.

Since the liquid crystal molecules on each of the subregions divided by the cutouts 971a and 971b are inclined in a direction perpendicular to the periphery, the four directions are approximately four directions. As described above, when the liquid crystal molecules are inclined in various directions, the reference viewing angle of the liquid crystal display is increased.

In the same region where the cutouts 971a and 971b are formed, when the protrusions are formed on the common electrode 270 instead of the cutouts 971a and 971b, the protrusions act like the cutouts 971a and 971b. That is, the reference field angle of the liquid crystal display may increase as the electric field is distorted by the protrusions.

On the other hand, the direction of the secondary electric field generated by the voltage difference between the subpixel electrodes 191a, 191b is perpendicular to the periphery of the subregion. Thus, the direction of the negative electric field coincides with the direction of the horizontal component of the main electric field. As a result, the negative electric field between the subpixel electrodes 191a and 191b acts to strengthen the crystal in the oblique direction of the liquid crystal molecules.

As described above, the cutout of the common electrode 270 includes a central horizontal portion 960t1, a curved portion 960o, and a terminal horizontal portion 960t2. As shown in FIG. 8, when the central horizontal portion 960t1 is positioned to completely overlap the storage electrode 137, the central horizontal portion 960t1 is a pair separated along the edge of the storage electrode 137. Can be formed. The central horizontal portion 960t1 is positioned at a point where a pair of diagonal lines which are symmetrical to each other forming the curved portion 960o meet. At the meeting point, the liquid crystal molecules may be affected by both the right and left inclined portions of the oblique portion, and the alignment direction thereof may be disturbed. The central horizontal portion 960t1 serves as a means for preventing the above phenomenon and controlling the alignment direction of the liquid crystal molecules.

However, as shown in FIG. 9, in the region where the sustain electrode 137 is formed, the separation distance from the common electrode 270 to the region where the opening 186 is formed is increased. Therefore, the control of the liquid crystal molecules in the corresponding region is weakened so that the central horizontal portion 960t1 may not function properly. In order to prevent this, as shown in FIG. 8, a central horizontal portion 960t1 positioned to overlap with an area where the storage electrode 137 is formed is formed in a pair at the edge of the storage electrode 137.

A liquid crystal panel assembly according to another exemplary embodiment of the present invention will now be described with reference to FIG. 14.

14 is a layout view illustrating a part of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

The liquid crystal panel assembly according to the present exemplary embodiment also includes a lower panel (not shown) and an upper panel (not shown) facing each other and a liquid crystal layer (not shown) interposed between the two display panels.

The vertical structure of the liquid crystal panel assembly according to the present embodiment is generally similar to the layer structure of the liquid crystal panel assembly shown in FIGS. 8 to 13C, and detailed descriptions of the common parts will be omitted.

Referring to the lower panel, a plurality of gate conductors including a plurality of gate lines (not shown) and storage electrode lines 131 are formed on an insulating substrate (not shown). The storage electrode line 131 includes a storage electrode 137. A gate insulating film (not shown) is formed on the gate conductor. An island semiconductor (not shown) is formed on the gate insulating film, and a plurality of ohmic contacts (not shown) are formed thereon. A data conductor including a plurality of data lines 171 is formed on the ohmic contact member and the gate insulating layer. A passivation film (not shown) having an opening 186 is formed on the data conductor 171 and the exposed semiconductor portion, and a plurality of contact holes (not shown) and the opening 186 are formed in the passivation film and the gate insulating film. . A plurality of pixel electrodes 191 and a plurality of contact assistants (not shown) are formed on the passivation layer.

Referring to the upper panel, a light blocking member (not shown), a plurality of color filters (not shown), an overcoat (not shown), a common electrode (not shown), and an alignment layer (not shown) are disposed on an insulating substrate (not shown). Is formed.

The pixel electrode 191 is divided into a first subpixel 191al having a concave side and a second subpixel 101br having a convex side, and at least one recess 193a and 193b is formed at an edge of the concave side. It is. Two recesses 193a and 193b of the first subpixel 191al are formed along the side surface of the opening 186. As a result, a sufficient gap between neighboring first and second subpixels 191al and 191br may be sufficiently secured to prevent an electrical short between the first and second subpixels 191al and 191br.

It is sufficient that at least one recessed part 193a and 193b is formed, and there is no limitation depending on the shape or number thereof. However, the recesses 193a and 193b may be regarded as having a predetermined portion of the pixel electrode 191 cut away, and thus, in the previous embodiment, the direction of the liquid crystal molecules is controlled in the same manner as the central horizontal portion 960t1 of the common electrode 280. It can be used as a means. In this case, according to the same principle as the central horizontal portion 960t1, it is preferable that recessed portions 193a and 193b are formed in pairs at the edges of the sustain electrode 20 in the region overlapping with the sustain electrode 137.

A liquid crystal panel assembly according to another exemplary embodiment of the present invention will now be described with reference to FIG. 15.

15 is a layout view illustrating a portion of a liquid crystal panel assembly according to another exemplary embodiment of the present invention.

The liquid crystal panel assembly according to the present exemplary embodiment also includes a lower panel (not shown) and an upper panel (not shown) facing each other and a liquid crystal layer (not shown) interposed between the two display panels.

The vertical structure of the liquid crystal panel assembly according to the present embodiment is generally similar to the layer structure of the liquid crystal panel assembly shown in FIGS. 8 to 13C, and detailed descriptions of the common parts will be omitted.

Referring to FIG. 15, the first subpixel electrode 191al of the pixel electrode 191 disposed on the left side and the second subpixel electrode 191br of the pixel electrode 191 disposed on the right side are adjacent in the row direction. do. The first and second subpixel electrodes 191al and 191br have convex sides 194a and 194b, respectively. In addition, the first and second subpixel electrodes 191al and 191br may include two concave sides 195a1, 195a2, 195b1, and 195b2, and concave sides 195a and 195b including two longitudinal sides 195a3 and 195b3. Has

The storage electrode line 131 crosses the center portion of the pixel electrode 191. That is, the pixel electrode 191 is vertically symmetrical with respect to the storage electrode line 131. One sustain electrode 137 spans two neighboring pixel electrodes 191. More specifically, the storage electrode 137 overlaps the first subpixel electrode 191al of the pixel electrode 191 positioned on the left side and the second subpixel electrode 191br of the pixel electrode 191 positioned on the right side. do. The storage electrode 137 includes a first portion 137a overlapping the first subpixel electrode 191al and a second portion 137b overlapping the second subpixel electrode 191br.

A passivation layer is formed between the sustain electrode 137 and the pixel electrode 191, and the passivation layer has a first opening 187a and a second opening 187b. The first opening 187a exposes the first portion 137a of the storage electrode 137, and the second opening 187b exposes the second portion 137b of the storage electrode 137. The first and second openings 186 and 187 are separated at portions overlapping the first subpixel electrode 191al and the second subpixel electrode 191br. As a result, a short circuit between the first and second subpixel electrodes 191al and 191br may be prevented from occurring in the stepped portions of the first and second openings 187a and 187b.

Two vertices near the convex side of the second subpixel electrode 191br are chamfered among the vertices of the second opening 187b, and the chamfered hypotenuse is parallel to the convex side of the second subpixel electrode 191br. This can prevent the capacity of the holding capacitor from lowering.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined by the following claims And changes may be made without departing from the spirit and scope of the invention.

Claims (15)

A substrate having a gate line and a data line crossing each other and defining a pixel region, wherein the pixel region has a first region and a second region;
A sustain electrode formed on the substrate over the first and second regions;
A transparent insulating film pattern formed on the sustain electrode and having a first opening on the sustain electrode of the first region and a second opening on the sustain electrode of the second region; And
A first pixel electrode and a second pixel electrode formed on the transparent insulating layer pattern and positioned in the first and second regions, respectively,
The sustain electrode is covered by the transparent insulating film pattern in a region between the first pixel electrode and the second pixel electrode. delete The method of claim 1,
The display substrate of claim 1, wherein different voltages are applied to the first and second regions. The method of claim 1,
And the first and second pixel electrodes are inclined with respect to the length direction of the sustain electrode and have a curved shape in a symmetrical direction. 5. The method of claim 4,
In the transparent insulating film pattern, at least one of the first and second openings is chamfered at at least one vertex, and the chamfered side is parallel to one of the mutually symmetrical directions. Preparing a substrate having a gate line and a data line crossing each other and defining a pixel region, wherein the pixel region has a first region and a second region;
Forming a sustain electrode on the substrate, the sustain electrode positioned over the first and second regions;
Forming a gate electrode spaced apart from the sustain electrode on the substrate, and forming a source electrode and a drain electrode spaced apart from each other on the gate electrode;
Forming a transparent insulating film pattern having a first opening on the sustain electrode of the first region and a second opening on the sustain electrode of the second region on the source electrode and the drain electrode; And
Forming a first pixel electrode and a second pixel electrode in the first and second regions on the transparent insulating film pattern, respectively;
And the sustain electrode is covered by the transparent insulating film pattern in a region between the first pixel electrode and the second pixel electrode. The method according to claim 6,
Forming the source electrode and the drain electrode,
Forming a semiconductor film and a data conductive film to cover the gate electrode and the sustain electrode;
Exposing the data conductive layer on the semiconductor layer and forming a photoresist pattern having different first and second thicknesses according to regions;
Firstly removing the data conductive film exposed by the photosensitive film pattern and the semiconductor film below the data conductive film;
Removing the photoresist pattern by a first thickness;
Secondly removing the first removed data conductive layer exposed by the photoresist pattern removed by the first thickness to form the source electrode and the drain electrode; And
And partially removing the first removed semiconductor film exposed by the source electrode and the drain electrode. The method according to claim 6,
The forming of the gate electrode includes forming a first gate electrode and a second gate electrode spaced apart from each other,
Forming the source electrode and the drain electrode,
Forming a first drain electrode on the first gate electrode, the first drain electrode spaced apart from the first source electrode and electrically connected to the first pixel electrode; And
Forming a second drain electrode on the second gate electrode and a second drain electrode spaced apart from the second source electrode and electrically connected to the second pixel electrode. . A first substrate having a first region and a second region facing each other, and a second substrate;
A liquid crystal layer interposed between the first and second substrates and arranged with liquid crystals;
A sustain electrode formed on the first substrate over the first region and the second region;
A transparent insulating film pattern formed on the sustain electrode and having a first opening on the sustain electrode of the first region and having a second opening on the sustain electrode of the second region;
A pixel electrode formed on the transparent insulating film pattern, the pixel electrode including a first pixel electrode and a second pixel electrode positioned in the first and second regions, respectively;
A common electrode formed on the second substrate, the common electrode having direction control means for controlling an arrangement direction of the liquid crystal;
And the direction control means is located at an edge of the sustain electrode and is formed in a pair parallel to the longitudinal direction of the sustain electrode and symmetrical to each other. The method of claim 9,
And the edges of the direction control means and the sustain electrode overlap each other in plan view. The method of claim 9,
And the direction control means is a cutout pattern in which a part of the common electrode is removed. The method of claim 9,
And said direction control means is a projection formed on said common electrode. The method of claim 9,
And the direction control means is spaced apart from a boundary between the first and second regions. The method of claim 13,
At least one of the first and second pixel electrodes has at least one recess formed in a region where the sustain electrode is formed. The method of claim 13,
And the first and second pixel electrodes are inclined with respect to the length direction of the sustain electrode and have a curved shape in a symmetrical direction.

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