KR101334306B1 - Distribution board, motor control panel and cabinet panel with function of tripping power through sensing of arc flash - Google Patents

Abstract

The present invention is the high pressure distribution panel having the blocking function through an arc flash sensor, a low voltage distributing tool, and a motor control center and a cabinet panel. The high pressure distribution panel, the low voltage distributing tool, and the motor control center and the cabinet panel can detect the generation of the arc flash from the flowing phase currents in any one of holding spaces based on photo sensing signals of the current sensing module, from the sensing and point light sensing unit furnace through an offset sensing unit comprised of two or more point light sensing units, and from AC voltage lines located in the holding spaces. The arc offset and the arc flash which can be generated by the holding space senses cam be sensed at any breaker, a trip coil drive unit and the holding spaces for operating the trip coil of the breaker of three phase voltage that runs in electrical devices for selectively blocking within two or more holding spaces and supplies the sensed illumination to offset the energy level in the arc. The level of the arc energy is calculated from the number of occurrence in a certain period, and also by examining the intensity of the detected arc flash, as well as the duration and the corresponding holding space. The load level is determined based on phase currents sensed by the current sensing module. The necessity of the trip is determined based on the energy level and the load level in the arc. According to the necessity of the trip, the control module includes the operation of the trip coil of the breaker to the trip coil drive unit. [Reference numerals] (12) Main MPU;(14) Sub MPU;(20) Manipulation unit;(22) Remote control receiving unit;(24) Trip level setting unit;(30) Light sensing module;(32) Current sensing module;(34) Access sensing module;(36) Door sensing module;(40) Trip coil drive unit;(42) First light alarming unit;(44) Second light alarming unit;(50) LED display unit;(52) Sound output unit;(54) Screen display unit;(AA) External terminal

Description

Distribution board, motor control panel and cabinet panel with function of tripping power through sensing of arc flash}

The present invention relates to a high-voltage switchgear, a low-voltage switchgear, a motor control panel and a distribution panel for detecting an arc flash to selectively cut off the electricity supply.

In general, the high and low voltage switchgear, the motor control panel and the distribution panel (hereinafter referred to as 'water distribution equipment') for receiving and transforming high and low voltage electricity include various terminals, bus bars, and the like. . In order to prevent the occurrence of fire and / or power outage accidents, safety inspection or maintenance of the power distribution facility is inevitable from time to time.

This safety check and maintenance allows the manager or operator to approach within a certain distance from the power distribution facility. In addition, the safety inspection and maintenance allow the operator or manager to access live power distribution equipment. As such, safety accidents are frequently generated, such as electric shocks to workers or managers.

As a method for preventing the occurrence of such a safety accident, a water distribution facility having a power interruption function through arc flash detection has been disclosed in Korea Patent Registration No. 10-1194708 (hereinafter referred to as 'the first related document'). The water distribution facility according to the first related document, the approach distance of the operator through the approach sensor, the arc through the arc sensor, the current amount of use of the load through the current sensors, these sensing and measured The arc flash accident energy level can be calculated in consideration of resources and spaces in the distribution panel, and control signals can be controlled by supplying a control signal selectively to the trip coil of the circuit breaker according to the calculated arc flash accident energy level. .

For example, an arc may not be detected by an arc sensor, and an access sensor may not be able to detect an operator's access. In this case, the water distribution equipment can naturally perform a normal operation.

On the other hand, if there is no arc detection by the arc flash detection sensor but the worker's approach is detected by the proximity sensor, the characteristics of the power distribution facility and the detected worker such as fault current and / or short circuit current of the power distribution facility are detected. The accident energy level may be determined based on the approach distance of and the breaker may be blocked by the trip coil by adjusting the current applied to the trip coil of the breaker according to the accident energy level. In addition to this, a heavy warning signal according to the approach distance of the operator can be displayed and warned through the display device. As such, the operator can see the warning and exit, and the breaker may not operate. Thereby, the damage of life and power outage can be minimized.

On the other hand, the power distribution equipment is required to stably supply power to any load without power failure. In addition, the power distribution equipment can continuously supply electric power to equipment using an arc, such as an electric arc furnace for melting the metal or the like, which is operated in the vicinity thereof. The arc flash generated in such arc utilizing equipment may have the same or similar wavelength as the arc flash that may be generated in the water distribution facility. As such, the arc sensor in the power distribution facility may detect a normal arc flash (that is, an external arc flash) according to a normal occurrence factor as an arc flash generated inside the water distribution facility by accident or insulation degradation. Therefore, the water distribution facility according to the first related document can drive the breaker unnecessarily or unnecessarily issue a danger alarm. Such unnecessary power outage may not only cause confusion in the maintenance of the power distribution equipment, but may also make normal operation of the load difficult.

As an example to solve the problem in the water distribution equipment according to the first related document, a water distribution equipment having an arc pull-flash sensor that can accurately detect the occurrence position of the arc flash is Korean Patent No. 10-1197021 (Hereinafter referred to as 'the second related document'). In the water distribution facility according to the second related document, the arc pull-lash sensor is configured to include an optical fiber and a fluorescence filter to block unnecessary ultraviolet rays that may enter the sensor. In other words, the water distribution facility allowed only the arc flash from the arc generation area inside to be detected by the arc pull-lash sensor. Through this, the water distribution facility according to the second related literature attempted to facilitate the maintenance work.

However, even if the optical fiber and the fluorescence filter are mounted on the arc pull-ash sensor, it is extremely difficult to completely block external light that may flow into the sensor due to the characteristics of the light. Nevertheless, an additional device may be additionally installed in the power distribution facility to completely block external light, but this may reduce the distance between the elements in the power distribution facility, thereby degrading the insulation characteristics of the power distribution facility. The volume of the water distribution plant can be increased.

In addition, the water distribution facilities according to the first and second related documents can be installed in various working environments, including indoors and outdoors. As such, the illuminance around the water distribution equipment is inevitably changed depending on the installation place and time. The ambient illuminance of this changing power distribution facility cannot affect the detection of whether or not an arc flash having a wavelength of 300 nm to 1500 nm and a brightness of approximately 9000 lux is generated, but the intensity (intensity) of the arc flash detected by the sensor is May affect As a result, the power distribution facilities according to the first and second related documents cannot accurately detect the strength (strength) of the arc flash, and thus may unnecessarily drive the breaker or issue a danger alarm. This unnecessary power outage can cause confusion in the maintenance of water distribution facilities and can also make normal operation of the load difficult.

Korean Patent No. 10-1194708 (October 19, 2012) Korean Patent No. 10-1197021 (October 29, 2012)

Embodiments of the present invention relate to a high voltage switchgear, a low voltage switchgear, a motor control panel and a distribution panel equipped with a digital arc flash relay for solving the above problems.

The present embodiments provide a high voltage switchgear, a low voltage switchgear, a motor control panel, and a switchgear having a blocking function through an arc pull-lash detection suitable for accurately detecting an internal occurrence of an arc flash and accurately controlling power supply / blocking.

In addition, embodiments of the present invention to provide a high-voltage switchboard, a low-voltage switchboard, a motor control panel and a distribution panel equipped with a digital arc flash relay suitable for minimizing unnecessary power outages.

The high voltage switchgear, the low voltage switchgear, the motor control panel and the switchgear having the blocking function through the arc pull-lash detection according to an embodiment of the present invention are: selectively blocking the three-phase voltage flowing into the electrical elements in at least two storage spaces. Circuit breaker for; A trip coil drive unit for driving the trip coil of the breaker; An offset detection unit for detecting illuminance in any one of the storage spaces and supplying the detected illuminance to an arc offset; At least two point light sensing units configured to apply the arc offset to detect an arc flash generated in each of the storage spaces; A current sensing module for sensing phase currents flowing through AC voltage lines disposed in the accommodation spaces; And generation of the arc flash in any of the storage spaces based on the light sensing signals from the point light sensing unit, the intensity of the detected arc flash, the duration and the latest schedule in the storage space. The arc full flash energy level is calculated using the number of occurrences of the period, the load level is calculated based on the phase currents sensed by the current sensing module, and the trip is based on the arc full flash energy level and the load level. The control module may be configured to determine a necessity and cause the trip coil driving unit to drive the trip coil of the breaker according to whether the trip is determined.

The high voltage switchgear, the low voltage switchgear, the motor control panel and the switchgear having a blocking function through the arc pull-lash detection may include: a door detecting unit configured to detect an open / closed state of the doors of the storage spaces; An approach distance detecting unit detecting an approach distance of an accessor to the storage spaces; And it may further include a display unit for displaying the access state of the accessor. In this case, the control module may control the approach distance detected by the approach distance detection unit to be displayed through the display unit when confirming the opening of the door from the door open / close detection signal from the door detection unit.

In addition, the high voltage switchgear, the low voltage switchgear, the motor control panel and the distribution panel having a blocking function through the arc pull-lash detection: a trip level setting unit for setting a threshold trip level; A loop light sensing unit configured to detect the occurrence of the arc flash in all the storage spaces by applying the arc offset; And a driving controller configured to cause the trip coil driving unit to selectively drive the driving coil based on the threshold trip level and the light sensing signal from the loop light sensing unit.

As described above, in the high-voltage switchgear, low-voltage switchgear, the motor control panel and the distribution panel having the blocking function through the arc pull-lash detection in the embodiment of the present invention, the amount of environmental arc component light according to the internal illuminance is generated in each storage space It can be used as offset correction amount for arc pulllash detection which can be done. As such, the arc flash that can be generated in each storage space can be accurately sensed irrespective of ambient illumination. Accordingly, the power can be cut off accurately in response to the arc pull-out, and unnecessary power failure can be prevented.

In addition, generation of the arc flash in each storage space is determined through two inspection processes based on the loop arc detection signal and the point arc detection signal. As such, the occurrence of the arc flash can be detected accurately. Accordingly, the power cutoff can be more accurately performed in response to the arc pulllash.

In addition, the shutoff of the power may be continued in software after the shutdown of the power is initiated in hardware through a comparison of the threshold trip level and the sensed arc flash size. As such, the interruption of power can proceed quickly in the event of an emergency. Accordingly, damage to the water distribution elements in the water distribution facility can be minimized.

1A and 1 are block diagrams illustrating a water distribution facility having a blocking function through arc pull-lash detection according to an embodiment of the present invention.
FIG. 2 is a detailed circuit diagram illustrating an example of a remote receiving cell included in the remote receiving unit of FIG. 1.
3 is a detailed circuit diagram illustrating an example of the trip level setting unit in FIG. 1.
4 is a detailed block diagram illustrating an example of the light sensing module of FIG. 1.
FIG. 5 is a detailed circuit diagram illustrating an example of the point light sensing unit in FIG. 4.
FIG. 6 is a detailed circuit diagram illustrating an example of the loop light sensing unit in FIG. 4.
FIG. 7 is a detailed circuit diagram illustrating an example of an offset sensing unit in FIG. 4.
FIG. 8 is a detailed circuit diagram illustrating an example of the trip coil drive unit in FIG. 1.
9 is a pin block diagram illustrating an example of an internal configuration of a main MPU in FIG. 1.
FIG. 10 is a pin block diagram illustrating an example of an internal configuration of a sub MPU in FIG. 1.
FIG. 11 is a detailed block diagram illustrating an example of an internal configuration of the FPGA in FIG. 1.
12A to 12C are flowcharts illustrating an operation process of the main MPU in FIG. 1.
FIG. 13 is a flowchart illustrating an operation of a sub MPU in FIG. 1.

Hereinafter, the power distribution equipment having a blocking function through the arc pull-lash detection according to the preferred embodiments of the present invention is attached to such that those skilled in the art can easily carry out the present invention. It will be described in detail with reference to the drawings. In the detailed description of the embodiments of the present disclosure, when it is determined that detailed descriptions of related well-known configurations or functions may obscure the gist of the present disclosure, the detailed description may be omitted.

1 is a block diagram illustrating a water distribution facility having a blocking function through arc pull-lash detection according to an embodiment of the present invention.

As shown in FIG. 1, the power distribution facility having a power interruption function through arc pull-lash detection according to an exemplary embodiment of the present invention has a control module 10, an operation unit 20, a remote receiver 22, and a trip level setting. The unit 24 may include a light sensing module 30, a current sensing module 32, an access sensing unit 34, and a door sensing unit 36. The water distribution apparatus includes a trip coil drive unit 40, first and second light notification units 42 and 44, an LED display unit 50, a sound output unit 52, and a screen display unit 54 . The control module 10 may include a main microprocessor unit 12, a sub MPU 14, a field programmable gate array (FPGA) 16 and an analog multiplexer 18, no.

The operation unit 20 can transmit an instruction from an operator or an administrator to the main MPU 12 of the control module 10. [ For example, the control unit 20 may provide a mode command for switching between an on-line mode and a service mode, a reset command for clearing an error state, and a trip command for driving a trip coil. It can be delivered to the main MPU 12 of. For this, the operation unit 20 may include a mode button, a reset button, and a trip button, but is not limited thereto. The output of the mode button, the reset button, and the trip button may be supplied to the main MPU 12 of the control module 10.

In addition, the operation unit 20 may further include a setting button, a cancel button, an up button, and a down button. The setting button can be used to request to display a setting image for setting the system on the screen display unit 52. [ The cancel button can be used to request the screen display 52 to display an initial image. The up and down buttons can be used to request to scroll the displayed image on the screen display 52 up or down. The output of the setting button, the cancel button, and the up and down buttons may be supplied to the sub MPU 14 of the control module 10, although not shown in the figure.

The remote receiving unit 22 can transmit an operator or manager command sent from the remote controller to the main MPU 12 of the control module 10. [ For example, the remote receiver 22 may transmit the mode command, the reset command, and the trip command to the main MPU 12 of the control module 10. The main MPU 12 of the control module 10 receives the trip command from the operation unit 20 and the remote receiving unit 22 even if the trip command is transmitted to the main MPU 12 of the control module 10. [ The on-line mode can be ignored.

In general, the remote controller sends a remote signal (eg, an infrared signal) in the form of digital data such as a pulse train. However, as the remote controller moves away from the remote receiver 22, there is a tristate area for allowing the remote receiver 22 to input an unrecognizable weak remote signal of '0' and '1'. As such, the remote receiving unit 22 receiving the remote signal transmitted from the remote controller located in the tri-state area may generate an error. To prevent this, the remote receiver 22 may be implemented by an analog circuit as shown in FIG. 2 to prevent the occurrence of an error due to the received weak remote signal. In addition, the remote receiver 22 may include three remote receiving cells for receiving and separating the three commands. The first to third remote signals output from the three remote receiving cells may be supplied to the analog multiplexer 18 of the control module 10. These remote receiving cells may each be implemented as shown in FIG. 2.

2, the remote receiving cell includes a remote signal sensor IRS, first to fourth resistors R1 to R4, a first capacitor C1, a first diode D1, and a first voltage follower ( OP1).

The remote signal sensor IRS and the first resistor R1 are connected in series between a first DC voltage line VCC and a ground voltage line GND. The first DC voltage VCC may be a transistor-transistor voltage, for example, about 5V. The remote signal sensor (IRS) has a resistance value that decreases according to the intensity of an incoming remote signal. When a strong remote signal is incident, the resistance value of the remote signal sensor IRS may have a resistance value similar to or lower than that of the first resistor R1. Alternatively, when a weak remote signal is received or a remote signal is not received, the remote signal sensor (IRS) may have a very large resistance value as compared to the first resistor Rl. As such, the remote signal sensor IRS may allow a remote receive voltage to be generated that increases as the intensity of the incident remote signal becomes stronger. As such a remote signal sensor (IRS), an infrared sensor may be used. The remote receive voltage may be transmitted from the connection point between the remote signal sensor IRS and the first resistor R1 to the non-inverting terminal of the first voltage follower OP1.

The first voltage follower OP1 may buffer the remote receive voltage from the connection point of the remote signal sensor IRS and the first resistor R1. The remote reception voltage Vrrs buffered by the first voltage follower OP1 may be supplied to the analog multiplexer 18 of the control module 10 shown in FIG. 1.

The second resistor R2 and the first capacitor C1 integrate the remote reception voltage sensed by the remote signal sensor IRS to convert the integrated remote reception voltage to the first voltage follower OP1. Can be supplied to The integral time constant of the second resistor R2 and the first capacitor C1 may be set differently according to a remote receiving cell to distinguish the three commands. For this purpose, the second resistor R2 may be connected between the remote signal sensor IRS and the non-inverting terminal + of the first voltage follower OP1, and the first capacitor C1 may be The non-inverting terminal + of the first voltage follower OP1 and the base voltage line GND may be connected to each other.

The first diode D1 and the third and fourth resistors R3 and R4 may implement one level limiter. As such, the first diode D1 and the third and fourth resistors R3 and R4 are connected to the first voltage follower OP1 from a connection point between the remote signal sensor IRS and the first resistor R1. A low level remote reception voltage (i.e., a weak remote signal) that can be supplied to the non-inverting terminal (+) of < RTI ID = 0.0 > In other words, the first diode D1 and the third and fourth resistors R3 and R4 have at least a predetermined level of a remote receiving voltage at which the remote signal sensor IRS and the first resistor R1 are connected. It is possible to supply from the non-inverting terminal (+) of the first voltage follower (OP1) from. Accordingly, an error in the remote reception voltage (Vrrs) output from the first voltage follower (OP1) can be prevented.

The trip level setting unit 24 can set a critical trip level (or critical arc level) Vcts by an operation of an administrator or an operator. The threshold trip level Vcts may be set to have a value within an upper level range of approximately 50% of the arc pulllash level scale. For example, the arc full-flash level scale assigns a value of '1' to the minimum arc detection level Vmadl at which the occurrence of arc flash can be detected, as well as '100' at the maximum level the arc flash can have. When divided into a form of assigning a value of ', the threshold trip level Vcts may be set to have any value within an upper level range of approximately 50 to 100. In addition, the threshold trip level (Vcts) may be set appropriately for the water distribution equipment based on at least one of statistical facts such as the intensity (or intensity) of the arc flash, the duration and the number of occurrences. For example, the critical trip level Vcts may be adjusted according to the type of arc sensor applied and the characteristics of the power distribution equipment. The threshold trip level set as described above can be used to specify an emergency situation. The threshold trip level Vcts set by the trip level setting unit 24 may be supplied to the main MPU 12 via the analog multiplexer 18. [ The trip level setting unit 24 may be implemented as shown in FIG. 3.

As illustrated in FIG. 3, the trip level setting unit 24 may include fifth and sixth resistors R5 and R6, a first variable resistor VR1, and a second voltage follower OP2. . The fifth and sixth resistors R5 and R6 and the first variable resistor VR1 may be connected in series between the first DC voltage line VCC and the ground voltage line GND. The first variable resistor VR1 may be connected between the fifth and sixth resistors R5 and R6 and may have a resistance value which is increased or decreased by an operation of a manager or an operator. The first variable resistor (VR1) may divide the first DC voltage (VCC) and output the divided voltage as the critical trip level signal (Vcts). The second voltage follower OP2 buffers the critical trip level signal Vcts from the first variable resistor VR1 and supplies the buffered critical trip level signal to the control module 10 shown in Fig. To the analog multiplexer 18 of FIG.

Referring back to FIG. 1, the light sensing module 30 may detect an arc flash that may be generated in a plurality of spaces in the water distribution facility. In addition, the light sensing module 30 may sense environmental arc component light according to the ambient illuminance of the water distribution equipment. In addition, the light sensing unit 30 may provide the detected environmental arc component light to the detection of the arc flash to enable accurate arc pulllash detection. To this end, the light sensing module 30 may include at least two point light sensing units, one loop light sensing unit, and an offset sensing unit.

For example, when the water distribution equipment is divided into five storage spaces, the light sensing module 30 may be implemented as shown in FIG. 4. As shown in FIG. 4, the light sensing module 30 may include first to fifth point light sensing units 100A to 100E, a loop light sensing unit 110, and an offset sensing unit 120. .

The first to fifth point light sensing units 100A to 100B may be disposed in the five storage spaces, respectively. In addition, the first to fifth point light sensing units 100A to 100E can commonly input the arc offset voltage Voff from the offset sensing unit 120. [ Each of the first to fifth point light sensing units 100A to 100E may accurately detect an arc flash generated in a corresponding storage space by using the arc offset voltage. The first to fifth point arc detection signals Vpas1 to Vpas5, which may be detected by the first to fifth point light sensing units 100A to 100E, are the main MPU of the control module 10 shown in FIG. 1. 12 can be supplied.

The loop light sensing unit 110 may also input the arc offset voltage Voff from the offset sensing unit 120. [ In addition, the loop light detecting unit 110 may accurately detect the arc flash generated in all of the five storage spaces by using the arc offset voltage Voff. The loop arc detection signal Vlas which can be detected by the loop light sensing unit 110 may be supplied to the main MPU 12 of the control module 10 shown in FIG.

The offset detection unit 120 may sense the environmental arc component light according to the ambient illuminance of the water distribution equipment. The offset detection unit 120 detects the environmental arc component light as the arc offset voltage Voff from the first to fifth point light sensing units 100A to 100E and the loop light sensing unit 110 . Alternatively, the offset sensing unit 120 may supply the sensed environmental arc component light to the main MPU 12 of the control module 10 shown in FIG. 1 as an offset sensing voltage Voff. . In this case, the first to fifth point light sensing units 100A to 100E and the loop light sensing unit 110 are connected to the main MPU 12 of the control module 10, The arc offset voltage Voff can be input from the arc offset voltage Voff.

FIG. 5 is a detailed circuit diagram illustrating an example of the point light sensing unit 100 illustrated in FIG. 4.

Referring to FIG. 5, the point light detecting unit 100 may include a first light sensor LSS1, a first offset corrector 102, and a first amplifier 104. In addition, the point light sensing unit 100 may further include a first sensor state display unit 106.

The first photosensor LSS1 may be connected to the first DC voltage line VCC via the second variable resistor VR2 as well as to the ground voltage line GND. As the second variable resistor VR2 has a resistance value adjusted by an administrator or an operator, the sensing sensitivity of the first optical sensor LSS1 may be adjusted. Also, the first optical sensor LSS1 is disposed in any one of the storage spaces of the water distribution equipment. In addition, the first photosensor LSS1 can increase the amount of current according to the intensity of incident arc light. As such, a point light sensing signal having a voltage level that increases with the intensity of the arc light incident on the first optical sensor LSS1 may be generated. The point light detection signal may include an environmental arc component light according to an illuminance state in the storage space and an arc flash that may be generated in at least one of specific portions in the storage space. As the first photosensor LSS1, a well-known ultraviolet sensor may be used.

The first output correction unit 102 performs offset-correction of the point light detection signal sensed by the first optical sensor LSS1 using the arc offset voltage Voff and outputs the offset- As an arc detection signal. In other words, the first offset correction unit 102 may separate-extract only the arc flash from the point light detection signal. As such, the point arc detection signal output from the first offset correction unit 102 may include only an arc pulllash component that may be generated at any specific portion of the storage space. Accordingly, the first offset correction unit 102 allows the arc flash that may be generated in the storage space to be accurately detected even when the external light of the power distribution equipment is introduced into the storage space through the ventilation holes and / or the gaps. In other words, even when the operation using the arc (metal melting furnace, welding machine, etc.) is performed outside of the water distribution facility, the opposition correction unit 102 can accurately detect the arc flash generated in the storage space. The first offset correction unit 102 may be configured by a first differential amplifier OP3, seventh and eighth resistors R7 and R8, and a first transistor Q1.

The first differential amplifier OP3 inputs the point photosensitive signal from the connection point between the first optical sensor LSS1 and the second variable resistor VR2 toward its inverting terminal (-) and the figure. The arc offset voltage Voff from the offset sensing unit 120 of 4 may be input toward its non-inverting terminal (+). The output terminal of the first differential amplifier OP3 may be connected to the base electrode of the first transistor Q1 via the seventh resistor R7. A collector electrode of the first transistor Q1 may be connected to the first DC voltage line VCC and an emitter electrode of the first transistor Q1 may be connected to the ground voltage line V2 via an eighth resistor R8. (GND).

The first DC voltage (Vout) is output from the output terminal of the first differential amplifier OP3 when the point light sensing signal on the inverting terminal (-) is not higher than the arc offset voltage (Voff) on the non-inverting terminal VCC) may be output. As such, the first transistor Q1 may be turned off and the point corresponding to the base voltage from the emitter electrode of the first transistor 1 turned off toward the first amplifier 104. The light sensing signal may be output.

On the contrary, when the point light sensing signal on the inverting terminal (−) is higher than the arc offset voltage Voff on the non-inverting terminal (+), the point light sensing signal and the point from the first DC voltage VCC An output signal of the first differential amplifier OP3 lowered by a voltage corresponding to (or proportional to) the difference voltage of the arc offset voltage Voff may be output. As a result, the first transistor Q1 is turned on and a current amount corresponding to (or proportional to) the difference voltage between the point light sensing signal and the arc offset voltage Voff is supplied to the first DC voltage line VCC, To the eighth resistor (R8). Accordingly, the point arc detection signal corresponding to (or proportional to) the difference voltage between the point light sensing signal and the arc offset voltage Voff is output from the emitter electrode of the first transistor Q1, (Not shown).

The first amplifier 104 amplifies the point arc detection signal from the first offset correction unit 102 and converts the amplified point arc detection signal Vpas into the control module 10 shown in FIG. 1. Can be supplied to the main MPU (12). To this end, the first amplifier 104 may be implemented by a second diode D2, a second capacitor C2, ninth through thirteenth resistors R9 through r13, and a first operational amplifier OP4. have.

The second diode D2 and the eleventh resistor R11 are emitter electrodes of the first transistor Q1 of the first offset compensator 102 and non-inverting terminals of the first operational amplifier OP4. It can be connected in series between (+). The ninth resistor R9 may be connected between the first DC voltage line VCC and the cathode electrode of the second diode D2. The tenth resistor R10 may be connected between the cathode electrode of the second diode D2 and the ground voltage line GND. The second capacitor C2 may be connected between the non-inverting terminal + of the first operational amplifier OP4 and the base voltage line GND. The twelfth resistor R12 may be connected between the inverting terminal (-) and the output terminal of the first operational amplifier OP4. The thirteenth resistor R13 may be connected between the inverting terminal (-) of the first operational amplifier OP4 and the ground voltage line GND.

The second diode D2 and the ninth and tenth resistors R9 and R10 may implement one level limiter. As such, the second diode D2 and the ninth and tenth resistors R9 and R10 may be operated from the emitter electrode of the first transistor Q1 in the first offset compensator 102. A low level point arc detection signal (that is, a weak point arc detection signal) that can be supplied to the non-inverting terminal + of the amplifier OP4 may be blocked. In other words, the second diode (D2) and the ninth and tenth resistors (R9, R10) have at least a point arc detection signal of a level from the emitter electrode of the first transistor (Q1) To the non-inverting terminal (+) of the amplifier OP4. As such, the arc flash that can be generated at any particular area within the storage space can be detected more accurately.

The first operational amplifier OP4 may amplify the point arc detection signal input to its non-inverting terminal (+) through the second diode D2 at a constant amplification rate. The point arc detection signal Vpas amplified by the first operational amplifier OP4 may be supplied to the main MPU 12 of the control module 10 illustrated in FIG. 1. The amplification factor of the first operational amplifier OP4 may be determined by the resistance values of the tenth to thirteenth resistors R10 to R13. The second capacitor C2 may remove noise of a high frequency component included in the point arc detection signal supplied to the non-inverting terminal (+) of the first operational amplifier OP4.

The first sensor status indicator 106 detects point light under the control of the control module 10 shown in FIG. 1 (more specifically, under the control of the main MPU 12 or the FPGA 16). The normal driving state and the arc pull detection state of the unit 100 may be displayed. The first sensor state display unit 106 may include a first LED LD1, a second transistor Q2, and a resistor R14.

The first LED (LD1) may be connected between the first DC voltage line (VCC) and the collector electrode of the second transistor (Q2). The fourteenth resistor R14 may be connected between the base electrode of the second transistor Q2 and the control input line CSled. The emitter electrode of the second transistor Q2 may be connected to the ground voltage line GND. The control input line CSled may be supplied with a flashing control signal CSled from the control module 10 (ie, the main MPU 12 or the FPGA 16) illustrated in FIG. 1. The flashing control signal CSled may include a fast cycle pulse train or a slow cycle pulse train.

For example, when the first optical sensor LSS1, the first offset correction unit 102, and the first amplifier 104 are correctly configured and normally driven, the flashing control signal CSled may have a fast cycle. It may include a pulse train of. In this case, the second transistor Q2 opens and closes the current path of the first LED LD1 at a fast cycle according to the fast cycle of the pulse. As a result, the first LED (LD1) flickers at a fast cycle to display the normal driving state of the point light sensing unit 100. [

In addition, when the arc flash generated at a specific part of the storage space is detected by the first optical sensor LSS1, the first offset correction unit 102, and the first amplifier 104, the flashing is performed. The control signal CSled may include a pulse string of a slow cycle. As such, the second transistor Q2 opens and closes the current path of the first LED LD1 in a slow cycle according to the pulse train of the slow cycle. Accordingly, the first LED LD1 blinks in a slow cycle so that an occurrence of arc flash in the corresponding storage space is displayed.

On the contrary, when the first optical sensor LSS1, the first offset correcting unit 102, and the first amplifying unit 104 are not configured correctly and cannot be driven normally, the flashing control signal CSled is It does not contain any pulse train. In other words, when the first offset correcting unit 102 and the first amplifying unit 104 are not properly configured and can not be driven normally, the flicker control signal CSled maintains the ground voltage GND . In this case, the second transistor Q2 opens the current path of the first LED LD1 by the base voltage GND. As a result, the first LED (LD1) is turned off to indicate that the first offset correcting unit 102 and the first amplifying unit 104 are not correctly configured and can not be normally driven.

FIG. 6 is a detailed circuit diagram illustrating an example of the loop light sensing unit 110 illustrated in FIG. 4.

As shown in FIG. 6, the loop optical sensing unit 110 includes an optical fiber cable LFC, a second optical sensor LSS2, a second offset corrector 112, and a second amplifier 114. can do. In addition, the loop light sensing unit 110 may further include a first sensor state indicator 116. In addition, the loop light sensing unit 110 may further include at least one arc light generator 118.

The optical fiber cable (LFC) may be disposed via the receiving spaces of the power distribution equipment. In addition, the optical fiber cable LFC may guide the light in the storage spaces toward the second optical sensor LSS2. As such, by the optical fiber cable LFC, environmental arc component light according to the illumination condition in each of the storage spaces and arc flash that may be generated in each of the storage spaces are generated by the second optical sensor LSS2. Can be guided toward).

The second photosensor LSS2 may be connected to the first DC voltage line VCC via the third variable resistor VR3 as well as to the ground voltage line GND. The sensing sensitivity of the second photosensor LSS2 may be adjusted as the third variable resistor VR3 has a resistance value adjusted by adjustment by an administrator or an operator. The second optical sensor LSS1 is disposed at one end of the optical fiber cable LFC so that it can receive arc lights from the receiving spaces of the water distribution equipment guided by the optical fiber cable LFC have. In addition, the second photosensor LSS2 can increase the amount of current according to the intensity of the incident arc light. As a result, a loop light sensing signal having a voltage level that increases according to the intensity of the arc light incident on the second photosensor LSS2 can be generated. The loop light sensing signal may include an environmental arc component light according to an illuminance state in the receiving spaces of the power distribution equipment and an arc flash that may be generated in at least one of the storage spaces of the power distribution equipment. A well-known ultraviolet sensor may be used as the second photosensor LSS2.

The second offset correction unit 112 performs offset-correction of the loop light sensing signal sensed by the second optical sensor LSS2 using the arc offset voltage Voff, and supplies the offset- As an arc detection signal. In other words, the second offset correction unit 112 may separate-extract only the arc flash from the loop light detection signal. As such, the loop arc detection signal output from the second offset correction unit 112 may include only an arc pulllash component that may be generated in at least one of the receiving spaces of the power distribution equipment. Accordingly, the second offset correction unit 112 allows the arc flash that may be generated in the receiving spaces of the power distribution equipment to be accurately detected.

Accordingly, the first offset correction unit 102 accurately detects the arc flash that may be generated in the storage spaces even though the external light of the power distribution equipment is introduced into the storage space through the ventilation holes and / or the gaps. In other words, even if the operation using the arc (metal melting furnace and welding machine, etc.) is performed outside of the water distribution facility, the opposition correction unit 102 can accurately detect the arc flash generated in the plurality of storage spaces. . The second offset correcting unit 112 may be configured in the same manner as the first offset correcting unit 102 shown in FIG. As such, a detailed description of the second offset correcting unit 112 will be omitted.

 The second amplifier 114 amplifies the loop arc detection signal from the second offset correction unit 102 and converts the amplified loop arc detection signal Vlas into the control module 10 shown in FIG. 1. Can be supplied to the main MPU (12). The second amplifier 114 may be configured in the same manner as the first amplifier 104 illustrated in FIG. 5. As such, a detailed description of the second amplifying unit 114 will be omitted.

The second sensor status indicator 116 detects loop light under the control of the control module 10 shown in FIG. 1 (more specifically, under the control of the main MPU 12 or the FPGA 16). The normal driving state and the arc pull detection state of the unit 110 may be displayed. The second sensor state display unit 116 may be configured in the same manner as the first sensor state display unit 106 shown in FIG. 5. As such, a detailed description of the second sensor state display unit 116 will be omitted.

For example, when the second optical sensor LSS2, the second offset correcting unit 112, and the second amplifying unit 114 are correctly configured and driven normally, the second LED LD2 is driven at a fast cycle So that the normal driving state of the loop light sensing unit 110 is displayed. In addition, the arc flash generated in at least one of the receiving spaces of the power distribution facility is detected by the second optical sensor LSS2, the second offset corrector 112, and the second amplifier 114. The second LED LD2 flashes in a slow cycle so that the fact that the arc flash is generated in at least one of the receiving spaces of the power distribution facility is displayed. Alternatively, when the second light sensor LSS2, the second offset correction unit 112 and the second amplification unit 114 are not properly configured and can not be normally driven, the second LED LD2 The second light sensor LSS2, the second offset correcting unit 112, and the second amplifying unit 114 are not properly configured and thus can not be normally driven.

The at least one arc light generator 118 may be arranged at the other end of the optical fiber cable (LFC) or at regular intervals therefrom. The at least one arc light generating part 118 may supplement the light quantity of the environmental arc light component sensed by the second light sensor LSS2. Indeed, the amount of environmental arc light component light detected by the second light sensor LSS2 is compared to that detected by the first light sensor LSS1 of the point light sensing unit 100 shown in FIG. 5. Can be significantly reduced. As a result, an error may occur in the loop arc detection signal Vlas. In order to prevent the occurrence of an error in the loop arc detection signal Vlas, the at least one arc light generator 118 may be used in the loop light detection unit 110.

The light generating unit 118 may include a light emitting device OAD and a fourth variable resistor VR4. The fourth variable resistor VR4 and the light emitting element OAD may be connected in series between the first DC voltage line VCC and the ground voltage line GND.

The light emitting device OAD may emit visible light of approximately 650 nm corresponding to the arc component light. The visible light emitted from the light emitting device OAD may be incident on the second optical sensor LSS2 along the optical fiber cable LFC. In addition, the amount of visible light emitted from the light emitting device OAD may be determined through adjustment of the resistance value of the fourth variable resistor VR4 by an operation of a manager or an operator.

FIG. 7 is a detailed circuit diagram illustrating an example of the offset detection unit 120 in FIG. 4.

As shown in FIG. 7, the offset detection unit 120 includes a third optical sensor LSS3, a third capacitor C3, fifth and sixteenth resistors R15 and R16, and a third voltage follower OP5. ) May be included.

The third photosensor LSS3 may be connected to the first DC voltage line VCC via the fifteenth resistor R15 as well as to the ground voltage line GND. The fifteenth resistor (R15) may determine the sensing sensitivity of the third photosensor (LSS3). In addition, the third optical sensor LSS3 may be disposed in any one of a plurality of storage spaces of the power distribution facility. In addition, the third optical sensor LSS3 may have a resistance value that decreases according to the intensity of incident light. As such, an internal light sensing signal having a voltage level that increases according to the intensity of light incident on the third optical sensor LSS3 may be generated at a connection point between the third optical sensor LSS3 and the fifteenth resistor R15. have. The internal light sensing signal may include environmental arc component light (i.e., visible light) according to the illuminance state of the storage space of the water distribution equipment. A visible light sensor such as cadmium sulfide, which is well known, may be used as the third photosensor LSS1.

The sixteenth resistor R16 may be connected between a connection point of the third photosensor LSS3 and the fifteenth resistor R15 and a non-inverting terminal (+) of the third voltage follower OP5. The third capacitor C3 may be connected between the non-inverting terminal + of the third voltage follower OP5 and the base voltage line GND. The sixteenth resistor R16 and the third capacitor C3 may configure an integrator that integrates the environmental arc component light sensing signal sensed by the third optical sensor LSS3. As such, the environmental arc component light sensing signal from the connection point of the third optical sensor LSS3 and the fifteenth resistor R15 is integrated by the sixteenth resistor R16 and the third capacitor C3. After that, it can be supplied to the third voltage follower OP5.

The third voltage follower OP3 may buffer the integrated environmental arc component light sensing signal. The environmental arc component light sensing signal buffered by the third voltage follower OP5 is the first to fifth point light sensing units 100A to 100E illustrated in FIG. 4 as the arc offset voltage Voff. And the loop light sensing unit 110. In other words, the buffered environmental arc component light sensing signal may be supplied to the inverting terminal (−) of the first differential amplifier OP3 shown in FIGS. 5 and 6 as the arc offset voltage Voff.

Returning to FIG. 1, the current sensing module 32 includes three phase currents (i.e., R) that are hand-distributed through three-phase power lines (ie, R-phase, T-phase, and S-phase power lines) in the water distribution facility. Phase, T phase and S phase currents). As such, three phase current sensing signals may be supplied from the current sensing module 32 to the analog multiplexer 18. The current sensing module 32 may include three phase current sensing units arranged corresponding to the three-phase power line. Each of the phase current sensing units may include a non-contact type Hall sensor disposed on the phase power line and a buffer for buffering the phase current sensing signal from the Hall sensor. The Hall sensor can sense up to 100A of current. In addition, the Hall sensor can output a phase current sensing signal having an intermediate voltage of about 2.5 V when there is no current flow in the phase power line. The buffer may buffer the phase current sense signal from the corresponding connected Hall sensor and supply it to the analog multiplexer 18.

When the door of the water distribution facility is opened, the approach detecting unit 34 detects the distance to the approaching manager or worker and transmits the detected approach sensing data to the sub-MPU 14 of the control module 10. Can supply As such, the proximity sensing unit 34 may be disposed within the water distribution facility. For the transmission of the access distance data, the approach sensing unit 34 may be connected to the sub MPU 14 by an RS-485 serial bus.

The door detection unit 36 may detect an open / closed state of the door of the power distribution equipment, and supply a door open / close detection signal to the sub MPU 14 of the control module 10. In order to transmit the door open / close detection signal, the door detection unit 34 may be connected to the sub MPU 14 by the RS-485 serial bus. In addition, the door open / close detection signal generated by the door detection unit 36 may be scanned by the sub MPU 14 at a period of approximately 0.5 seconds.

The trip coil driving unit 40 drives a trip coil (not shown) in response to only a software trip control signal CSstr from the main MPU 12 of the control module 10 to distribute power to three phases. Power can be selectively turned off. In addition, the trip coil driving unit 40 may generate a hardware trip control signal CShtr from the arc detection signal from the light sensing module 30 and the threshold trip level from the trip level setting unit 24. Can be. In this case, the trip coil drive unit 40 is applied to the hardware trip control signal CShtr according to the logic value of the trip prohibition control signal CStrp from the main MPU 12 of the control module 10. You can respond. For example, the trip coil drive unit 40 responds to the hardware trip control signal CShtr only when the trip prohibition control signal CStrp is in a disabled state (eg, a high logic state). That is, the trip coil (not shown) may be driven to selectively cut off three-phase electric power distributed by water. In addition, the software trip control signal CSstr is generated after a time elapsed from about 0.5 to 2.5 msec from the time of detecting the excessive arc flash due to the confirmation process of the main MPU 12, whereas the hardware trip control signal CSstr CShtr) may occur within a period of approximately 0.5 msec at the time of detection of the excessive arc flash. As a result, the trip coil drive unit 40 starts to drive the trip coil in response to the hardware trip control signal CShtr, and then, in response to the software trip control signal CSstr, Can be maintained. Therefore, the trip coil drive unit 40 can promptly cut off the power to be supplied by driving the trip coil quickly when a trip factor (emergency situation) is caused. The trip coil drive unit 40 may be configured as shown in FIG. 8.

Referring to FIG. 8, the trip coil drive unit 40 may include a control high voltage switch (IGBT), a bridge diode (BD), a transformer (TM1), a clock generator 200, and a switch driver 210. In addition, the trip coil driving unit 40 may further include a trip coil voltage monitoring unit 220. In addition, the trip coil driving unit 40 may further include a trip accelerator 230.

The control high voltage switch IGBT may be connected in series to the trip coil TC. In addition, the control high voltage switch (IGBT) may form a current path of the trip coil TC when a control voltage is supplied to its control terminal. The trip coil TC may turn off the breaker of a water distribution equipment not shown when a current is supplied. As a result, the single-phase or three-phase power supplied to the loads around the power distribution equipment through the breaker of the power distribution equipment can be cut off.

The bridge diode BD may rectify the alternating-current voltage ACV flowing into the circuit breaker to generate a second direct-current voltage of a high voltage (approximately 220V). The second DC voltage generated in the bridge diode BD may be supplied to both ends of the series circuit of the control high voltage switch (IGBT) and the trip coil TC. The sixth variable resistor VR6 connected between the two input terminals of the bridge diode BD may disperse the amount of current flowing through the bridge diode BD.

The clock generator 200, the transformer TM1, and the switch driver 210 may implement one control voltage step-up circuit. The control boost circuit is connected to a control terminal of the control high voltage switch IGBT according to a logic state of the software trip control signal CSstr from the main MPU 12 of the control module 10 shown in FIG. 1. The control voltage can be selectively supplied. For example, when the software trip control signal CSstr has a low logic, the control booster circuit may supply the control voltage to a control terminal of the control high voltage switch IGBT.

In another embodiment, the control boosting circuit may selectively supply the control voltage to the control terminal of the control high voltage switch IGBT according to the logic state of the composite trip control signal CStr from the blocking accelerator 230. . For example, when the synthesis trip control signal CStr has a low logic, the control booster circuit may supply the control voltage to a control terminal of the control high voltage switch IGBT.

The clock generator 200 may be selectively driven according to the logic state of the software trip control signal CSstr or the composite trip control signal CStr. For example, the clock generator 200 may be driven when the software trip control signal CSstr or the composite trip control signal CStr has a low logic. The driven clock generator 200 can generate a clock signal at a certain frequency (e.g., about 500 MHz). The clock signal generated by the clock generator 200 may be supplied to the primary coil of the transformer TM1.

The transformer TM1 may transform a clock signal from the clock generator 200 to cause the second AC voltage having a low voltage to be induced in its secondary coil. The high logic value of the clock signal may be about 5V of the first DC voltage VCC, while the maximum value of the second AC voltage may be two times higher than the first DC voltage VCC.

The switch driver 210 may generate the control voltage in the DC voltage form from the second AC voltage from the secondary coil of the transformer TM1. In addition, the switch driver 210 may supply the control voltage to the control terminal of the control high voltage switch (IGBT). To this end, the switch driver 210 includes a third diode D3, fourth and fifth capacitors C4 and C5, twenty-first to twenty-fifth resistors R21 to R25, fifth variable resistor VR5 and It may include two differential amplifiers (OP7).

The third diode D3 and the fourth capacitor C4 rectify and smooth the second AC voltage from the secondary coil of the transformer TM1 to generate a third DC voltage. The third DC voltage may have a voltage level approximately two times higher than the first DC voltage VCC.

The fifth variable resistor VR5 and the twenty-first resistor R21 divide the third DC voltage from the cathode electrode of the third diode D3 to generate a divided voltage Can be generated. The first divided voltage may be supplied to the non-inverting terminal (+) of the second differential amplifier OP7.

The 22nd and 23rd resistors R22 and R23 divide the third DC voltage from the cathode electrode of the third diode D3 to generate a minute voltage (hereinafter referred to as a second minute voltage) can do. The second divided voltage may be supplied to the inverting terminal (-) of the second differential amplifier OP7.

The second differential amplifier OP7 differentially-amplifies the first and second divided voltages supplied to its non-inverting and inverting terminals to generate the control voltage having a voltage level approaching the third DC voltage. can do. The level of the control voltage may be determined by a difference between the first and second divided voltages. In other words, the magnitude of the control voltage is determined by the resistance value ratio of the fifth variable resistor VR5 and the 21st resistor R21 and the resistance value ratio of the 22nd and 23rd resistors R22 and R23 Can be determined. As such, the control voltage can be adjusted high or low by adjusting the resistance value of the fifth variable resistor VR5. The 24th and 25th resistors R24 and R25 and the fifth capacitor C5 may serve to stabilize the control voltage which is an output of the second differential amplifier OP7.

The trip coil voltage monitoring unit 220 may sense the magnitude of the second DC voltage supplied to the control high voltage switch IGBT (i.e., the level of the trip coil voltage). In addition, the trip coil voltage monitor 220 may supply a trip coil voltage detection signal Vtss according to the sensed level of the trip coil voltage to the main MPU 12 of the control module 10 shown in FIG. 1. Can be. The trip coil voltage detection signal Vtss may have a low logic when the second DC voltage maintains a normal level (that is, when a second DC voltage of a normal level is supplied to the trip coil TC). have. On the contrary, when the second DC voltage is lower than the normal level (that is, when the second DC voltage having a low level is supplied to the trip coil TC), it may have a high logic. The trip coil voltage monitoring unit 220 may include the 26th and 27th resistors R26 and R27, at least two diodes D4 and D5, and a photo coupler PDC.

The light emitting part of the 26th resistor R26, the at least two diodes D4 and D5, and the photo coupler PDC may be connected in series between both output terminals of the bridge diode BD. The 27th resistor R27 and the light receiving portion of the photocoupler PDC may be connected in series between the first DC voltage line VCC and the ground voltage line GND.

The 26th resistor R26 may lower the second DC voltage applied to the at least two diodes D4 and D5 from the bridge diode BD by a predetermined magnitude. The at least two diodes D4 and D5 may open and close the current path of the light emitting part of the photocoupler PDC according to the magnitude (ie, level) of the second DC voltage output from the bridge diode BD. .

For example, when the second DC voltage output from the bridge diode BD maintains a normal level, the at least two diodes D4 and D5 may form a current path of a light emitting part of the photocoupler PDC. Can be. At this time, the light emitting portion of the photocoupler (PDC) emits light. Accordingly, the light receiving portion of the photocoupler (PDC) that receives the emission light from the light emitting portion is turned on so that the trip logic voltage sensing signal Vtss of low logic is supplied to the main MPU 12 of FIG. Can be. The trip coil voltage detection signal Vtss of the low logic indicates that the trip coil voltage is normally supplied to the control high voltage switch IGBT.

On the contrary, when the second DC voltage output from the bridge diode BD is lower than the normal level, the voltages supplied to the at least two diodes D4 and D5 may also be lowered. As such, the at least two diodes D4 and D5 may open the current path of the light emitting part of the photo coupler PDC. At this time, the light emitting portion of the photocoupler (PDC) can not emit light. Accordingly, the light receiver of the photo coupler PDC which is turned off may supply the trip coil voltage detection signal Vtss of the high logic to the main MPU 12 of FIG. 1. The trip logic voltage detection signal Vtss of the high logic indicates that the trip coil voltage is abnormally supplied to the control high voltage switch IGBT.

The trip accelerator 230 may generate the clock generator before the software trip control signal CSstr from the main MPU 12 of the control module 10 is enabled (ie, has low logic). The synthesis trip control signal CStr supplied to the 200 may be enabled in a low logic state in advance. As such, the control high voltage switch IGBT can be turned on within a short time from the point of occurrence of excessive arc flash above the threshold trip level.

For example, the software trip control signal CSstr output from the main MPU 12 may be enabled after a time elapsed of at least 0.5 to 2.5 msec from the time of occurrence of excessive arc flash above the threshold trip level Vcts. . As such, the control high voltage switch IGBT can also be turned on after a time elapsed of at least 0.5 to 2.5 msec from the time of occurrence of excessive arc flash above the threshold trip level Vcts. However, the trip accelerator 230 that enables the composite trip control signal CStr before the software trip control signal CSstr is enabled (ie, has low logic) is equal to or greater than a threshold trip level. The control high voltage switch IGBT can be turned on within a time of 0.5 msec from the time of occurrence of excessive arc flash. To this end, the trip acceleration unit 230 includes a second comparator OP6, first to third smoothed trigger inverters INV1 to INV3, third to fifth transistors Q3 to Q5, and seventeenth to twentieth And resistors R17 to R20.

The second comparator OP6 may be one of the point arc detection signals Vpas and the loop arc detection signal Vlas from the optical sensing module 30 (preferably, the loop arc detection signal Vlas). ) And the threshold trip level Vcts from the trip level setting unit 24. In addition, the second comparator OP6 may input the loop arc detection signal Vlas on its inverting terminal (−). ) And the threshold trip level Vcts on its non-inverting terminal + to generate the hardware trip control signal CShtr The hardware trip control signal CShtr is used to detect the loop arc. When the voltage of the signal Vlas is not lower than the threshold trip level Vcts, it may be enabled in a low logic state The hardware trip control signal CShtr may generate an excessive arc flash above a threshold trip level. , remind The hardware trip control signal CShtr may be enabled at a time earlier than the software trip control signal CSstr. For example, the hardware trip control signal CShtr may be enabled within 0.5 msce from the time of occurrence of an excessive arc flash above a threshold trip level. Can be enabled.

The first smit trigger inverter INV1, the seventeenth and eighteenth resistors R17 and R18, and the third transistor Q3 are connected from the main MPU 12 of the control module 10 shown in FIG. 1. The software trip control signal CSstr may be buffered. The seventeenth resistor R17 may limit a current supplied to the base electrode of the third transistor Q3. The 18th resistor R18 may serve as a pull-up resistor for the third and fourth transistors Q3 and Q4.

The second smit trigger inverter INV2, the nineteenth and eighteenth resistors R19 and R18 and the fourth transistor Q4 receive the hardware trip control signal CShtr from the second comparator OP6 Can be buffered. The nineteenth resistor R19 may limit the current supplied to the base electrode of the fourth transistor Q4.

The first and second summing trigger inverters INV1 and INV2, the seventeenth to the nineteenth resistors R17 to R19 and the third and fourth transistors Q3 and Q4 may constitute an AND-gate. have. This AND-gate AND-logic-computes the hardware trip control signal CShtr from the second comparator OP6 and the software-like trip control signal CSstr from the main MPU 12, So that the control signal CStr is generated.

The third smit trigger inverter INV3, the twentieth resistor R20, and the fifth transistor Q5 are in a logic state of the trip prohibition control signal CStrp from the main MPU 12 of FIG. 1. Accordingly, the hardware trip control signal CShtr supplied to the AND gate from the second comparator OP6 may be selectively blocked. For example, when the trip prohibition control signal CStrp is enabled in a low logic state (that is, when a prohibit interrupt command is input or the power distribution facility is in a service mode), the third limit trigger inverter The hardware trip control signal CShtr supplied to the AND gate from the second comparator OP6 may be blocked by the INV3, the twentieth resistor R20, and the fifth transistor Q5. .

Referring back to FIG. 1, the first optical alarm unit 42 responds to a service mode alarm signal, an online mode alarm signal, and a trip alarm signal from the main MPU 12 of the control module 10. Lamp, online mode alarm light and trip alarm light can be selectively lit. The service mode alarm signal and the online mode alarm signal may be enabled complementarily to each other. As such, the service mode alarm and the on-line mode alarm can be complementarily turned on each other. The trip alarm signal may be enabled when power shutdown is performed, that is, when the trip coil is driven by the trip coil drive unit 40. As such, the trip alarm or the like can be turned on while the power shutdown is being performed.

The second optical alarm unit 44 can be turned on and off in response to a door alarm signal and an access alarm signal from the sub MPU 14 of the control module 10 such as a door open alarm, have. The door alarm signal may be enabled while the door of the water distribution facility is open. As such, the door open alarm and the like can be turned on while the door is opened. The access alarm signal may be enabled while the door of the water distribution facility is open. Also, the access alarm signal may be enabled at different times depending on the access distance of the manager or operator to the access sensor while the door open alarm signal is enabled. For example, the shorter the access distance of the manager or operator to the access sensor is, the shorter the enable period of the access alarm signal becomes. As a result, the access status alarms and the like can be rapidly blinked gradually as the approach distance of the manager or the operator to the access sensor becomes short.

The LED display 50 may indicate the status of each of the components in the power distribution facility in response to LED drive control signals from the FPGA 16 of the control module 10. [ The LEDs included in the LED display unit 50 may be turned off when the designated operation is not performed or when no driving power is supplied. In addition, the LEDs included in the LED display unit 50 may be continuously lit green or red when the corresponding devices perform prescribed operations. The LEDs in the LED display unit 50 are input of a prohibition command, a trip command, and a reset command through the operation unit 20 and the remote receiver 22, the driving state of the optical sensors in the light sensing module 30, and the The driving state of the hall sensors in the current sensing module 32, whether or not the trip level is set, an online and service mode, a trip coil voltage state, a trip / bit trip state, and a water distribution state of a phase current may be displayed.

The voice output unit 52 may output a voice synthesis message from the FPGA 16. The voice synthesis message may include a voice message for notifying the opening of the door, a voice message for notifying the access level of the manager or the operator, a voice message for notifying the power cutoff (that is, the driving state of the trip coil), and the like.

The screen display unit 54, under the control of the sub-MPU 14 of the control module 10, the year and time currently set in the power distribution equipment, the setting of the optical sensors in the light sensing module 30, the current The setting of the current sensors in the sensing module 24, the command input setting through the operation unit 20 and the remote receiving unit 22, the setting of the trip coil, trip occurrence information, trip level and communication related setting can be displayed. have. The image displayed on the screen display unit 54 can be switched each time the setting button in the operation unit 20 is pressed. Also, the image displayed on the screen display unit 54 can be automatically switched every time an event is generated. In addition, the image displayed on the screen display unit 54 can be scrolled up and down as the up / down button in the operation unit 20 is pressed. The screen display unit 54 may include any one of flat panel display devices such as an LCD (Liquid Crystal Display) device and an OLED (Organic Light Emitting Display) device.

The control module 10 is configured to detect the arc sense signals from the light sensing module 30, the phase current sense signals from the current sensing module 32 and the threshold trip level from the trip level setting unit 24 The operation of the trip coil drive unit 40 can be controlled. Specifically, the control module 10 checks whether the arc flash is included in the loop arc detection signal Vlas from the loop light detection unit 110 of the light detection module 30 to determine the arc flash. It can be checked first. In other words, when the level of the loop arc detection signal Vlas corresponds to at least the minimum arc detection level (eg, '1' when the maximum arc detection level is set to '100'), the control module 10 may primarily determine that an arc flash has occurred in any one of the plurality of storage spaces in the power distribution facility. In addition, the control module 10 may secondaryly check whether one of the first to fifth point arc detection signals Vpas1 to Vpas5 is included in the light sensing module 30. have. In the secondary inspection, if any one of the first to fifth point arc detection signals Vpas1 to Vpas5 has a magnitude greater than or equal to the minimum arc detection level, the control module 10 may control the plurality of control units within the power distribution facility. It can be ascertained that an arc flash has occurred in either of the storage spaces. For example, if the magnitude of the first point arc detection signal Vpas1 is equal to or greater than the minimum arc detection level, the control module 10 may determine that an arc flash has occurred in the first storage space of the power distribution facility. have. As another example, when the magnitude of the fifth point arc detection signal Vpas1 is equal to or greater than the minimum arc detection level, the control module 10 may determine that an arc flash has occurred in the fifth storage space of the power distribution facility. . On the contrary, when none of the first to fifth point arc detection signals Vpas1 to Vpas5 falls below the minimum arc detection level Vmadl, the control module 10 may determine the arc flash determined primarily. Can be regarded as an error. When the generation of the arc flash is confirmed in this way, the control module 10 may determine whether an emergency situation occurs by checking whether the size (or intensity) of the determined arc flash is lower than the threshold trip level Vcts. In this case, when the determined arc flash does not correspond to an emergency situation, the control module 10 may determine the occurrence number, duration, and average size of the determined point arc detection signal and the latest predetermined period of arc flash obtained therefrom. Or intensity) can be calculated. In addition, the control module 10 calculates the peak value of the three-phase current that is distributed based on the three phase current sensing signals scanned from the current detection module 32 and the three-phase current sensing signals obtained during a recent period of time, The frequency, the kurtosis, the distortion, the rms value, and the standard deviation, and calculate the load level using those calculated values. The control module 10 checks which of the ranges of the arc load energy ranges of the grade and the calculated load level belongs to a level range of the load level ranges of the grade. To determine if a trip (i.e. power off) is necessary.

The arc pulllash energy scale is divided into the form of assigning '1' to the minimum arc pulllash energy level and '100' to the maximum arc pulllash energy level. Can be classified as a rating. In this case, the calculated arc flash energy may belong to the lower two to four classes of arc pull energy levels of the five arc arc level levels range. This is due to the fact that the boundary between the occurrence of the emergency situation and the non-emergency situation is determined by the critical trip level Vcts. Similarly, the load level scale may be divided into '1' for the minimum load level and '100' for the maximum load level, and the load level ranges may be classified into five classes at 20 level intervals have. As such, the calculated load level may belong to any one of the load level ranges of the five grades.

If the calculated arc pull energy is within the range of the lowest level arc pull energy and the calculated load level is also within the range of the lowest level load level, the control module 10 trips (i.e., , Power off). On the contrary, if the calculated load level falls within at least the lower level load level range, even if the calculated arc pull energy falls within the lowest level arc pull energy level range, then the control module 10 It may be determined that there is a need for a trip (i.e. power off).

If it is determined that an emergency occurs or there is a need for tripping, the control module 10 applies the low-logic software-controlled trip control signal CSstr to the trip coil drive unit 40, (TC) can be driven. As a result, a breaker (not shown) is turned off and power can be cut off.

In addition, the control module 10 is based on the access distance data from the approach detection unit 34 and the door detection signal from the door detection unit 36 open and close state and the operator of the door of the power distribution equipment Alternatively, the manager may visually notify the access status of the manager through the second optical notification unit 44. In addition, the control module 10 can control operations according to commands of an administrator or an operator input through the operation unit 20 and the remote receiving unit 22. For example, a reset operation in accordance with a reset command, a switching of online / service mode according to a mode switching instruction, a forced drive of a trip coil in response to a trip command, a drive of a trip coil in response to a prohibition command, The switching / scrolling operation of the display image on the screen display section 54 according to the down commands can be performed under the control of the control module 10. [ In addition, the control module 10 may include the light sensing module 30, the current sensing module 32, the approach sensing unit 34, the door sensing unit 36, the trip coil driving unit 40, and the like. Whether the normal operation of the trip coil voltage state and the like are visually displayed through the first and second notification unit 42,44, the LED display unit 50 and the screen display unit 54 or the voice output unit 52 can be controlled to be notified acoustically. Furthermore, the control module 10 may transmit the current state of the water distribution equipment to an upper human-machine interface (HMI) or receive control data from a higher-level HMI. The control module 10 may be implemented in a form including at least two MPUs in order to alleviate a large amount of computational processing load caused by the above-described general operation control. For example, as shown in FIG. 1, the control module 10 may include the main MPU 12, the sub MPU 14, the FPGA 16, and the analog multiplexer 18.

The main MPU 12 receives the arc sense signals from the light sensing module 30, the phase current detection signals from the current sensing module 32, and the threshold trip level from the trip level setting unit 24 And can generate the software-controlled trip control signal CSstr for controlling the trip coil drive unit 40 based on the control signal. In addition, the main MPU 12 may control the operations according to a command of an administrator or an operator input through the operation unit 20 and the remote receiving unit 22. For example, a reset command may be performed. According to the reset operation, the on-line / service mode switching according to the mode switching command, the forced driving of the trip coil according to the trip command, the operation of inhibiting the trip coil according to the prohibition command, etc. may be performed. The MPU 12 may control the driving state of the trip coil driving unit 40 and the selection state of the online / service mode to be visually displayed through the first optical notification unit 42. Further, the main The MPU 12 may supply data about the light sensing module 30, the current sensing module 32, and the trip coil voltage state to the FPGA 16. This main MPU 12 is shown in FIG. Pin as shown It may include blocks.

The main MPU 12 shown in FIG. 9 may operate at a rate of 48 MHZ and perform A / D conversion at a rate of 5 MHZ per bit. The main MPU 12 may be connected to the FPGA 16 via a bus line for transferring statuses to the LED display unit 50 and the sub MPU 14. 9, the main MPU 12 may include an A / D converter, a terminal communication unit, a trip control unit, an RTC relay unit, a button input unit, a relay output unit, an LED unit, an FPGA relay unit, and a USB relay unit. have.

The A / D converter may input first to fifth point arc detection signals and loop arc detection signals from the light sensing module 30 through 'SENSORs 1 to 6'. In addition, the A / D converter may receive a remote signal received from the remote receiver 22 through 'MUX1_OUT' and a phase current lamp from the current sensing module 32 through 'MUX2_OUT'. The threshold trip level from 24 and the applied voltage of the control high voltage switch IGBT can be input. The A / D converter can supply a selection signal to the analog multiplexer 18 through 'MUX1_A, B, C' and MUX2_A, B and C 'for inputting signals through' MUX1_OUT 'and' MUX2_OUT ' have.

The terminal communication unit may be used for system setting in a service mode. In addition, the terminal communication unit is connected to the terminal of the personal computer at a communication speed of 115200bps, so that the status of the system can be monitored in the service mode.

The RTC relay unit can read the current time and date through I2C communication with the DS1307.

The trip control unit can check the state of the received remote signal or the mode button inputted through the 'PA6 (ARC DETECT)' and output the trip inhibition control signal (CStrp) through 'PB6 (TRIIP INHIBIT)' . In addition, the trip control unit can output the software-related trip control signal CSstr through 'PB13 (TRIP ENABLE)'.

The button input unit may scan a trip button, a mode button, and a reset button on the manipulation unit 20 through 'TRIP_SW', 'MODE_SW', and 'RESET_SW'.

The relay output unit may output the service mode alarm signal and the online mode alarm signal through 'ONLINE_RELAY' and 'SERVICE_RELAY'. The service mode alarm signal and the online mode alarm signal are complementarily enabled according to the operation of the mode button. Also, the relay output unit may output the trip alarm signal through 'TRIPPED_RELAY'. The trip alarm signal is not enabled during the trip test by the trip button in the service mode.

The LED unit can display the A / D conversion state by turning on or off the LED1 (A / D). The 'LED1 (A / D)' light off indicates a state in which the A / D conversion can not be performed in the current system. Also, the LED unit may indicate that the entire system operates normally by flickering 'LED2 (SYSTEM)' at a cycle of 250 ms.

The FPGA relay unit may exchange data with the FPGA 16 in a bus manner (8 bits and 11 addresses).

The USB relay can be used to delete firmware and download new firmware by a signal input via 'ERASE'.

Referring back to FIG. 1, the sub-MPU 14 stores the door of the water distribution facility based on the access distance data from the approach detection unit 34 and the door detection signal from the door detection unit 36. The opening and closing states of the operator and the access states of the operator or the manager may be visually notified through the second light notification unit 44. In addition, the sub MPU 14 can control the operation according to the command inputted by the manager or the operator through the operation unit 20. [ For example, switching / scrolling operation of the display image on the screen display unit 54 according to setting, canceling and up / down commands may be performed under the control of the sub MPU 14. In addition, the sub MPU 14 is connected to the light sensing module 30, the current sensing module 32, the approach sensing unit 34, the door sensing unit 36, Data on whether the trip coil drive unit 40 is operating normally or not and the operation state thereof can be visually displayed through the screen display unit 54. [ In addition, the sub-MPU 14 may transmit the current state of the water distribution facility stored in the FPGA 16 toward the upper HMI or receive control data from the upper HMI and store it in the FPGA 16. . Such sub MPU 14 may include a pin block diagram as shown in FIG. 10.

The sub-MPU 14 shown in FIG. 10 may operate at a speed of 16 MHz by the RISC method. Also, the sub MPU 14 is implemented as a memory map method, but when the LCD device having a slow operation speed is used as the screen display unit 54, the sub MPU 14 can be switched to a port driven external control. As shown in FIG. 10, the sub MPU 14 may include a key button unit, an HMI communication unit, a door communication unit, a station number dip switch unit, a relay output unit, an LED output unit, an FPGA relay unit, and an LCD relay unit. .

The key button unit is used to control images displayed on a screen display unit (for example, an LCD panel) such as 'KEY_SW1 (DOWN)', 'KEY_SW1 (UP)', 'KEY_SW1 (SET)' and 'KEY_SW1 (CANCLE)'. ', The down, up, set and cancel buttons on the control panel 20 can be scanned.

The HMI communication unit transmits the internal configuration data to the upper HMI by 9600bps by RS485 MODBUS standard 0x03 command. The transmitted data can be formatted according to the 'MODBUS protocol'.

The door communication unit may receive the access distance data and the door detection signal in the form of digital data from the access detection unit 34 and the door detection unit 36 at a speed of 9600 bps in an RS-485 serial communication method. The access and door detection signals may be formatted according to the 'MODBUS protocol'.

The station number dip switch unit can set a slave station number (unique address) that can be used for HMI communication through the operation of SW1 to SW4.

The relay output unit may output the door alarm signal and the access alarm signal through 'DOOR_RELAY' and 'DISTANCE_RELAY'.

The LED output unit may display the door open / close state of the water distribution equipment by turning on or off the 'DOOR_LED'. In addition, the LED output unit may display the approach distance of the manager or the worker in a scrolling manner by adjusting the lighting amount (or lighting length) of 'DISTANCE_LED'.

The FPGA relay unit may take data from the FPGA 16. To this end, the FPGA relay unit may be connected to the FPGA 16 through a port-type bus line (data 8 bits, address 6 bits).

The LCD relay unit may output control signals for driving the screen display unit 54 (eg, an LCD panel) having a 128 * 64 dot.

Returning to FIG. 1, the FPGA 16 stores data processed by the main MPU 12 and the sub MPU 14 and data necessary for controlling the trip coil (for example, a range of arc pull energy of each grade). Table and load level range table for each grade), and a program to be executed by the main MPU 12 and the sub MPU 14. Also, the FPGA 16 can relay bi-directional communication between the main MPU 12 and the sub MPU 14. In addition, the FPGA 16 drives the LED display unit 52 and the voice output unit 54 to process the light sensing module 30 processed by the main MPU 12 and the sub MPU 14, Whether the current detection module 32, the access detection unit 34, the door detection unit 36, the trip coil driving unit 40, and the like are normally operated, and the trip coil voltage status lamp are displayed on the LED display unit 50. ) And the audio output unit 54 to be visually and audibly output. To this end, the FPGA 16 may be configured as shown in FIG.

Referring to FIG. 11, the FPGA 16 may include a dual port memory (hereinafter, referred to as 'DPRAM') 300, first and second access units 310 and 312, and an LED / voice driver 320. have.

The DPRAM 300 includes the optical sensing module 30, the current sensing module 32, and the access sensing unit 34 processed by the main MPU 12 and the sub MPU 14 shown in FIG. 1. ), Whether the door detection unit 36 and the trip coil drive unit 40 are normally operated, and data regarding the trip coil voltage state may be stored. In addition, the DPRAM 300 may store reference data (eg, a class arc full-flash energy level range table and a class load level range table, etc.) necessary for controlling the trip coil. In addition, the DPRAM 300 may store programs to be executed by the main MPU 12 and the sub MPU 14.

The first access unit 310 may be connected to the main MPU 12 shown in FIG. 1 through a first bus line BUS1 and a first control line CSL1. The first bus line BUS1 may include eight data lines and twelve address lines. The first control line CSL1 may include three control lines for transmitting a chip selection signal C_CS, a read control signal C_RD and a write control signal C_WR from the main MPU 12 . When the highest address signal C_AD11 on the top 12 address lines has a value of '0', the first access unit 310 causes the DPRAM 300 to be accessed by the main MPU 12. can do. On the contrary, when the most significant address signal C_AD11 on the 12 most significant address lines has a value of '1', the first access unit 310 is configured such that the LED / voice driver 320 has the main MPU. Can be accessed by (12).

The second access unit 312 may be connected to the sub MPU 14 shown in FIG. 1 through a second bus line BUS2 and a second control line CSL2. The second bus line BUS2 may include eight data lines and six address lines. The second control line CSL2 includes three control lines for transmitting a chip select signal C_CS *, a read control signal C_RD * and a write control signal C_WR * from the sub MPU 14 can do. When the chip select signal C_CS * has a specific logic (eg, '0'), the second access unit 312 may cause the DPRAM 300 to be accessed by the sub MPU 14. Can be.

The LED / voice driver 320 is the optical sensing module 30, the current sensing module 32, and the access sensing unit 34 from the main MPU 12 via the first access unit 310. The data may be input to whether the door detecting unit 36 and the trip coil driving unit 40 are normally operated or operated. The data input operation of the LED / voice driver 320 may be performed when the highest address signal C_AD11 on the 12 address lines of the first address line of the first bus line BUS1 has a value of '1' have. Also, the LED / audio driver 320 allows the input data to be visually and audibly output through the LED display unit 50 and the audio output unit 52 shown in FIG.

Also, the FPGA 16 can relay bi-directional communication between the main MPU 12 and the sub MPU 14. In addition, the FPGA 16 drives the LED display unit 52 and the audio output unit 54 to drive the light sensing modules 30, The normal operation state of the current sensing module 32, the approach sensing unit 34, the door sensing unit 36 and the trip coil drive unit 40 and the trip coil voltage state are detected by the LED display unit 50 ) And the audio output unit 54, as shown in FIG. To this end, the FPGA 16 may be configured as shown in FIG.

Referring back to FIG. 1, the analog multiplexer 18 includes the remote reception signal from the remote receiver 22, the threshold trip level from the trip level setting unit 23, and the current sensing module 32. The phase current sensing signals from the APC 12 may be selectively transmitted to the main MPU 12. The selection operation of the analog multiplexer 18 may be controlled by the logic value of the selection signal from the main MPU 12.

12A to 12C are flowcharts illustrating an operation process of the main MPU illustrated in FIG. 1. The flowcharts of FIGS. 12A-12C will be described in detail in conjunction with the block diagram of FIG. 1.

Referring to FIG. 12A, when starting the blocking control function through the arc pull-monitoring, the main MPU 12 may initialize all the components in the system (step S1). In this initialization step, the main MPU 12 may set the online mode. The main MPU 14 may then check which one of the task interrupts has occurred. For example, the main MPU 12 may check whether either a 500 ms or 1 sec task interrupt has occurred (steps S2 and S3). When no task interrupt occurs in the steps S2 and S3, the main MPU 12 scans the buttons on the operation unit 20 to check whether there is a button selection by an operator or an administrator, and the remote It may be checked whether there is a remote signal scanned from the receiver 22 (step S4).

If it is checked in step S4 that there is no button selection and there is no scanned remote signal, the main MPU 12 detects the first to fifth point arc detection signals and the loop arc detection from the light sensing module 30. The signal and the three-phase current sensing signal from the current sensing module 32 may be scanned (step S5). Subsequently, the main MPU 12 checks whether an arc flash is included in the loop arc detection signal Vlas from the loop light sensing unit 110 of the light sensing module 30 to determine whether an arc flash is generated. It can be confirmed automatically (step S6). In other words, when the level of the loop arc detection signal Vlas corresponds to at least the minimum arc detection level (eg, '1' when the maximum arc detection level is set to '100'), the main MPU 12 may primarily determine that an arc flash has occurred in any one of a plurality of storage spaces in the water distribution facility.

When it is determined that the arc flash is included in the loop arc detection signal Vlas, the main MPU 12 may include the first to fifth point arc detection signals Vpas1 to ˜5 in the light sensing module 30. Any of Vpas5) may be secondaryly checked whether the arc flash is included (steps S7 to S11). In the secondary inspection, if any one of the first to fifth point arc detection signals Vpas1 to Vpas5 has a magnitude greater than or equal to the minimum arc detection level, the main MPU 12 may determine a plurality of It can be ascertained that an arc flash has occurred in either of the storage spaces. For example, if the magnitude of the first point arc detection signal Vpas1 is equal to or greater than the minimum arc detection level, the main MPU 12 may be sure that an arc flash has occurred in the first storage space of the power distribution facility. have. As another example, when the magnitude of the fifth point arc detection signal Vpas1 is equal to or greater than the minimum arc detection level, the main MPU 12 may determine that an arc flash has occurred in the fifth storage space of the power distribution facility. . In contrast, when none of the first to fifth point arc detection signals Vpas1 to Vpas5 falls short of the minimum arc detection level Vmadl, the main MPU 12 may determine the arc flash determined primarily. Can be regarded as an error. In this case, the main MPU 12 may return to the step S2.

In the second arc full lash inspection, the determined point arc detection signal (eg, the first point arc detection signal Vpas1) among the first to fifth point arc detection signals Vpas1 to Vpas5 is determined. If it is determined that the arc flash is included, the main MPU 12 may check whether the current operation mode is the online mode (step S12). At this time, if the current operation mode is the online mode, the main MPU 12 may determine whether an emergency situation occurs by checking whether the determined point arc detection signal Vpas is lower than the threshold trip level Vcts ( Step S13).

In the step S13, when the confirmed point arc detection signal Vpas is lower than the threshold trip level Vcts, the main MPU 12 performs the determined point arc detection signal and the arc of the latest predetermined period obtained therefrom. The arc full energy level may be calculated based on the number of flash occurrences, the duration, and the average size (or intensity) (step S14). In addition, the main MPU 12 is the peak value of the three-phase current that is multi-distributed based on the three-phase current sensing signals scanned several times from the current detection module 32 and the three phase current sensing signals obtained during the recent predetermined time The peak frequency, the kurtosis, the skewness, the rms value, and the standard deviation can be calculated, and the load levels can be calculated using the calculated ones (step S15). Subsequently, the main MPU 12 determines whether the calculated arc pull-flash energy level belongs to one of the graded arc pull-flash energy ranges and the calculated load level belongs to one of the graded load level ranges. In operation S16, it may be determined whether there is a need for a trip (power off).

If the determined point arc detection signal Vpas has a value greater than or equal to the threshold trip level Vcts in step S13 or if it is determined that there is a need for a trip (power off) in step S16, The MPU 12 supplies the software trip control signal CSstr in a low logic state to the trip coil drive unit 40 to cause the trip coil drive unit 40 to drive the trip coil TC. (Step S17). In this case, a circuit breaker (not shown) is turned off by the trip coil (TC) to cut off the power distributed several times. In addition, the main MPU 12 is the point light detection unit (for example, the first storage space) installed in the storage space (eg, the first storage space) of the power distribution equipment corresponding to the confirmed point arc detection signal The first LED LD1 in the first point light sensing unit 100A may be controlled to blink slowly so that the generation space of the arc flash can be easily identified. In addition, the main MPU 12 may start counting the trip period. In addition, the main MPU 12 may visually alert that the trip coil TC is driven by turning on the trip state indicator included in the first optical alarm unit 42.

 After performing step S17 or when it is determined that there is no need for a trip (power off) in step S16, the main MPU 12 has a trip / bit trip state and the confirmed point arc detection signal Vpas. And the three phase current sensing signals in the FPGA 16. In addition, the main MPU 12 may update the number of times, the duration and the average magnitude (intensity) of the arc flash stored in the FPGA 16 (step S18).

If it is checked in step S12 that the current mode is not the online mode, the main MPU 12 may determine that the current mode is a service mode. At this time, the main MPU 12 is in the receiving space (for example, the first storage space) of the power distribution equipment corresponding to the point arc detection signal (Vpas) confirmed to the terminal, such as a personal computer connected to the terminal communication unit It is possible to notify the occurrence of the arc flash of (S19 step).

On the other hand, if the 1sec task interrupt is generated in step S3, the main MPU 12 scans the threshold trip level Vcts from the trip level setting unit 24 to change the threshold trip level Vcts. You can check if there was any. In addition, if the currently scanned threshold trip level has changed by at least 20 levels compared to the previously scanned threshold trip level Vcts, the main MPU 12 may request a confirmation of the changed threshold trip level Vcts. Notification to the manager or operator audibly and / or visually through the path of the FPGA 16 and voice output 52 and / or the path of the FPGA 16, sub-MPU 14 and screen display 54 Can be (step S20). Subsequently, the main MPU 12 may read the current time and date through I2C communication with the DS1307 and update the actual time stored in the FPGA 16 using the read current time and date (step S21). ).

If it is checked in step S2 that the 500 ms task interrupt has occurred, as shown in FIG. 12B, the main MPU 12 checks whether the trip coil TC is driven, and the power distribution facility is currently tripped. It may be determined whether or not the state (that is, power off state) (step S22). If it is determined that the trip coil TC is driven, the main MPU 12 may determine whether the reference trip period has elapsed by checking whether the currently counted trip period has reached the reference trip period. Step S23). The reference trip period is a sufficient time required for the power distribution elements in the corresponding storage space of the power distribution facility to be stabilized, and may be set differently according to the specification of the power distribution facility. If the trip coil TC is not driven in step S22 or if the reference trip period has not elapsed in step S23, the main MPU 12 may return to step S2. .

On the contrary, if it is determined that the reference trip period has elapsed in step S23, the main MPU 12 supplies the software trip control signal CSstr of the high logic state to the trip coil driving unit 40. Thus, the trip coil driving unit 40 stops the driving of the trip coil TC (step S24). At this time, a circuit breaker (not shown) is turned off to resume power distribution. In addition, the main MPU 12 may visually notify that the trip coil TC is not driven by turning off the trip state indicator included in the first optical alarm unit 42.

In addition, the main MPU 12 checks the logic state of the trip coil voltage detection signal Vtss from the trip coil voltage monitoring unit 220 of the trip coil drive unit 40 to supply the trip coil voltage normally. It can be determined whether or not (step S25). At this time, when it is determined that the trip coil voltage is normally supplied, the main MPU 12 controls the display unit 50 via the FPGA 16 so that the trip coil LED in the LED display unit 50 is turned off. To be. On the contrary, if it is determined that the trip coil voltage is abnormally supplied (that is, the low trip coil voltage is supplied), the main MPU 12 receives the display unit 50 via the FPGA 16. ) To cause the trip coil LED in the LED display unit 50 to light green.

In addition, the main MPU 12 determines whether the loop arc detection signal Vlas and the first to fifth point arc detection signals Vpas1 to Vpas5 from the light sensing module 30 are initialized (that is, Or less than the minimum arc detection level Vmadl) (step S26). At this time, if it is determined that both the loop arc detection signal Vlas and the first to fifth point arc detection signals Vpas1 to Vpas5 are initialized, the main MPU 12 may determine that the light sensing module 30 All of the first LEDs LD1 in the loop and point light sensing units 110 and 100A to 100E may blink rapidly. In addition, the main MPU 12 causes the loop and point light sensor LEDs in the LED display unit 50 to emit red light via the FPGA 16 such that the loop and point arc detection signals Vpas1 ˜1 are used. Vpas5, Vlas) will indicate that all have been initialized.

Subsequently, the main MPU 12 may scan three phase current sensing signals from the current sensing module 32 and supply the values of the scanned phase current sensing signals to an automatic voltage regulator (not shown) (step S27). ). In addition, the main MPU 12 may scan the output signal of the remote receiver 22 (step S28). In addition, the main MPU 12 may check the communication enabled state with the terminal connected to the terminal communication unit (step S29). After performing step S29, the main MPU 12 may return to step S2.

Meanwhile, if it is checked in the step S4 that there is a button selection or the scanned remote signal, as shown in FIG. 12C, the main MPU 12 causes the selected button or the scanned remote signal to trip, or prohibit. It may be checked whether one of the command, the mode command, and the reset command corresponds (steps S30 to S33). At this time, if it is determined that the selected button or the scanned remote signal does not correspond to any one of a trip command, a prohibition command, a mode command, and a reset command, the main MPU 12 may return to the step S2. .

If it is determined in step S30 that the selected button or the scanned remote signal corresponds to a trip command, the main MPU 12 checks whether a current service mode flag is set to determine whether the current operation mode is a service mode. It can be confirmed (step S34). If it is determined that the current operation mode is the service mode, the main MPU 12 may determine the logic state of the software trip control signal CSstr supplied to the trip coil drive unit 40 for a predetermined period (eg, For example, approximately 2 sec) is maintained to stop the driving after the driving coil TC is driven for a predetermined time. At this time, the breaker (not shown) is turned on so that the distribution of power is cut off. In addition, the main MPU 12 may visually notify that the trip coil TC is driven by turning on the trip state indicator included in the first optical alarm unit 42. In addition, the main MPU 12 controls the LED display unit 50 via the FPGA 16 to light up the trip LED of the LED display unit 50 in red so that the trip state is determined by the LED display unit ( 50). On the contrary, if it is determined in step S34 that the current mode is the online mode, the main MPU 12 transmits an error message that the forced trip operation cannot be performed in the online mode to the terminal connected to the terminal communication unit. After that, the process may return to step S2.

If it is determined in step S31 that the selected button or the scanned remote signal corresponds to a prohibition command, the main MPU 12 performs the trip prohibition control signal trip prohibition control signal trip coil drive unit 40 of low logic. The driving of the trip coil TC by the hardware trip control signal CShtr may be prevented (step S36). After performing step S36, the main MPU 12 may return to step S2.

If it is determined in step S32 that the selected button corresponds to the mode command, the main MPU 12 sets the reset of the set of the online and service mode flags instead of the reset of the online and service mode flags. Are switched to each other (S37). After performing step S37, the main MPU 12 may return to step S2.

For example, when the current online mode flag is set, the main MPU 12 may set the service mode flag instead of the online mode flag so that the service mode is set. In addition, the main MPU 12 may light the service mode alarm light instead of the online mode alarm light in the first optical alarm unit 42. In addition, the main MPU 12 may light the service LED green instead of the online LED on the LED display 50 via the FPGA 16.

Alternatively, when the current service mode flag is set, the main MPU 12 may set the online mode flag instead of the service mode flag so that the online mode is set. In addition, the main MPU 12 may light the online mode alarm light instead of the service mode alarm light in the first optical alarm unit 42. In addition, the main MPU 12 may turn on the green LED instead of the service LED on the LED display unit 50 via the FPGA 16.

If it is determined in step S33 that the selected button or the scanned remote signal corresponds to a reset command, the main MPU 12 determines that the determined point arc detection signal Vpas is still higher than the minimum arc voltage level. It may be determined whether the arc flash continues to be generated by checking whether it is maintained (step S38). If it is determined in step S38 that generation of the arc flash does not continue, the main MPU 12 may return to step S1 to perform an initialization operation. On the contrary, if it is determined that generation of the arc flash continues in step S38, the main MPU 12 may receive an error indicating that initialization due to the reset command cannot be performed due to the generation of the arc flash. Messages to the manager or operator audibly and / or visually through the path of the FPGA 16 and voice output 52 and / or the path of the FPGA 16, the sub MPU 14 and the screen display 54. You can notify.

FIG. 13 is a flowchart for describing an operation of a sub MPU illustrated in FIG. 1. The flowchart of FIG. 13 will be described in detail in conjunction with the block diagram of FIG. 1.

Referring to FIG. 13, the sub-MPU 14 may initialize the second optical alarm unit 44 and the screen display unit 54 when starting the blocking control function through the arc pull-lash monitoring (step S1). ). In this initialization step, the sub-MPU 14 may turn off both the door open alarm light and the access state alarm light in the second optical alarm unit 44. In addition, the sub-MPU 14 may display an initial image on the screen display unit 54. Subsequently, the sub-MPU 14 may check whether any one of 100 ms, 200 ms, 500 ms, and 1 sec task interrupts has occurred (steps S50 to S51).

If it is checked in step S51 that the 100ms task interrupt is generated, the sub-MPU 14 may check whether data including a unique station number and a specific command is received from an upper HMI (step S55). If it is confirmed that data including the unique station number and the specific command have not been received, the sub-MPU 14 may return to step S51. On the contrary, if it is confirmed that data including the unique station number and a specific instruction has been received, the sub-MPU 14 sends the data related to the arc pull-monitoring state and the cutoff control state stored in the FPGA 16 to the higher level. Can be transferred to the HMI (Step S56). After performing step S56, the sub MPU 14 may return to step S51.

In step S52, the sub-MPU 12 stores the door in the second optical alarm unit 44 according to the door detection signal and the access distance data input from the door and the access detecting units 36 and 34. The on / off of the open alarm light and the off / flash of the approach state alarm light may be performed (step S57). For example, if the door detection signal has a logic value (eg, '0') indicating the closed state of the door, the sub MPU 14 turns off both the door open alarm light and the access state alarm light. You can. In addition, the sub MPU 14 may record the door closed state and the approach distance initial value to the FPGA 16. Then, both the door LED and the approach distance LED on the LED display 52 may be lit in green. The approach distance initial value may be '0'. Alternatively, if the door detection signal has a logic value (eg, '1') indicating an open state of the door, the sub-MPU 14 turns on the door open alarm light and the FPGA ( The door opening state may be recorded in 16) so that the door LED on the LED display unit 52 is turned on in red. Accordingly, the open state of the door can be visually displayed. In addition, the sub-MPU 14 may be turned off / flashing of the approach state alarm of the second light alarm unit 44 according to a logic value of the approach distance data (ie, access distance data of an administrator or an operator). The green / red lighting of the approach distance LED on the LED display unit 52 may be controlled to visually display whether the manager or the worker approaches and the approach distance. Specifically, if the approach distance data has an initial value (for example, '0'), the sub-MPU 12 turns off the approach state alarm of the second optical alarm unit 44; In addition, the access distance data of the initial value may be recorded in the FPGA 16 to indicate that there is no accessor. Alternatively, if the approach distance data is larger than the initial value, the sub-MPU 14 flashes the approach state alarm of the second optical alarm unit 44 and is larger than the initial value in the FPGA 16. Access distance data can be recorded to visually display the presence of an accessor and the approach distance. The visual display of the approach distance may be performed by turning on and turning a portion of the approach distance LED on the LED display unit 44 corresponding to the logic value of the approach distance data from green to red. After performing step S57, the sub MPU 14 may return to step S51.

If it is determined in step S53 that the 500 ms task interrupt is generated, the sub-MPU 14 may check whether any one of the up, down, set, and cancel buttons on the operation unit 20 is selected ( Step S58 to step S61).

When the up button is confirmed to be selected, the sub MPU 14 may cause the image displayed on the screen display unit 54 to be up-scrolled (i.e., the currently displayed image is replaced with the previous display image) ( Step S62). After performing step S62, the sub MPU 14 may return to step S51.

After performing step S62, the sub MPU 14 may return to step S51. When it is confirmed that the up button is selected, the sub-MPU 14 may cause the picture displayed on the screen display unit 54 to be down-scrolled (that is, the currently displayed picture is replaced with the next picture) (S63). step). After performing step S63, the sub MPU 14 may return to step S51.

After performing step S63, the sub MPU 14 may return to step S51. When it is confirmed that the setting button is selected, the sub-MPU 14 can cause the image displayed on the screen display unit 54 to be switched to the setting image (step S64). After performing step S64, the sub MPU 14 may return to step S51.

If it is confirmed that the cancel button is selected, the sub-MPU 14 may cause the image displayed on the screen display unit 54 to be switched to the initial image (step S65). After performing step S65, the sub MPU 14 may return to step S51.

On the other hand, if it is determined in step S53 that the 1sec task interrupt is generated, the sub-MPU 14 may update the current time and date using the actual time stored in the FPGA 16 (step S66). ). After performing step S66, the sub MPU 14 may return to step S51.

As described above, in a power distribution facility having a power interruption function through the arc pull-lash detection, an arc pull-lash detection in which the amount of environmental arc component light according to the internal illuminance of the power distribution facility may be generated in each storage space. Can be used as an offset correction amount. As such, the arc flash that can be generated in each storage space can be accurately detected. Accordingly, the power can be cut off accurately in response to the arc pull-out, and unnecessary power failure can be prevented.

In addition, generation of the arc flash in each storage space is determined through two inspection processes based on the loop arc detection signal and the point arc detection signal. As such, the occurrence of the arc flash can be detected accurately. Accordingly, the power cutoff can be more accurately performed in response to the arc pulllash.

In addition, the shutoff of the power may be continued in software after the shutdown of the power is initiated in hardware through a comparison of the threshold trip level and the sensed arc flash size. As such, the interruption of power can proceed quickly in the event of an emergency. Accordingly, damage to the water distribution elements in the water distribution facility can be minimized.

What has been described above is only embodiments for carrying out a power distribution facility having a blocking function through arc pull-lash detection according to the present invention. As such, the present invention is not limited to the above-described embodiments, and any person having ordinary skill in the art to which the present invention pertains may vary without departing from the spirit and technical spirit of the present invention as described in the claims below. It should be protected to cover the extent to which changes can be made.

10; A control module 12; Main MPU
14; Sub MPU 16; FPGA
18; An analog multiplexer 20; Control unit
22; Remote receiver 24; The trip level setting unit
30; A light sensing module 32; Current sensing module
34; An approach detection unit 36; Door detection unit
40; Trip coil drive units 42, 44; The first and second light notification units
50; LED display 52; Screen display portion
54; Audio output

Claims (12)

A circuit breaker for selectively blocking power flowing into at least electrical elements in the receiving spaces;
A trip coil drive unit for driving the trip coil of the breaker;
An offset detection unit for detecting illuminance in any one of the storage spaces and supplying the detected illuminance to an arc offset;
At least two point light sensing units configured to apply the arc offset to detect an arc flash generated in each of the storage spaces;
A current sensing module for sensing phase currents flowing through AC voltage lines disposed in the accommodation spaces; And
The occurrence of the arc flash is detected in any of the receiving spaces based on the light sensing signals from the point light sensing unit, and the intensity, duration and the latest fixed duration of the detected arc flash in the corresponding storage space. Calculates the arc full flash energy level using the number of occurrences of?, Calculates a load level based on the phase currents sensed by the current sensing module, and needs a trip based on the arc pull energy level and the load level. And a control module for causing the trip coil drive unit to drive the trip coil of the breaker according to whether or not the trip is determined. The method of claim 1,
A door detecting unit detecting a opening / closing state of the doors of the storage spaces;
An approach distance detecting unit detecting an approach distance of an accessor to the storage spaces; And
Further comprising a display unit for displaying the access status of the accessor,
The control module controls the arc flash detection to display the approach distance detected by the approach distance detection unit through the display unit when confirming the opening of the door from the door open / close detection signal from the door detection unit. High voltage switchgear with blocking function. The method of claim 1,
A trip level setting unit for setting a threshold trip level;
A loop light sensing unit configured to detect the occurrence of the arc flash in all the storage spaces by applying the arc offset; And
And a drive controller for causing the trip coil drive unit to selectively drive the drive coil based on the threshold trip level and the light sensing signal from the loop light sensing unit. High voltage switchgear with cutoff function. 4. The apparatus of claim 3, wherein the control module primarily detects the occurrence of the arc flash in any of the receiving spaces based on the light sensing signal from the loop light sensing unit, wherein the point light sensing units A high voltage switchgear having a blocking function through the arc flash detection, characterized in that the second secondary specification for the receiving space from which the arc flash is generated through the light detection signals from the. 5. The apparatus of claim 4, wherein the control module primarily determines the need for the trip based on the threshold trip level and the light sensing signals from the point light sensing unit, and determines the arc full energy level and the load level. Based on the second determination, the trip coil driving unit selectively drives the trip coil according to the primary determination and the secondary determination. High voltage switchboard. The device of claim 3, wherein the point light sensing unit is:
A first optical sensor detecting an arc component light in the storage space;
A first offset correction unit that corrects a light detection signal from the first optical sensor using the arc offset from the offset detection unit; And
And a first amplifier for amplifying the offset-corrected light sensing signal. The method of claim 6, wherein the point light unit is:
A first LED; And
Under the control of the control module, the flashing period of the first LED is controlled by the arc flash detection, characterized in that it further comprises a first LED driver to indicate whether or not the occurrence of the arc flash in the storage space; High voltage switchgear with function. 4. The loop light sensing unit of claim 3, wherein:
A second optical sensor for sensing the arc component light;
An optical fiber cable for guiding arc component light in the receiving spaces toward the second optical sensor;
A second offset correction unit that corrects a light detection signal from the second optical sensor using the arc offset from the offset detection unit; And
And a second amplifier for amplifying the offset-corrected light sensing signal. 10. The device of claim 8, wherein the point light unit is:
A second LED; And
And a second LED driver configured to control whether a flashing period of the second LED is controlled under the control of the control module to indicate whether the arc flash is generated in any one of the storage spaces. High-voltage switchgear with cutoff through detection. A circuit breaker for selectively blocking power flowing into at least electrical elements in the receiving spaces;
A trip coil drive unit for driving the trip coil of the breaker;
An offset detection unit for detecting illuminance in any one of the storage spaces and supplying the detected illuminance to an arc offset;
At least two point light sensing units configured to apply the arc offset to detect an arc flash generated in each of the storage spaces;
A current sensing module for sensing phase currents flowing through AC voltage lines disposed in the accommodation spaces; And
The occurrence of the arc flash is detected in any of the receiving spaces based on the light sensing signals from the point light sensing unit, and the intensity, duration and the latest fixed duration of the detected arc flash in the corresponding storage space. Calculates the arc full flash energy level using the number of occurrences of?, Calculates a load level based on the phase currents sensed by the current sensing module, and needs a trip based on the arc pull energy level and the load level. And a control module configured to cause the trip coil drive unit to drive the trip coil of the breaker according to whether the trip is determined or not. A circuit breaker for selectively blocking power flowing into at least electrical elements in the receiving spaces;
A trip coil drive unit for driving the trip coil of the breaker;
An offset detection unit for detecting illuminance in any one of the storage spaces and supplying the detected illuminance to an arc offset;
At least two point light sensing units configured to apply the arc offset to detect an arc flash generated in each of the storage spaces;
A current sensing module for sensing phase currents flowing through AC voltage lines disposed in the accommodation spaces; And
The occurrence of the arc flash is detected in any of the receiving spaces based on the light sensing signals from the point light sensing unit, and the intensity, duration and the latest fixed duration of the detected arc flash in the corresponding storage space. Calculates the arc full flash energy level using the number of occurrences of?, Calculates a load level based on the phase currents sensed by the current sensing module, and needs a trip based on the arc pull energy level and the load level. And a control module for causing the trip coil drive unit to drive the trip coil of the breaker according to whether the trip is determined or not. A circuit breaker for selectively blocking power flowing into at least electrical elements in the receiving spaces;
A trip coil drive unit for driving the trip coil of the breaker;
An offset detection unit for detecting illuminance in any one of the storage spaces and supplying the detected illuminance to an arc offset;
At least two point light sensing units configured to apply the arc offset to detect an arc flash generated in each of the storage spaces;
A current sensing module for sensing phase currents flowing through AC voltage lines disposed in the accommodation spaces; And
The occurrence of the arc flash is detected in any of the receiving spaces based on the light sensing signals from the point light sensing unit, and the intensity, duration and the latest fixed duration of the detected arc flash in the corresponding storage space. Calculates the arc full flash energy level by using the number of occurrences of? And a control module for causing the trip coil driving unit to drive the trip coil of the breaker according to whether the trip is determined or not.

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