KR101333609B1 - Liquid crystal display device and method for fabricating the same - Google Patents

Abstract

The present invention provides the same thickness by forming the first and second pixel patterns having different thicknesses on the protective layer in the part where the seal pattern outside the display area is formed to equalize the overall thickness of the material layer laminated on each part. The present invention provides a liquid crystal display device and a method of manufacturing the same, which can prevent cell gap defects generated when the seal pattern is formed.

Description

Liquid crystal display device and method for manufacturing the same {Liquid crystal display device and method for fabricating the same}

1 is a schematic plan view of a general liquid crystal display device.

2A-2E are cross-sectional views, respectively, of the areas labeled A, B, C, D, E in FIG. 1;

3A to 3E are cross-sectional views of liquid crystal display devices according to the present invention, and cross-sectional views of portions corresponding to areas A, B, C, D, and E shown in FIG.

4A and 4B are plan views schematically illustrating only portions in which a seal pattern and first and second pixel patterns formed thereunder are formed in the liquid crystal display according to the present invention.

5 is a cross-sectional view of a portion of a pixel area including a thin film transistor in a display area in the liquid crystal display according to the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

111: array substrate 113: gate wiring

114: common wiring 127: data wiring

142: pixel electrode 146: second pixel pattern

161: color filter substrate 181c, 181d: third, fourth seal pattern

AA: display area P: pixel area

NA: Non-display area Tr: Thin film transistor

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having a uniform cell gap through step compensation in a low cell gap structure, and a manufacturing method thereof.

Recently, as the information society has evolved rapidly, the necessity of a flat panel display having excellent characteristics such as thinning, light weight, and low power consumption has emerged.

Such a flat panel display may be divided according to whether it emits light or not. A light emitting display is one that displays an image by emitting light by itself, and a display is performed by displaying an image using an external light source. It is called a display device. The light emitting display includes a plasma display panel, a field emission display, an electro luminescence display, and the light receiving display includes a liquid crystal display. display).

Dual liquid crystal display devices are being actively applied to notebooks and desktop monitors because of their excellent resolution, color display, and image quality.

The liquid crystal display device arranges two substrates on which electrodes are formed so that the surfaces on which the two electrodes are formed face each other, injects a liquid crystal between the two substrates, and then applies a voltage to the two electrodes to form a liquid crystal. It is a device that expresses an image by controlling light transmittance by moving molecules.

The liquid crystal panel for a liquid crystal display device includes a process of manufacturing an array substrate in which pixel electrodes and thin film transistors, which are switching elements, are formed for each pixel, and a common electrode and red, green, and blue colors correspond to each pixel as opposed to the array substrate. After injecting the liquid crystal between the process of manufacturing the color filter substrate is formed and the array substrate and the color filter substrate produced through the two processes, and then proceeds to a series of bonding process is completed.

FIG. 1 is a schematic plan view of a general liquid crystal display, and FIGS. 2A to 2E are cross-sectional views of regions labeled A, B, C, D, and E in FIG. 1, respectively. In this case, area A represents a portion where the gate wiring in the display area and a patterned spacer formed thereon is formed, and area B represents a portion where the data wiring is formed among portions in which a seal pattern adjacent to the data pad portion is formed, and region C represents a gate pad. The gate wiring is formed among the portions where the seal pattern is formed adjacent to the portion, and the regions D and E represent portions in which the common wiring is formed among the portions in which the seal pattern is formed in the region symmetrical to the side surfaces of the gate and data pad portions.

As shown in the figure, in the liquid crystal display device 1, a plurality of gate pads 47 connected to an external driving circuit are first provided in the non-display area NA formed at an edge of the array substrate 11 as a lower substrate. Gates on which the data pads 48 are formed and data pad portions GPA and DPA are formed.

In addition, a gate line 13 and a data line 27 are formed in the display area AA to be connected to the gate pad 47 and the data pad 48 to cross each other to define a plurality of pixel areas P. Each pixel region P is formed with a thin film transistor Tr connected to the gate line 13 and the data line 27 to serve as a switching element, and each of the thin film transistors Tr and the thin film transistor Tr. The pixel electrode 37 is connected to each pixel area P.

In addition, the gate line 13 is disposed outside the display area AA including the plurality of pixel areas P, that is, the upper side where the data pad part DPA is formed and the left side where the gate pad part GPA is formed. A common wiring (not shown) for applying a common voltage is formed on the common electrode 73 on the color filter substrate 61 positioned on the same layer as ().

On the other hand, the color filter substrate 61 is configured to correspond to the array substrate 11 having the above-described structure, more precisely to the region except for the gate and data pad portions GPA and DPA of the array substrate 11. In addition, a first black matrix 63 is formed on the color filter substrate 61 along the edge of the display area AA, and both ends thereof contact the first black matrix 63. The second black matrix 65 is formed in a lattice form and overlaps the gate and data lines 13 and 27 formed on the substrate 11, and corresponds to each pixel region P. 65, overlapping with the color filter layer 70 of red, green, and blue, a common electrode 73 is formed on the front surface of the lower portion of the color filter layer 70, the second black matrix 65 Correspondingly at predetermined intervals and having a columnar shape It turned the spacer (95) is formed. In this case, the patterned spacer 95 is to maintain a constant gap (cell gap) between the color filter substrate 61 and the array substrate 11.

In addition, a liquid crystal layer (not shown) is formed between the two substrates (11, 61), the liquid crystal layer (not shown) to prevent leakage, the display area for maintaining the cell gap at the edge of the liquid crystal display device The seal pattern 81 is formed outside the AA to surround the display area AA.

In addition, first and second alignment layers 50 and 77 are formed on top of each of the substrates 11 and 61 to induce consistent initial alignment of the liquid crystal molecules in the liquid crystal layer (not shown).

In the liquid crystal display device 1 having such a configuration, when looking at the cross-sectional structure of the portion indicated as A, B, C, D, and E in FIG. When the seal pattern 81 is formed on the generated portion and these two substrates 11 and 61 are bonded together, a cell gap defect is caused.

In more detail, referring to FIG. 2A, which is a cross-sectional view of part A of which a patterned spacer is formed over the gate wiring in the center of the display area, the cross-sectional structure of the gate wiring 13 and the gate insulating film are sequentially sequentially formed on the array substrate 11. 18, a protective layer 37, a pixel electrode 42 (overlaid with the gate wiring 13 to form a storage capacitor), and a first alignment layer 50 are formed, and a color filter corresponding thereto. In the substrate 61, the second black matrix 65, the color filter layer 70, the common electrode 73, the patterned spacer 95, and the second alignment layer 77 are sequentially formed. At this time, each of the material layers formed between the two substrates 11 and 61 is formed by the gate wiring 13 and the common wiring 14 2550 Å, the gate insulating film 18 4,000 Å, the protective layer 37 1500 Å, and the pixel electrode 42, respectively. ) And the pixel pattern 44 (protective layer having a concave-convex surface corresponding to a portion where the seal pattern 81 is formed adjacent to the gate and data pad portions GPA and DPA to increase the bonding force of the seal pattern 81). (37) a plurality of upper portions) 400 mW, the first and second alignment layers 50 and 77, 800 mW, the semiconductor pattern 24 1700 mW, the source and drain electrodes (not shown) and the data line 27 are 2000 mW, the common electrode (73) Assuming that 1500Å, color filter layer 70 12000Å, and the first and second black matrices 63, 65 13000 A, except for the height of the patterned spacer 95 in the above section A, the laminated material layer It can be seen that the total thickness of is 3.655 μm.

On the other hand, referring to Fig. 2B, which is a sectional view of a portion corresponding to the data wiring of the portion B adjacent to the data pad portion, in which the seal pattern is formed, in this portion, the gate insulating film 18 / semiconductor pattern 24 / The data wiring 27, the protective layer 37, the pixel pattern 44, the seal pattern 81, the second alignment layer 77, the common electrode 70 and the first black matrix 63 are stacked. Except for the seal pattern 81a, the total thickness of the laminated material layer is 2.490 μm. If the thickness of the seal pattern 81a is assumed to be the same as the height of the patterned spacer 95, the A, It can be seen that a step of 1.16 µm occurs in two parts of B. Therefore, in this portion B, it can be seen that a constant cell gap is maintained only when the seal pattern 81a is formed to be about 1.165 μm thicker than the height of the patterned spacer of the region A. FIG.

In addition, referring to FIG. 2C, which is a cross-sectional view of a portion corresponding to the gate wiring of the portion C in which the seal pattern is formed adjacent to the gate pad portion, the gate wiring 13 / gate insulating film 18 / protective layer from the bottom to the top thereof. (37) / pixel pattern 44 / seal pattern 81b / second alignment layer 77 / common electrode 73 / first black matrix 63, wherein the seal It can be seen that the total thickness of all the stacked material layers except for the pattern 81 is 2.375 μm. Therefore, it can be seen that a step of about 1.280 μm occurs in the area C based on the area A. Therefore, in this portion C, the height of the patterned spacer 95 in the area A is substantially 1.280 μm. It can be seen that the cell gap is kept constant only by forming the seal pattern 81b thicker.

Also, referring to FIGS. 2D and 2E, which are cross-sectional views, respectively, in which portions of the D and E regions, which are symmetrical to the B and C regions, are formed, respectively, the common wiring ( 14) / gate insulating film 18 / protective layer 37 / seal pattern 81 / second alignment layer 77 / common electrode 73 / first black matrix 63, wherein It can be seen that the total thickness of all the stacked material layers except the seal pattern 81 is 2.335 μm. Therefore, it can be seen that a step of about 1.320 μm occurs in the regions D and E with respect to the region A. Therefore, substantially in the portions D and E, the patterned spacer 95 of the region A is formed. It can be seen that the seal pattern 81 should be formed thicker by about 1.320 μm in height.

It is the seal pattern 81 that maintains the separation gap between the array and the color filter substrates 11 and 61 at the edge portion of the liquid crystal display device having different steps and stacked material layers. 81) it becomes the glass fiber contained in.

However, since the seal pattern 81 is typically formed by dispensing a sealant including glass fibers of the same size for each edge portion, the difference in the steps at the edge portion is ignored and the seal pattern has the same thickness. The cell gap failure has occurred due to the formation of (81).

In recent years, a liquid crystal display device has a trend of manufacturing a liquid crystal layer having a thickness of about 4 μm to about 6 μm and a thickness of about 2 μm to about 4 μm. Increasingly, the ratio of the step difference to the thickness of the liquid crystal layer is increased by the seal pattern 81 formed as the same thickness for all the edge parts, ignoring the step between the display area AA and the outer edge part thereof. The situation is giving.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to prevent cell gap defects caused by edge difference by providing a liquid crystal display device having the same level with respect to the edge portion outside the display area.

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a first substrate having a display area and first to fourth non-display areas defined outside the display area; A gate wiring extending in one direction to the display area on the first substrate; A common wiring formed in the second and fourth non-display areas on the first substrate; A gate insulating film formed on the entire surface of the gate and the common wiring; A data line formed over the gate insulating layer and crossing the gate line in the display area; A protective layer formed over the data line; A plurality of first pixel patterns formed over the passivation layer on the passivation layer, the pixel electrode corresponding to the display area, and on the passivation layer corresponding to the first non-display area; A plurality of second pixel patterns having a thickness different from that of the first pixel pattern on the passivation layer corresponding to the second to fourth non-display areas; A second substrate facing the first substrate; A color filter layer formed on an inner surface of the second substrate; A common electrode formed on the front surface in contact with the color filter layer; The seal pattern formed in contact with the first and second pixel patterns and having the same thickness; The liquid crystal layer may be formed between the first and second substrates in the seal pattern.

In this case, the lower portion of the data line further includes a semiconductor pattern having the same shape as the wiring line and having a predetermined thickness.

The common wiring may have the same thickness as the gate wiring, and the plurality of first pixel patterns may have the same thickness as the pixel electrode.

In addition, the total thickness of each material layer stacked with different components in the first to fourth non-display areas is the same, and the second pixel pattern is equal to the difference between the thickness of the data line and the gate line. The thickness of the second pixel pattern is equal to or less than the thickness of the first pixel pattern. The thickness of the second pixel pattern is equal to the thickness of the gate wiring in the total thickness of the first pixel pattern, the data wiring, and the semiconductor pattern. It is characterized by being subtracted.

A first black matrix formed on an inner surface of the second substrate to correspond to the first to fourth non-display areas, and a second black matrix formed inside the first black matrix to correspond to the gate and data lines; A plurality of patterned spacers further overlapping the second black matrix under the common electrode.

The first and second substrates may further include first and second alignment layers in contact with the liquid crystal layer, respectively, and the first alignment layer formed on the first substrate may correspond to the display area.

The first substrate may include a data pad portion having a data pad connected to the data line in the first non-display area and a gate pad connected to the gate line in the second non-display area. It further comprises a gate pad portion.

The first substrate further includes a thin film transistor connected to the gate line, the data line, and the pixel electrode in a display area.

A liquid crystal display device manufacturing method according to the present invention includes a display area and a gate wiring extending in one direction to the display area on the first substrate on which the first to fourth non-display areas are defined outside the display area; Forming a common wiring in the fourth non-display area; Forming a gate insulating film on the entire surface of the gate and the common wiring; Forming a data line formed over the gate insulating layer to intersect the gate line in the display area; Forming a protective layer on a front surface of the data line; Forming a pixel electrode on the passivation layer corresponding to the display area and a plurality of first pixel patterns corresponding to the first non-display area; Forming a plurality of second pixel patterns having a thickness different from that of the first pixel pattern corresponding to the second to fourth non-display areas on the passivation layer; Forming a color filter layer on an inner surface of a second substrate facing the first substrate; Forming a common electrode on an entire surface of the lower portion of the color filter layer; Forming a seal pattern in contact with the first and second substrates simultaneously with the first and second pixel patterns, the seal pattern having the same thickness; And forming a liquid crystal layer between the first and second substrates inside the seal pattern.

In this case, the common electrode may be formed to have the same thickness as the gate line, and the plurality of first pixel patterns may be formed to have the same thickness as the pixel electrode.

In addition, the total thickness of each material layer stacked with different components in the first to fourth non-display areas may be formed to be the same, and the second pixel pattern may have a difference between the data line and the gate line thickness It is characterized in that it is formed so as to have a thickness that is added to or subtracted from the thickness of the first pixel pattern.

The forming of the data line may further include forming a semiconductor pattern having the same shape as that of the data line under the data line, wherein the thickness of the second pixel pattern is the first pixel pattern. And the total thickness of the data line and the semiconductor pattern to have a value obtained by subtracting the thickness of the gate line.

In addition, a first black matrix formed on the inner surface of the second substrate to correspond to the first to fourth non-display areas, and a second black matrix formed on the inner side of the first black matrix to correspond to the gate and data lines. Steps; Forming a plurality of patterned spacers overlapping the second black matrix under the common electrode; Forming a first alignment layer on the pixel electrode corresponding to the display area; The method may further include forming a second alignment layer under the patterned spacer and the common electrode.

Further, a data pad electrode connected to the data line in the first non-display area and a gate pad electrode connected to the gate line in the second non-display area are formed outside the seal pattern on the first substrate. It further comprises a step.

The method may further include forming a thin film transistor connected to the gate line, the data line, and the pixel electrode in the display area on the first substrate.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

First, the most characteristic part of the liquid crystal display according to the present invention includes a material layer stacked at the same thickness at the edge portions of the four sides where the seal pattern outside the display area is formed, thereby forming the center of the display area where the patterned spacer is formed. By having the same step as compared to the area corresponding to the gate wiring of the same, even if the seal pattern including the glass fiber of the same size as the conventional thickness for all the edge portion to prevent the cell gap failure does not occur.

To this end, the liquid crystal display according to the present invention includes the first pixel pattern having the same thickness as that of the pixel electrode and the second pixel pattern having a thickness thicker than that of the pixel electrode. It is formed in the part formed, It is characterized by the above-mentioned.

In this case, the thickness of the second pixel pattern varies depending on the thickness of the pattern or the material layer disposed below it, and a method of obtaining the thickness of the second pixel pattern will be described later.

Hereinafter, a liquid crystal display having such structural features and a manufacturing method thereof will be described.

3A through 3E are cross-sectional views of liquid crystal display devices according to the present invention, and corresponding cross-sectional views of portions A, B, C, D, and E shown in FIG. Since the planar structure of the liquid crystal display device according to the present invention is the same as the conventional liquid crystal display device, only the cross-sectional structure having a difference point is shown in the drawings. At this time, the same components are given the reference numerals by adding 100 to the conventional components. Further, in the seal pattern, the seal pattern passing through the B region is the first seal pattern 181a, the seal pattern passing through the C region the second seal pattern 181b, and the seal pattern passing through the D and E regions is respectively 3rd and 3rd. Four seal patterns 181c and 181d are defined, and when the first to fourth seal patterns 181a, 181b, 181c and 181d are collectively referred to as a seal pattern 181.

In addition, for convenience of description, it is assumed that each material layer included in the liquid crystal display according to the present invention has the following thickness as an example.

The gate wiring 113 and the common wiring 114 formed on the same layer in the same process are 2550 GPa, the gate insulating film 118 is 4000 GPa, the protective layer 137 is 1500 GPa, the pixel electrode 142 and the first pixel pattern ( 144 (a plurality of upper portions of the protective layer 137 to have a surface of an uneven structure corresponding to a portion where the seal pattern 181 is formed in order to increase the bonding force of the seal pattern 181 formed closest to the data pad portion). Formed pattern) 400 Å, first and second alignment layers 150 and 177 (the first alignment layer 150 is formed on the array substrate 111, and the second alignment layer 177 is formed on the color filter substrate 161). ) Is made of pure amorphous and impurity amorphous silicon formed under the data line 127 by a fabrication process of forming a semiconductor pattern 124 (source and drain electrodes (not shown) and a semiconductor layer (not shown) at the same time. Pattern) is 1700 kHz, the source and drain electrodes (not shown) and the data line 127 are 2000 μs, common electrode 173 is assumed to have a thickness of 1500 μs, color filter layer 170 is 12000 μs, and the first and second black matrices 163 and 165 have a thickness of 13000 μs. Specific thickness above the protective layer so as to have a surface of the uneven structure corresponding to the portion where the second to fourth seal patterns 181b, 181c, and 181d located on the other side of the surface other than the first seal pattern 181a formed adjacent to each other are formed. Pattern formed to have a thickness of 1550Å (varies depending on the thickness of the material layer laminated for each model) when the material layer having the thickness as described above is formed, and a method of obtaining the same will be described later.

First, referring to FIG. 3A, the cross-sectional structure of the region A corresponding to the gate wiring 113 in the display area AA is sequentially examined. The gate wiring 113 and the gate insulating film are sequentially formed between the array substrate and the corresponding color filter substrate. (118) / protective layer 137 / pixel electrode 142 (storage electrode) / first alignment film 150 / second alignment film 177 / patterned spacer 195 / common electrode 173 / color filter layer ( 170) / the second black matrix 165 is formed.

Therefore, the total thickness of each laminated material layer except for the height of the patterned spacer 195 in this A portion is 3.655 mu m.

Meanwhile, referring to FIG. 3B, the cross-sectional structure of the region B corresponding to the data line of the portion overlapping with the first seal pattern 181a formed closest to the data pad portion outside the display area is described. From the 111 to the color filter substrate 161, the gate insulating film 118 / semiconductor pattern 124 / data wiring 127 / protective layer 137 / first pixel pattern 144 / first seal pattern 181a / The second alignment film 177 / common electrode 173 / first black matrix 163 are stacked. Accordingly, in the portion B, except for the first seal pattern 181a, the total thickness of the stacked material layers is 2.490 μm, wherein the thickness of the first seal pattern 181a and the patterned spacer 195 of FIG. Assuming that the heights of) are the same, it can be seen that a step of 1.165 μm occurs in the A and B regions.

Therefore, substantially in this region B, the thickness of the seal pattern 181a should be formed to be about 1.165 mu m thicker than the height of the patterned spacer (195 in FIG. 3A) of region A. FIG.

In addition, referring to FIG. 3C, which is a sectional view of a portion in which the gate wiring of the region C, in which the second seal pattern 181b is formed, is formed adjacent to the gate pad part, the gate wiring from the array substrate 111 to the color filter substrate 161. (113) / gate insulating film 118 / protective layer 137 / second pixel pattern 146 / second seal pattern 181b / second alignment layer 177 / common electrode 173 / first black matrix ( It can be seen that it has a laminated structure of 163, wherein the thickness of all the stacked material layers except for the second seal pattern 181b in the region C is 2.490㎛.

Therefore, it can be seen that a step of about 1.165 μm occurs in the area C based on the area A. Therefore, in this area C, the height of the patterned spacer (195 in FIG. 3A) of the area A is substantially 1.165. It can be seen that the second seal pattern 181b should be formed thicker by about μm.

Also, a region where the third and fourth seal patterns 181c and 181d respectively face the second and first seal patterns 181b and 181a passing through the C region adjacent to the gate pad portion and the B region adjacent to the data pad portion. 3D and 3E, which are cross-sectional views of the upper part of the common wiring 114 in the regions D and E, the common wiring 114 and the gate insulating film 118 from the array substrate 111 to the color filter substrate 161. / Protective layer 137 / second pixel pattern 146 / third or fourth seal pattern 181c or 181d / second alignment layer 177 / common electrode 173 / first black matrix 163 It can be seen that it has a structure, in which the thickness of all the laminated material layer except for the third or fourth seal pattern (181c or 181d) in the D and E region is 2.490㎛.

Accordingly, it can be seen that a step of about 1.165 μm is generated in the D and E regions similarly to the above-described B and C regions on the basis of the region A. Therefore, the patterned spacer of the region A is also substantially applied to these portions. It can be seen that the third or fourth seal pattern 181c or 181d should be formed to be about 1.165 μm thicker than the height of 195 of FIG. 3A.

Therefore, as described above, the pixel electrode (not shown) is disposed under the first seal pattern 181a including the region B formed as a region of the first seal pattern 181a adjacent to the data pad part. Second to fourth seal patterns 181b and 181c having the same thickness t1 and having the same thickness t1, and passing through these areas including other C, D, and E areas. , 181d is formed below the second pixel pattern 146 having a thickness (t2) thicker than the first pixel pattern 144, the material layer all stacked at all edges of the edge of these display areas The thickness of becomes the same.

 Therefore, even when the seal pattern 181 having the same thickness is formed by using the sealant including glass fibers of the same size in each edge portion outside the display area, no cell gap defect occurs in the edge portion.

In this case, except for components formed in common in the B, C, D, and E regions, that is, the gate insulating layer 118, the protective layer 137, the second alignment layer 177, and the common electrode 173, the thickness difference may be reduced. It can be seen that the components having the gate wiring (113 in FIG. 3C) (or common wiring), the data wiring (127 in FIG. 3B), and the first pixel pattern (144 in FIG. 3B). In this case, for convenience of description, the thicknesses of the data line, the semiconductor pattern, and the gate line (including the common line) are defined as t3, t4, and t5, respectively.

In this case, except for the first and second pixel patterns (144 in FIG. 3B and 146 in FIGS. 3C to 3D), the different components in the region B include data wirings (127 in FIG. 3B) and semiconductor patterns (in FIG. 3B). 124) and the sum of these thicknesses (t3 + t4) is 3700 ms.

In addition, a component having a difference from the B region in the C, D, and E regions is a common wiring (114 in FIGS. 3D and 3E) or a gate wiring (113 in FIG. 3C), wherein the common wiring (FIG. 3D, It can be seen that the thickness t5 of 114 in 3e or the gate wiring (113 in FIG. 3c) is 2550 ns, and reflecting this calculation, the first and second pixel patterns (144 in FIG. 3b and 146 in FIGS. 3c to 3d). The difference between the stacked material layers in the region B and the regions C, D, and E, except for 1) is 1150 Å (3700 Å-2550 Å), so that the thickness of the first and second pixel patterns (144 in FIG. 3B and 146 in FIGS. 3C to 3D) is increased. Except for (t1, t2), it can be seen that region B is formed to be about 1150Å thicker than regions C, D, and E.

Therefore, in order to increase the bonding force between the seal pattern 181 and the protective layer 137, if the surface corresponding to the seal pattern 181 is configured to have an uneven structure, the first seal pattern penetrating the B region In the forming of the pixel electrode (not shown), a first pixel pattern (144 of FIG. 3B) having the same material and the same thickness t1 is formed under the 181a, and the C, D, and E regions are formed. A second pixel pattern (3c to 3d) having a thickness t2 of 1150 패턴 thicker than the first pixel pattern (144 in FIG. 3b) is formed in the lower portion of the second through fourth seal patterns 181b, 181c, and 181d that penetrate. It can be seen that by forming 146), the same lamination thickness is achieved in the B, C, D, and E regions.

In summary, the first pixel pattern 144 of FIG. 3B is formed in the lower portion of the first seal pattern 181a adjacent to the data pad part with the same thickness t1 as the pixel electrode (not shown) formed in the display area. The data wiring (127 of FIG. 3B) and the semiconductor pattern below the first pixel pattern (144 of FIG. 3B) may be disposed below the second to fourth seal patterns 181b, 181c, and 181d. (T3 + t4-t5 minus the thickness t5 of the gate wiring (113 in FIG. 3c) (or the common wiring (114 in FIG. 3d, 3e)) from the thickness t3 + t4 of 124 of FIG. By forming the second pixel pattern 146 having a thickness (t2 = t1 + t3 + t4-t5) thicker than), it can be formed to have the same step in each edge portion.

At this time, a plan view showing a part of the liquid crystal display according to the present invention, which briefly shows only the seal patterns 181 (181a, 181b, 181c, and 181d) and the first and second pixel patterns 144 and 146 below. 4A and 4B, the first and second pixel patterns 144 and 146 may have a plurality of comb pattern shapes or a plurality of quadrangles spaced apart from each other by a predetermined interval with respect to the longitudinal direction of the seal pattern 181. It may be formed in various ways, such as a pattern form.

On the other hand, as a modification, the above-described embodiment is characterized by simultaneously patterning a data line (or a source and a drain electrode) and a semiconductor layer (a component constituting a thin film transistor), thereby forming a structure having a semiconductor pattern under the data line. In the liquid crystal display device in which the semiconductor layer and the data line (including the source and drain electrodes) are patterned using different masks, a semiconductor pattern is not formed under the data line.

In this case, except for the first and second pixel patterns in the region B and the regions C, D, and E, there is only a thickness difference between the common wiring and the data wiring, and the common wiring is generally thicker. The region E has a thicker thickness in comparison with the region B, so in this case, the thickness of the same thickness as that of the pixel electrode is below the second to fourth seal patterns passing through these regions for the C, D, and E regions. The second pixel pattern 146 is formed by forming a first pixel pattern and having a thickness difference between the common wiring and the data wiring in a lower portion of the first seal pattern that passes through the region B adjacent to the data pad part. If it is formed can be formed to have the same step for each edge portion.

Next, FIGS. 3A through 3E and 4A and FIG. 4B illustrate a method of manufacturing a liquid crystal display device having the above-described structure, and a cross-sectional view of a portion of a pixel area including a thin film transistor in a display area in the liquid crystal display device according to the present invention. It demonstrates with reference to FIG.

First, in manufacturing the array substrate 111, a first metal material is deposited on the transparent insulating substrate 110 to form a first metal layer (not shown), and then a photoresist having photosensitive characteristics is disposed on the entire surface. After the coating, the photoresist is exposed to light using a mask and developed, the first metal layer (not shown) exposed to the outside of the developed photoresist is etched, and the photoresist is stripped. A plurality of gate lines 113 extending in one direction are formed by patterning the first metal layer (not shown) by performing a mask process including a series of steps, and simultaneously switching regions TrA in each pixel region P. The gate electrode 115 branched from the gate wiring 113 is formed, and the non-display except the portion adjacent to the gate pad part GPA and the data pad part DPA is more accurately outside the display area AA. Station (NA) that is, to form a common wire 114 having the same thickness as the gate wiring 113 in the non-display area (NA) containing the D and E regions.

In addition, a plurality of gate pad electrodes 116 respectively connected to the plurality of gate wires 113 are formed at an outer side of the gate pad part GPA having the seal pattern 181 formed on the leftmost side of the display area AA. To form.

Next, an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the gate wiring 113, the common wiring 114, and the gate electrode 115 to form a gate insulating film 118. And sequentially deposit pure amorphous silicon, impurity amorphous silicon, and a second metal material on the gate insulating layer 118 to form a pure amorphous silicon layer (not shown), an impurity amorphous silicon layer (not shown), and a second metal layer. After forming (not shown), a photoresist is formed on the second metal layer (not shown) to form a photoresist layer (not shown), and the first and second photoresists are subjected to diffraction exposure or halftone exposure. A pattern (not shown) is formed.

Thereafter, the gate is formed by sequentially etching a second metal layer (not shown), an impurity amorphous silicon layer (not shown), and a pure amorphous silicon layer (not shown) exposed to the outside of the first and second photoresist patterns. Each pixel region P is defined on the insulating layer 118 by crossing the gate line 113, and the semiconductor pattern 124 of pure and amorphous silicon patterned in the same shape and the data line 127 are formed thereon. At the same time, in the switching region TrA in the pixel region P, a source drain pattern (not shown) having a triple layer structure connected to the data line 127 and a semiconductor layer of impurity and pure amorphous silicon beneath it. 123 is formed.

In addition, a plurality of data pad electrodes connected to the plurality of data lines 127 are respectively provided on the outer side of the data pad part DPA on which the first seal pattern 181a is to be formed. 128).

Next, ashing is performed to remove the second photoresist pattern (not shown) to expose a portion of the source drain pattern (not shown) below.

Next, the source and drain electrodes 130 spaced apart from each other in the switching region TrA by sequentially etching and removing the exposed source drain pattern (not shown) and a portion of the semiconductor layer 123 made of impurity amorphous silicon thereunder. 133 and a lower portion of the semiconductor layer 123 forming an ohmic contact layer 123b of impurity amorphous silicon and an active layer 123a of pure amorphous silicon.

Next, a protective layer 137 is formed on the entire surface of the data line 127 and the source and drain electrodes 130 and 133, and then a mask process is performed on the protective layer 137 to pattern each switching region. In TrA, the drain contact hole 140 exposing the lower drain electrode 133 is formed.

In this case, gate and data pad contact holes (not shown) for exposing the gate pad electrode 147 and the data pad electrode 148 are also formed in the gate pad part GPA and the data pad part DPA, respectively.

Next, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) over the protective layer 137 having the drain contact hole 140 and a gate and data pad contact hole (not shown). ) Is deposited on the entire surface and patterned by a mask process to form the pixel electrode 142 in contact with the drain electrode 133 through the drain contact hole 140 in each pixel region P. A plurality of comb-shaped or rectangular first pixel patterns 144 spaced apart from each other on the protective layer 137 corresponding to a portion where the first seal pattern 181a adjacent to the data pad portion where the region B is formed is formed. To form.

In this case, in the gate pad part GPA and the data pad part DPA, the gate and data auxiliary contacting the gate pad electrode 116 and the data pad electrode 128 through the gate and data contact holes (not shown), respectively. Pad electrodes 147 and 148 are formed.

Next, a thickness t3 of the sum of the data line 127 and the lower semiconductor pattern 124 compared to the thickness t1 of the first pixel pattern 144 over the pixel electrode 142 and the first pixel pattern 144. After forming a metal material layer having a thickness (t2 = t1 + t3 + t4-t5) that is thicker than the thickness t5 of the gate wiring 113 (or common wiring 114) by + t4 By patterning the second and fourth seal patterns 181b and 181c except for a portion (a region including a region B) in which the first seal pattern 181a near the data pad portion DPA is to be formed. According to the present invention, a plurality of comb-toothed or rectangular second pixel patterns 146 spaced apart from each other are formed on the protective layer 137 of the portion 181d formed (the portions including the regions C, D, and E). The array substrate 111 according to the embodiment is completed.

Meanwhile, in the manufacture of the color filter substrate 161 facing the same, the first black matrix 163 is formed along the edge of the substrate 161 by coating and patterning the black resin on the transparent substrate 161. The second black matrix 165 having a lattice shape is formed inside the first black matrix 163.

Next, a color filter layer 170 including red, green, and blue color filter patterns that are sequentially repeated is formed in the upper portion of the second black matrix 165 and the openings surrounded by the second black matrix 165.

Next, a common electrode 173 is formed by depositing a transparent conductive material on the entire surface corresponding to the color filter layer 170 and the first black matrix 163, and the second black matrix (top) is formed on the common electrode 173. The color filter substrate 161 is completed by forming the columnar patterned spacer 195 in a portion overlapping with the 165 and corresponding to the gate wiring 113 on the array substrate 111. In this case, the height of the patterned spacer 195 is the thickness of the liquid crystal layer in the display area AA, and is about 2 μm to about 6 μm.

In the array substrate 111 and the color filter substrate 161 completed as described above, the surfaces of the array substrate 111 and 161 facing each other, that is, the portion corresponding to the display area AA in the array substrate 111. After the first alignment layer 150 is formed, and the second alignment layer 177 is formed on the entire surface corresponding to the color filter substrate 161, the first and second alignment layers 150 and 150 of the two substrates 111 and 161 are formed. After forming the liquid crystal layer (not shown) between the 177, the seal pattern 181 thicker than the height of the patterned spacer 195 is formed in the portion corresponding to the first and second pixel patterns (144, 146). Then, the two substrates 111 and 161 are bonded together to complete the liquid crystal display device 101 according to the embodiment of the present invention.

In this case, the thickness of the seal pattern 181 is a step difference between the center portion and the edge portion of the display region AA at the height of the patterned spacer 195 in the display region AA (regions A, B, and C). Differences in the areas D and E result in values larger than 1.165 μm in the embodiment of the present invention.

In summary, in the present invention, even when the seal patterns having the same thickness are formed by making the total thicknesses of the stacked material layers in the first to fourth non-display areas of the array substrate on which the seal patterns are formed have the same value. It is characterized by preventing the cell gap failure.

The liquid crystal display according to the present invention manufactured as described above has a structure in which the thicknesses of the stacked material layers are the same for all edge portions outside the display area, and thus, there is an effect of preventing cell gap defect due to the difference in the edge portions. Further, even if a seal pattern having the same thickness is formed, a cell gap defect does not occur due to this, thereby improving yield and finally improving productivity.

Claims (22)

A first substrate having a display area and first to fourth non-display areas defined outside the display area; A gate wiring extending in one direction to the display area on the first substrate; A common wiring formed in the second and fourth non-display areas on the first substrate; A gate insulating film formed on the entire surface of the gate and the common wiring; A data line formed over the gate insulating layer and crossing the gate line in the display area; A protective layer formed over the data line; A plurality of first pixel patterns formed over the passivation layer on the passivation layer, the pixel electrode corresponding to the display area, and on the passivation layer corresponding to the first non-display area; A plurality of second pixel patterns having a thickness different from that of the first pixel pattern on the passivation layer corresponding to the second to fourth non-display areas; A second substrate facing the first substrate; A color filter layer formed on an inner surface of the second substrate; A common electrode formed on the front surface in contact with the color filter layer; A seal pattern formed in contact with the first and second pixel patterns and having the same thickness; A liquid crystal layer formed between the first and second substrates inside the seal pattern And the liquid crystal display device. The method of claim 1, And a semiconductor pattern having the same shape as that of the data wiring and having a predetermined thickness under the data wiring. 3. The method according to claim 1 or 2, And the common wiring has the same thickness as the gate wiring. 3. The method according to claim 1 or 2, And the plurality of first pixel patterns have the same thickness as the pixel electrode. 3. The method according to claim 1 or 2, And a total thickness of each material layer stacked with different components in the first to fourth non-display areas is the same. 6. The method of claim 5, And the second pixel pattern has a thickness that is equal to or less than the thickness of the first pixel pattern by a difference between the thickness of the data line and the gate line. 6. The method of claim 5, The thickness of the second pixel pattern is a value obtained by subtracting the thickness of the gate wiring from the total thickness of the first pixel pattern, the data wiring, and the semiconductor pattern. 3. The method according to claim 1 or 2, A first black matrix formed on an inner surface of the second substrate corresponding to the first to fourth non-display areas, and a second black matrix formed inside the first black matrix to correspond to the gate and data lines; A plurality of patterned spacers overlapping the second black matrix under the common electrode; And the liquid crystal display device. 3. The method according to claim 1 or 2, The first and second substrates further include first and second alignment layers in contact with the liquid crystal layer, respectively. The method of claim 9, And a first alignment layer formed on the first substrate to correspond to the display area. 3. The method according to claim 1 or 2, The first substrate may include a data pad portion having a data pad connected to the data line in the first non-display area and a gate pad connected to the gate line in the second non-display area, outside the seal pattern. Liquid crystal display further comprising a portion. 3. The method according to claim 1 or 2, The first substrate further includes a thin film transistor connected to the gate line, the data line, and the pixel electrode in a display area. A gate wiring extending in one direction to the display area on the first substrate on which the first to fourth non-display areas are defined, and a common wiring to the third and fourth non-display areas; Steps; Forming a gate insulating film on the entire surface of the gate and the common wiring; Forming a data line formed over the gate insulating layer to intersect the gate line in the display area; Forming a protective layer on a front surface of the data line; Forming a pixel electrode on the passivation layer corresponding to the display area and a plurality of first pixel patterns corresponding to the first non-display area; Forming a plurality of second pixel patterns having a thickness different from that of the first pixel pattern corresponding to the second to fourth non-display areas on the passivation layer; Forming a color filter layer on an inner surface of a second substrate facing the first substrate; Forming a common electrode on an entire surface of the lower portion of the color filter layer; Forming a seal pattern in contact with the first and second substrates simultaneously with the first and second pixel patterns, the seal pattern having the same thickness; Forming a liquid crystal layer between the first and second substrates inside the seal pattern Method of manufacturing a liquid crystal display device comprising a. 14. The method of claim 13, And wherein the common electrode is formed to have the same thickness as that of the gate line. 14. The method of claim 13, The plurality of first pixel patterns are formed to have the same thickness as the pixel electrode. 14. The method of claim 13, A method of manufacturing a liquid crystal display device, characterized in that the total thickness of each material layer stacked with different components in the first to fourth non-display areas is the same. 14. The method of claim 13, And the second pixel pattern is formed to have a thickness that is equal to or less than the thickness of the first pixel pattern by a difference between the thickness of the data line and the gate line. 14. The method of claim 13, The step of forming the data line, And forming a semiconductor pattern having the same shape as that of the data line below the data line. The method of claim 18, The thickness of the second pixel pattern is formed to have a value obtained by subtracting the thickness of the gate wiring from the total thickness of the first pixel pattern, the data wiring, and the semiconductor pattern. The method of claim 13 or 18, Forming a first black matrix formed on the inner surface of the second substrate corresponding to the first to fourth non-display areas, and forming a second black matrix inside the first black matrix corresponding to the gate and data lines; ; Forming a plurality of patterned spacers overlapping the second black matrix under the common electrode; Forming a first alignment layer on the pixel electrode corresponding to the display area; Forming a second alignment layer under the patterned spacer and the common electrode; Method of manufacturing a liquid crystal display device further comprising. The method according to claim 13 or 18, Forming a data pad electrode connected to the data line in the first non-display area and a gate pad electrode connected to the gate line in the second non-display area, outside the seal pattern; A method of manufacturing a liquid crystal display device further comprising. The method according to claim 13 or 14, And forming a thin film transistor connected to the gate line, the data line, and the pixel electrode in the display area on the first substrate.

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