KR101332109B1 - Power generating circuit and switching circuit having the same - Google Patents

Abstract

The present invention relates to a power supply circuit and a switching circuit having a power supply circuit, wherein a second control signal is applied to the control terminal, a first control signal is applied to one end, and the first transistor is connected to the output terminal. ; A second transistor to which the first control signal is applied to a control terminal, the second control signal is applied to one end, and the other end thereof is connected to an output terminal; A third transistor in which any one of the control signals is applied to a control terminal and one end of which is grounded; And a fourth MOS transistor, the other one of the control signals being applied to a control terminal, one end of which is connected to the other end of the third MOS transistor, and the other end of which is connected to the output terminal.

Description

Switching circuit with power generation circuit and power generation circuit {POWER GENERATING CIRCUIT AND SWITCHING CIRCUIT HAVING THE SAME}

The present invention relates to a power supply circuit and a switching circuit provided with a power generator circuit.

Recently, in the field of electronics and electronics, the miniaturization of electronic devices and the reduction of power consumption extend the battery duration.

On the other hand, even in the case of parts with relatively low power consumption, since it was necessary to receive a separate power source from the outside, it was difficult to make it on-chip with various closely related parts, and a separate pin for receiving an external power source Since it must be provided, there was a limit to downsizing.

1 is a view schematically illustrating a configuration of a switching circuit according to the prior art.

Referring to FIG. 1, the conventional switching circuit operates by receiving power from the same power source Vs as the power amplifier PA and the switch unit receiving a control signal from a controller such as a chipset. .

However, as illustrated in FIG. 1, when the power amplifier and the switch unit are supplied with power from the same power source Vs, mutual interference occurs between the noise of the power amplifier and the noise of the switch unit. There has been a problem that performance degradation of various devices can be caused.

In addition, when the switch unit is operated by an external power source, there is a problem that unnecessary power consumption occurs because continuous power is supplied regardless of whether the control signal applied to the switch unit is on / off or high / low.

The present invention devised to solve the above problems, an object of the present invention is to provide a power generation circuit for generating a power by receiving a control signal.

In addition, an object of the present invention is to provide a switching circuit with the power generating circuit.

The power generation circuit according to an embodiment of the present invention, which is designed to achieve the above object, is selected from a plurality of control signals output from a chipset, and a first control signal and a second voltage level are respectively determined. A power generation circuit receiving a control signal, comprising: a first transistor having a second control signal applied to a control terminal, a first control signal applied to one end, and the other end connected to an output terminal; A second transistor to which the first control signal is applied to a control terminal, the second control signal is applied to one end, and the other end thereof is connected to an output terminal; A third transistor in which any one of the control signals is applied to a control terminal and one end of which is grounded; And a fourth transistor having another control signal of the control signal applied to the control terminal, one end of which is connected to the other end of the third transistor, and the other end of which is connected to the output terminal.

In this case, when the first control signal or the second control signal is an on signal, a power supply voltage may be output to the output terminal.

In addition, a power supply voltage is output to the output terminal only when the first control signal or the second control signal is an on signal, and zero voltage is output to the output terminal when the first control signal and the second control signal are off signals. Can be output.

In addition, the first transistor, the second transistor, the third transistor and the fourth transistor may be a P-type MOS transistor.

On the other hand, the switching circuit with a power generation circuit according to an embodiment of the present invention, the power generation circuit described above; A switch unit turned on / off according to a control signal; And a power amplifier receiving a control signal.

At this time, the power supply for supplying power to the power amplifier; may further include.

The apparatus may further include a power supply unit supplying power to the power amplifier, wherein the switch unit may receive power generated from the power generation circuit.

Since the power generation circuit of the present invention configured as described above can generate power only by a control signal, it provides a useful effect of miniaturization of various electronic devices.

In addition, since power is generated only when a control signal corresponding to on or high is applied, power consumption may be reduced as compared with the case where the external power is continuously supplied as in the related art.

In addition, the switching circuit with the power generation circuit of the present invention can also be miniaturized than before, and even when the power amplifier and the switch on-chip, the mutual interference between the noise of the power amplifier and the noise of the switch is minimized. Performance degradation of various devices can be minimized.

1 is a view schematically illustrating a configuration of a switching circuit according to the prior art.
2 is a view schematically illustrating a switching circuit according to an embodiment of the present invention.
3 is a circuit diagram schematically illustrating a power generation circuit according to a first embodiment of the present invention.
4 is a circuit diagram schematically illustrating a power generation circuit according to a second embodiment of the present invention.
5 is a circuit diagram schematically illustrating a power generation circuit according to a third embodiment of the present invention.
6 is a circuit diagram schematically illustrating a modification of FIG. 4.
7 is a view illustrating a signal of a power generation circuit input and output terminal according to FIG. 6.
8 is a view illustrating a signal of a power generation circuit input and output terminal according to FIG. 4.

The advantages and features of the present invention and the techniques for achieving them will be apparent from the following detailed description taken in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The present embodiments are provided so that the disclosure of the present invention is not only limited thereto, but also may enable others skilled in the art to fully understand the scope of the invention. Like reference numerals refer to like elements throughout the specification.

The terms used herein are intended to illustrate the embodiments and are not intended to limit the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is to be understood that the terms 'comprise', and / or 'comprising' as used herein may be used to refer to the presence or absence of one or more other components, steps, operations, and / Or additions.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 is a view schematically illustrating a switching circuit according to an embodiment of the present invention.

2, the switching circuit 100 according to an embodiment of the present invention may include a power amplifier 110, a switch unit 120, and a power generation circuit 130.

The power generation circuit 130 receives a control signal generated from the controller 140, which may be implemented by various chipsets, and generates a power voltage VDD supplied to the switch unit 120. can do.

In addition, the power amplifier 110 may receive power from a separate external power source (Vs), and the switch unit 120 may receive power from the power generation circuit 130.

Accordingly, since the switch unit 120 may be driven by receiving power generated from the power generation circuit 130 without a separate external power source, the size of the entire switching circuit 100 may be reduced.

In addition, since the power amplifier 110 and the switch unit 120 are driven by separate power sources, the interference of the noise of the power amplifier 110 and the noise of the switch unit 120 may be minimized. The reliability of can be improved.

3 is a diagram illustrating a power generation circuit 130 according to a first embodiment of the present invention.

Referring to FIG. 3, the power generation circuit according to the first embodiment of the present invention may include two transistors, a ground transistor, a connection transistor, and an output terminal.

Each of the two transistors may include a control terminal and two terminals, and different control signals may be applied to one of the control terminal and the other terminal.

One of the two control signals is applied to the transistor at one end, the other control signal is applied to the control terminal, and the other end may be connected to the output terminal.

One of the control signals is applied to the control terminal of the ground transistor, and one end is grounded.

The other control signal of the control signal is applied to the control terminal of the connection transistor, one end of which is connected to the other end of the ground transistor, and the other end thereof may be connected to the output terminal.

Meanwhile, the two transistors, the ground transistor, and the connection transistor may be implemented as a MOS transistor.

In this case, the MOS transistors may be P-type MOS transistors.

In FIG. 3, the two transistors may be referred to as M1 and M2, the ground transistor may be referred to as M3, and the connection transistor may be referred to as M4.

Meanwhile, referring to FIG. 3, the power generation circuit 130 according to the first embodiment of the present invention may include first to fourth MOS transistors M1 to M4.

The first MOS transistor M1 has a second control signal applied to a gate, a first control signal is applied to a source, a drain is connected to an output terminal, and the second MOS transistor M2 has a gate applied to a gate. The first control signal may be applied, the second control signal may be applied to a source, and the drain may be connected to the output terminal.

In addition, the third MOS transistor M3 may have the second control signal applied to a gate, and the source may be grounded. The fourth MOS transistor M4 may have the first control signal applied to the gate. The source may be connected to the drain of the third MOS transistor M3, and the drain may be connected to the output terminal.

In this case, although not illustrated, a first control signal may be applied to the gate of the third MOS transistor M3 and a second control signal may be applied to the gate of the fourth MOS transistor M4.

In addition, when the first control signal or the second control signal is an on signal, a power supply voltage may be output to the output terminal.

In addition, a power supply voltage is output to the output terminal only when the first control signal or the second control signal is an on signal, and zero voltage is output to the output terminal when the first control signal and the second control signal are off signals. Can be output.

In addition, the first transistor, the second transistor, the third transistor and the fourth transistor may be a P-type MOS transistor.

Vc1 Vc2 OUT H L H L H H L L 0

As illustrated in Table 1, the first control signal Vc1 and the second control signal Vc2 may be H or L. In each case, the power generation circuit 130 according to the first embodiment of the present invention. The principle of generating a power supply voltage will be described below.

First, referring to FIG. 3, when Vc1 is H and Vc2 is L, the first MOS transistor M1 may be turned on and H may be output to the output terminal OUT.

In addition, when Vc1 is L and Vc2 is H, the second MOS transistor M2 may be turned on and H may be output to the output terminal OUT.

However, when both Vc1 and Vc2 are L, both the first and second MOS transistors M1 and M2 are turned off, and L is output to the output terminal OUT.

On the other hand, when Vc1 and Vc2 are L and L, the third MOS transistor M3 and the fourth MOS transistor M4 are turned on, and the output terminal is grounded. When any one of Vc1 and Vc2 becomes H, the output terminal is not grounded. Do not.

Therefore, the output terminal may output H or may be grounded to output zero voltage.

In general, the transistor may leak a minute current even when turned off. Therefore, in the power generation circuit illustrated in FIG. 6, a minute current may leak from the output terminal even if all the control signals are L, thereby causing abnormal operation.

However, as illustrated in FIG. 3, when the third MOS transistor and the fourth MOS transistor are provided, the power generation circuit 130 when one of the control signals is changed from the state of H to all of the control signals to L By quickly removing the residual microcurrent through the ground terminal, only H or 0 can be output to the output terminal.

For convenience of understanding, signals of the power generation circuit input / output terminals are illustrated in FIGS. 7 and 8. 7 is a diagram illustrating signals of the power generation circuit input and output terminal according to FIG. 6, and FIG. 8 is a diagram illustrating signals of the power generation circuit input and output terminal according to FIG. 4.

7 and 8, when Vc1, Vc2, and Vc3 are (L, L, and L), Vout is not completely 0. In the case of FIG. 8, Vc1, Vc2, and Vc3 are (L, L). , L), it can be seen that Vout is completely zero.

4 is a diagram illustrating a power generation circuit 130-1 according to a second embodiment of the present invention, and illustrates a power generation circuit 130-1 that may be applied to three control signals.

Referring to FIG. 4, the power generation circuit 130-1 according to the second embodiment of the present invention may include first to ninth transistors M1 to M9.

In this case, a third control signal is applied to a gate of the first MOS transistor M1, a first control signal is applied to a source, and a second control signal of the second MOS transistor M2 is applied to a gate thereof. The drain of the first MOS transistor M1 may be connected to a source, and the drain may be connected to an output terminal.

In addition, the third MOS transistor M3 has a first control signal applied to a gate, a second control signal is applied to a source, and the fourth MOS transistor M4 has a third control signal applied to a gate. The drain of the third MOS transistor M3 may be connected to a source, and the drain may be connected to an output terminal.

In addition, the fifth MOS transistor M5 has a second control signal applied to a gate, a third control signal is applied to a source, and the sixth MOS transistor M6 has a first control signal applied to a gate. The drain of the fifth MOS transistor M5 may be connected to a source, and the drain may be connected to an output terminal.

In addition, the third control signal may be applied to the gate and the source may be grounded in the seventh MOS transistor M7, and the second control signal may be applied to the gate of the eighth MOS transistor M8. A source may be connected to the drain of the seventh MOS transistor M7. The ninth MOS transistor M9 may be applied with the first control signal to a gate, and the source may be connected to the eighth MOS transistor M8. The drain may be connected to the output terminal.

In this case, although not shown, the first control signal, the second control signal, and the third control signal may be applied to the gates of the seventh MOS transistor M7 to the ninth MOS transistor M9 in different orders. .

In addition, when any one of the first control signal, the second control signal and the third control signal is an ON signal, a power supply voltage may be output to the output terminal.

In addition, a power supply voltage is output to the output terminal only when the first control signal, the second control signal, and the third control signal are on signals, and the first control signal, the second control signal, and the third control signal are turned off. In the case of a signal, zero voltage may be output to the output terminal.

In addition, the first to ninth transistors M1 to M9 may be P-type MOS transistors.

Vc1 Vc2 Vc3 OUT H L L H L H L H L L H H L L L 0

As illustrated in Table 2, the first control signal Vc1, the second control signal Vc2, and the third control signal Vc3 may be H or L. In each case, the second embodiment of the present invention is used. The principle in which the power supply voltage is generated in the power generation circuit 130-1 will be described below.

First, referring to FIG. 4, when Vc1 is H, Vc2 is L, and Vc3 is L, the first and second MOS transistors M1 and M2 may be turned on and the output terminal OUT. H can be output.

In addition, when Vc1 is L, Vc2 is H, and Vc3 is L, the third MOS transistor M4 and the fourth MOS transistor M4 may be turned on and H may be output to the output terminal OUT. Can be.

In addition, when Vc1 is L, Vc2 is L, and Vc3 is H, the fifth MOS transistor M5 and the sixth MOS transistor M6 may be turned on, and H may be output to the output terminal OUT. Can be.

However, when Vc1, Vc2, and Vc3 are all L, the first to sixth MOS transistors M1 to M6 are all turned off, and L is output to the output terminal OUT.

On the other hand, when Vc1, Vc2, and Vc3 are L, L, and L, the seventh MOS transistor M7 to ninth MOS transistor M9 are turned on so that the output terminal out is grounded, and any one of Vc1, Vc2, Vc3 is grounded. If any one is H, the output terminal is not grounded.

Therefore, the output terminal may output H or may be grounded to output zero voltage.

In general, the transistor may leak a minute current even when turned off. Therefore, in the power generation circuit illustrated in FIG. 6, a minute current may leak from the output terminal even if all the control signals are L, thereby causing abnormal operation.

However, as illustrated in FIG. 4, when the seventh to nineth MOS transistors are provided, the power generation circuit 130 when all of the control signals are changed to L when either of the control signals is H By quickly removing the microcurrent remaining in -1) through the ground terminal, only H or 0 can be output to the output terminal.

For convenience of understanding, signals of the power generation circuit input / output terminals are illustrated in FIGS. 7 and 8. 7 is a diagram illustrating signals of the power generation circuit input and output terminal according to FIG. 6, and FIG. 8 is a diagram illustrating signals of the power generation circuit input and output terminal according to FIG. 4.

7 and 8, when Vc1, Vc2, and Vc3 are (L, L, and L), Vout is not completely 0. In the case of FIG. 8, Vc1, Vc2, and Vc3 are (L, L). , L), it can be seen that Vout is completely zero.

FIG. 5 is a diagram illustrating a power generation circuit 130-2 according to a third embodiment of the present invention, and illustrates a power generation circuit 130-2 that can be applied to four control signals.

Referring to FIG. 5, the power generation circuit 130-2 according to the third embodiment of the present invention may include first to sixth MOS transistors M1 to M16.

In this case, the first control transistor is applied to the gate the second control signal, the first control signal is applied to the source, the second control transistor (M2) is applied to the gate the third control signal A drain of the first MOS transistor M1 is connected to a source, a fourth control signal is applied to a gate of the third MOS transistor M3, and a drain of the second MOS transistor M2 is applied to a source. The drain may be connected to the output terminal.

In addition, the fourth MOS transistor M4 has a first control signal applied to a gate, a second control signal applied to a source, and the fifth MOS transistor M5 has a third control signal applied to a gate. A drain of the fourth MOS transistor M4 is connected to a source, and a fourth control signal is applied to a gate of the sixth MOS transistor M6, and a drain of the fifth MOS transistor M5 is applied to a source. The drain may be connected to the output terminal.

In addition, the first control signal is applied to the gate and the third control signal is applied to the gate of the seventh MOS transistor M7, and the second control signal is applied to the gate of the eighth MOS transistor M8. A drain of the seventh MOS transistor M7 is connected to a source, and a fourth control signal is applied to a gate of the ninth MOS transistor M9, and a drain of the eighth MOS transistor M8 is applied to a source. The drain may be connected to the output terminal.

In addition, the first control signal is applied to the gate and the fourth control signal is applied to the source of the tenth MOS transistor M10, and the second control signal is applied to the gate of the eleventh MOS transistor M11. A drain of the tenth MOS transistor M10 is connected to a source, and a third control signal is applied to a gate of the twelfth MOS transistor M12, and a drain of the eleventh MOS transistor M11 is applied to a source. The drain may be connected to the output terminal.

In addition, the fourth MOS transistor M13 may be the fourth control signal applied to the gate, and the source may be grounded. The fourteenth MOS transistor M14 may be the third control signal applied to the gate. A source may be connected to a drain of the thirteenth MOS transistor M13. The fifteenth MOS transistor M15 may be applied with the second control signal to a gate, and the source may be connected to the fourteenth MOS transistor M14. The sixteenth MOS transistor M16 may be connected to a drain, and the first control signal is applied to a gate, a source is connected to a drain of the fifteenth MOS transistor M15, and a drain is connected to an output terminal. It may be.

In this case, although not shown, the first control signal, the second control signal, the third control signal, and the fourth control signal are respectively different in the order of the gates of the thirteenth MOS transistor M13 to the sixteenth MOS transistor M16. Can be applied one by one.

In addition, when any one of the first control signal, the second control signal, the third control signal and the fourth control signal is an ON signal, a power supply voltage may be output to the output terminal.

Also, a power supply voltage is output to the output terminal only when the first control signal, the second control signal, the third control signal and the fourth control signal are on signals, and the first control signal, the second control signal, and the first control signal are output. When the third control signal and the fourth control signal are off signals, zero voltage may be output to the output terminal.

In addition, the first MOS transistor M1 to the sixteenth MOS transistor M16 may be P-type MOS transistors.

Vc1 Vc2 Vc3 Vc4 OUT H L L L H L H L L H L L H L H L L L H H L L L L O

As illustrated in the above table, the first control signal Vc1, the second control signal Vc2, the third control signal Vc3 and the fourth control signal Vc4 may be H or L, in each case. A principle of generating a power voltage in the power generation circuit 130-2 according to the third embodiment of the present invention will be described below.

First, referring to FIG. 5, when Vc1 is H and Vc2 to Vc3 are L, the first MOS transistor M1, the second MOS transistor M2, and the third MOS transistor M3 may be turned on. H may be output to the output terminal OUT.

In addition, when Vc1 is L, Vc2 is H, Vc3 is L, and Vc4 is L, the fourth MOS transistor M4, the fifth MOS transistor M5, and the sixth MOS transistor M6 are in an on state. H may be output to the output terminal OUT.

In addition, when Vc1 is L, Vc2 is L, Vc3 is H, and Vc4 is L, the seventh MOS transistor M7, the eighth MOS transistor M8, and the ninth MOS transistor M9 are in an on state. H may be output to the output terminal OUT.

In addition, when Vc1 is L, Vc2 is L, Vc3 is L and Vc4 is H, the tenth MOS transistor M10, the eleventh MOS transistor M11 and the twelfth MOS transistor M12 are in an on state. H may be output to the output terminal OUT.

However, when Vc1, Vc2, Vc3, and Vc4 are all L, all of the first to twelfth MOS transistors M1 to M12 are turned off, and L is output to the output terminal OUT.

On the other hand, when Vc1, Vc2, Vc3, and Vc4 are L, L, L, and L, the thirteenth MOS transistor M13 to sixteenth MOS transistor M16 are turned on so that the output terminal out is grounded, and Vc1, Vc2 If any one of Vc3 and Vc4 is H, the output terminal is not grounded.

Therefore, the output terminal may output H or may be grounded to output zero voltage.

In general, a transistor may leak a small current even when turned off. Therefore, in the power generation circuit illustrated in FIG. 6, a minute current leaks to the output terminal even though all control signals are L, causing abnormal operation or unnecessary power consumption. Can be generated.

However, as illustrated in FIG. 5, when the thirteenth to sixteenth MOS transistors are provided, the power generation circuit 130 is changed when all of the control signals are changed to L when either of the control signals is H. FIG. By quickly removing the microcurrent remaining in -2) through the ground terminal, only H or 0 can be output to the output terminal.

For convenience of understanding, signals of the power generation circuit input / output terminals are illustrated in FIGS. 7 and 8. 7 is a diagram illustrating signals of the power generation circuit input and output terminal according to FIG. 6, and FIG. 8 is a diagram illustrating signals of the power generation circuit input and output terminal according to FIG. 4.

7 and 8, when Vc1, Vc2, and Vc3 are (L, L, and L), Vout is not completely 0. In the case of FIG. 8, Vc1, Vc2, and Vc3 are (L, L). , L), it can be seen that Vout is completely zero, and the power consumption can be reduced more than if the H state by the external power source.

The foregoing detailed description is illustrative of the present invention. In addition, the foregoing description merely shows and describes preferred embodiments of the present invention, and the present invention can be used in various other combinations, modifications, and environments. That is, it is possible to make changes or modifications within the scope of the concept of the invention disclosed in this specification, the disclosure and the equivalents of the disclosure and / or the scope of the art or knowledge of the present invention. The foregoing embodiments are intended to illustrate the best mode contemplated for carrying out the invention and are not intended to limit the scope of the present invention to other modes of operation known in the art for utilizing other inventions such as the present invention, Various changes are possible. Accordingly, the foregoing description of the invention is not intended to limit the invention to the precise embodiments disclosed. Also, the appended claims should be construed to include other embodiments.

100: switching circuit
110: power amplifier
120:
130: power generation circuit
140:
Vc1, Vc2, Vc3, Vc4: control signal
M1 ~ M16: Most transistors

Claims (7)

In the power generation circuit is selected from a plurality of control signals output from the chipset, each of which receives a first control signal and a second control signal, the voltage level is determined individually,
A first transistor to which the second control signal is applied to a control terminal, the first control signal is applied to one end, and the other end thereof is connected to an output terminal;
A second transistor to which the first control signal is applied to a control terminal, the second control signal is applied to one end, and the other end thereof is connected to an output terminal;
A third transistor having one of the first control signal and the second control signal applied to a control terminal, and having one end grounded; And
Another control signal, which is not applied to the control terminal of the third transistor, of the first control signal and the second control signal is applied to the control terminal, and one end thereof is connected to the other end of the third transistor, and the other end thereof is output. A fourth transistor connected to the terminal;
Containing
Power generation circuit.
The method of claim 1,
When the first control signal or the second control signal is an on signal that the power supply voltage is output to the output terminal
Power generation circuit.
The method of claim 1,
A power supply voltage is output to the output terminal only when the first control signal or the second control signal is an on signal, and zero voltage is output to the output terminal when the first control signal and the second control signal are off signals. Is output
Power generation circuit.
The method of claim 1,
The first transistor, the second transistor, the third transistor and the fourth transistor are P-type MOS transistors.
Power generation circuit.
A power generation circuit according to any one of claims 1 to 4;
A switch unit turned on / off according to at least one control signal selected from a plurality of control signals output from the chipset; And
A power amplifier receiving at least one control signal selected from a plurality of control signals output from the chipset;
Containing
Switching circuit with a power generation circuit.
The method of claim 5,
A power supply unit supplying power to the power amplifier;
Further comprising
Switching circuit with a power generation circuit.
The method of claim 5,
A power supply unit supplying power to the power amplifier;
More,
The switch unit is to receive the power generated by the power generation circuit
Switching circuit with a power generation circuit.

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