KR101376810B1 - Inverter - Google Patents

Abstract

The present invention relates to an inverter, in which a control signal including a first control signal, a second control signal, and a third control signal is applied to output an inverted signal, the first control signal is applied to a gate, The source is a grounded first MOS transistor; A second MOS transistor having a third control signal applied to the gate and a second control signal applied to the source; And a third MOS transistor to which the second control signal is applied to the gate and the third control signal is applied to the source. It may include, and the drain of the first MOS transistor, the second MOS transistor and the third MOS transistor may be connected to the output terminal.

Description

Inverter {INVERTER}

The present invention relates to an inverter, in particular to an inverter that can be applied to a switching circuit.

In general, the inverter refers to a device for converting DC power to AC power in the field of electronic and electric, but the inverter used in the field of digital signal processing refers to an electronic logic gate manufactured in the form of an integrated circuit that reverses the received signal.

Recently, in the field of electronics and electronics, the miniaturization of electronic devices and the reduction of power consumption extend the battery duration.

On the other hand, the conventional general inverter could be operated only when a separate external power source (VDD) is applied.

Therefore, it was difficult to make the inverter on-chip with various components, and there was a limit in miniaturization because a separate pin should be provided to receive external power.

In addition, in general, when external power is supplied, there is a problem that unnecessary power consumption occurs because continuous power is supplied regardless of the operation of the corresponding parts.

The present invention devised to solve the above problems, an object of the present invention is to provide an inverter that can perform the inverting operation without a separate external power source.

In addition, an object of the present invention is to provide a switching circuit provided with the inverter.

In the inverter according to an embodiment of the present invention for achieving the above object, in the inverter for receiving the control signal and output the inverted signal, the first control signal is applied to the control terminal, one end is grounded A first transistor; A second transistor to which a third control signal is applied to the control terminal and a second control signal is applied to one end; And a third transistor in which the second control signal is applied to a control terminal and the third control signal is applied to one end thereof. The other terminal of the first transistor, the second transistor, and the third transistor are connected to an output terminal. It may be.

In this case, the first control signal, the second control signal and the third control signal is a signal having an H or L value, at least one of the first control signal, the second control signal and the third control signal. The control signal may have a different value from the rest of the control signal.

In addition, the first transistor may be an N-type MOS transistor, and the second transistor and the third transistor may be a P-type MOS transistor.

In the inverter according to an embodiment of the present invention, the inverter receives the n control signals and inverts and outputs the inverting target control signal, wherein the inverting target control signal is applied to the control terminal and one end is grounded. 1 transistor; And a plurality of second transistors in which two first control signals selected in two are applied to the control terminal in consideration of the order of the remaining control signals except for the inverting target control signal, and a second control signal is applied to one end thereof. The other ends of the first transistor and the second transistor may be connected to the output terminal.

In this case, the second transistor is provided with (n-1)! / (N-3)! (! Is factorial), and the n control signals are signals having an H or L value. At least one control signal of the control signals may have a different value from the other control signals.

The first transistor may be an N-type MOS transistor, and the second transistor may be a P-type MOS transistor.

In the inverter according to an embodiment of the present invention, the inverter receives the n control signals and inverts and outputs the inverting target control signal, wherein the inverting target control signal is applied to the control terminal and one end is grounded. 1 transistor; And a plurality of second transistors in which the first control signals selected by two are applied to the control terminal in consideration of the order among the remaining control signals except for the inverting target control signal, and the second control signal is applied to one end thereof. And an n inverting unit having different ends of the first transistor and the second transistor connected to an output terminal, and outputting n inverted signals by inverting each of the n control signals.

Since the inverter of the present invention configured as described above can perform an inverting operation without receiving a separate power source, it can contribute to miniaturization of various electronic devices to which the inverter is applied, and can also reduce power consumption of the electronic device. Provide a useful effect.

In addition, the antenna circuit including the inverter of the present invention can also be miniaturized than before, and the power consumption can also be reduced, so that the battery duration can be extended when applied to the equipment powered by the battery.

1 is a block diagram schematically illustrating a switching circuit according to an embodiment of the present invention.
2 is a diagram illustrating the configuration and signal transmission characteristics of the buffer unit.
3 is a diagram illustrating the configuration and signal transmission characteristics of the inverter unit.
4 is a diagram illustrating a switch unit according to an embodiment of the present invention.
Fig. 5 is a modification of Fig.
6 (a) is a circuit diagram showing the configuration of an inverter according to an embodiment of the present invention.
6 (b) is a circuit diagram showing the configuration of an inverter according to an embodiment of the present invention.
6 (c) is a circuit diagram showing the configuration of an inverter according to an embodiment of the present invention.
7 is a view showing a signal of the inverter input and output terminal according to Figure 6 (a).
8 is a view showing the configuration of an inverter according to an embodiment of the present invention.

The advantages and features of the present invention and the techniques for achieving them will be apparent from the following detailed description taken in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The present embodiments are provided so that the disclosure of the present invention is not only limited thereto, but also may enable others skilled in the art to fully understand the scope of the invention. Like reference numerals refer to like elements throughout the specification.

The terms used herein are intended to illustrate the embodiments and are not intended to limit the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is to be understood that the terms 'comprise', and / or 'comprising' as used herein may be used to refer to the presence or absence of one or more other components, steps, operations, and / Or additions.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 is a block diagram schematically illustrating a switching circuit according to an embodiment of the present invention.

Referring to FIG. 1, the switching circuit 100 according to the present invention may include a driver 110 and a switch 120.

In this case, the driving unit 110 may include a power generator, a buffer unit 112 and an inverter unit 113.

The controller generates a control signal and may be implemented in various chipsets.

The power generation circuit 111 may perform a function of generating a power voltage VDD to be supplied to the buffer unit 112 by receiving a control signal generated from a control unit that may be implemented by various chipsets.

In addition, the inverter unit 113 may perform an inverting operation only by inputting a control signal without a separate external power source.

Accordingly, the buffer unit 112 and the inverter unit 113 may be driven by receiving power provided from the power generation circuit 111 without a separate external power source, thereby reducing the size of the entire switching circuit 100. It can be.

Meanwhile, the switch unit 120 may include a plurality of input / output terminals, an antenna, and a switch, and may perform an operation of connecting or disconnecting a specific input / output terminal and an antenna.

2 is a diagram illustrating the configuration and signal transmission characteristics of the buffer unit 112, and FIG. 3 is a diagram illustrating the configuration and signal transmission characteristics of the inverter unit 113.

As illustrated in FIGS. 2 and 3, the buffer unit 112 outputs the same control signal as the input control signal, and the inverter unit 113 inverts the input control signal to output the inverted control signal. .

In this case, since the power generation circuit 111 is connected to the buffer unit 112 to supply power, the buffer unit 112 and the inverter can be driven without a separate external power source.

4 is a diagram illustrating a configuration of the switch unit 120 according to an embodiment of the present invention.

Referring to FIG. 4, the switch unit 120 may include a plurality of input / output terminals, antennas, and switches. In this case, the switch may include a first switch and a second switch.

The first switch is provided between each input and output terminal and the antenna to perform an on / off operation to connect or cut off a specific input and output terminal and the antenna, the second switch is provided between each input and output terminal and the ground terminal on / off By performing the operation, the input / output terminal and the ground terminal can be connected or disconnected.

In this case, in FIG. 4, the first series switch 121 and the second series switch 122 may correspond to the first switch, and the first shunt switch 123 and the second shunt switch 124 may correspond to the first switch. It can correspond to two switches.

In this case, the control signal Vca1 output from the buffer unit 112 is applied to the first series switch 121, and the control signal Vca2 is applied to the second series switch 122 to turn on / off the corresponding switch. have.

In addition, the control signal Vca1 'output from the inverter unit 113 is applied to the first shunt switch 123, and the control signal Vca2' is applied to the second shunt switch 124 to turn on / off the switch. You can.

The same control signal may be applied to the buffer unit 112 and the inverter unit 113, and the inverter unit 113 may invert and output the input control signal.

Therefore, the signals Vca1 and Vca2 output from the buffer unit 112 and the signals Vca1 'and Vca2' output from the inverter unit 113 may have a complementary relationship. That is, when Vca1 is an H signal, Vca1 'may be a L signal.

Accordingly, the first series switch 121 and the first shunt switch 123 may be complementarily turned on and off, and the second series switch 122 and the second shunt switch 124 may be complementarily turned on. Can be on / off.

FIG. 5 is a diagram illustrating a modification of FIG. 4 and illustrates the switch unit 120 in the case of three input / output terminals.

In this case, although the input and output terminals are illustrated as Tx, Rx, and BT in FIG. 5, the present invention is not limited thereto. Referring to FIG. 5, the control signals Vca1, Vca2, and Vca3 passing through the buffer unit 112 are first series switches 121 ′ provided between the Tx, Rx, BT terminals, which are input / output terminals, and the antenna RFC. The on / off of each of the second series switch 122 'and the third series switch 125' may be controlled to connect or disconnect an input / output terminal and an antenna.

In this case, the signals output from the inverter, Vca1 ', Vca2', Vca3 'are the first shunt switch 123', the second shunt switch 124 ', and the third shunt switch 126' provided between the input and output terminals and the ground. ) You can connect or disconnect between each input and output terminal and ground.

In addition, Vc1, Vc2, and Vc3 may not have two or more signals at the same time as illustrated in FIG. 8. Therefore, the input / output terminals Tx, Rx and BT are not simultaneously connected to the antenna.

In addition, since Vca1 'is a signal inverted by Vc1, the first, second and third series switches and the first, second and third shunt switches may be complementarily turned on / off.

In general, the switches can pass a fine signal even in the off state.

However, as described above, when one input / output terminal and an antenna are connected by the complementary operation of the first, second, and third series switches and the first, second, and third shunt switches, the other input / output terminal and the antenna may be more completely blocked. Therefore, the noise of the signal transmitted between the input and output terminal and the antenna is reduced and the accuracy can be improved.

6 (a) is a circuit diagram showing the configuration of an inverter according to an embodiment of the present invention.

Referring to FIG. 6 (a), the inverter according to an embodiment of the present invention outputs an inverted signal by receiving a control signal including a first control signal, a second control signal, and a third control signal. In addition, the first and second MOS transistors M1, M2, and M3 may be configured to include a third transistor.

The first MOS transistor M1 may be applied with a first control signal to a gate, a source may be grounded, and a drain may be connected to an output terminal.

The second MOS transistor M2 may have a third control signal applied to a gate, a second control signal applied to a source, and a drain thereof connected to an output terminal.

The third MOS transistor M3 may have a second control signal applied to a gate, a third control signal applied to a source, and a drain thereof connected to an output terminal.

In this case, the first MOS transistor M1 may be an N-type MOS transistor.

In addition, the second MOS transistor M2 and the third MOS transistor M3 may be P-type MOS transistors.

In the drawing, the first control signal is denoted by Vc1, the second control signal is denoted by Vc2, and the third control signal is denoted by Vc2.

Referring to FIG. 6 (a), when the control signals are to be inverted and output by the Vc1 signal in a situation where the control signals are divided into three cases as shown in the following table, the gate of the first MOS transistor M1 is output. It can be set as the first control signal input to.

Vc1 [INPUT] Vc2 Vc3 Vca1 '[OUTPUT] H L L L L H L H L L H H

According to Table 1 above, when Vc1 is H, Vca1 'is L, and when Vc1 is L, Vca1' is output as H.

Specifically, when Vc1 is H, since the source and the drain of the first MOS transistor M1 are electrically connected, the output terminal is connected to the ground terminal and L is output as the output terminal.

On the other hand, when Vc1 is L, since the source and the drain of the first MOS transistor M1 are electrically cut off, the output terminal is not connected to the ground terminal.

In addition, Vc3 and Vc2 are applied to the gate and the source of the second MOS transistor M2, respectively, and Vc2 and Vc3 are applied to the gate and the source of the third MOS transistor M3. When one of Vc2 and Vc3 is H, H is output to the drain of one of the second MOS transistor M2 and the third MOS transistor M3.

Therefore, when Vc1 is L, Vca1 'becomes H.

6 (b) is a circuit diagram showing the configuration of an inverter according to an embodiment of the present invention.

Referring to FIG. 6B, unlike FIG. 6A, the first control signal is represented by Vc2, the second control signal is represented by Vc1, and the third control signal is represented by Vc3. Since it is the same as the description, the overlapping description is omitted.

Referring to FIG. 6 (b), when the control signals are to be inverted and output in the Vc2 signal in a situation where the control signals are divided into three cases as shown in the following table, the gate of the first MOS transistor M1 is output. It can be set as the first control signal input to.

Vc1 Vc2 [INPUT] Vc3 Vca2 '[OUTPUT] H L L H L H L L L L H H

According to Table 2 above, when Vc2 is H, Vca2 'becomes L, and when Vc2 is L, Vca2' is outputted as H.

Description of the specific principle is omitted because it is similar to the description with reference to Figure 6 (a).

6 (c) is a circuit diagram showing the configuration of an inverter according to an embodiment of the present invention.

Referring to FIG. 6C, unlike FIG. 1A, the first control signal is represented by Vc3, the second control signal is represented by Vc1, and the third control signal is represented by Vc2. Since it is the same as the description, the overlapping description is omitted.

Referring to FIG. 6 (c), when the control signals are to be inverted and output from the Vc3 signal in a situation where the control signals are divided into three cases as shown in the following table, the gate of the first MOS transistor M1 is output. It can be set as the first control signal input to.

Vc1 Vc2 Vc3 [INPUT] Vca3 '[OUTPUT] H L L H L H L H L L H L

According to Table 3 above, when Vc3 is H, Vca3 'is L, and when Vc3 is L, Vca3' is output as H.

Description of the specific principle is omitted because it is similar to the description with reference to Figure 6 (a).

FIG. 7 is a graph illustrating signals of the inverter input / output terminal according to FIG. 6 (a).

As illustrated in FIG. 7, when inverting Vc1 and outputting Vca1 ', Vca1' is output as L in a section where Vc1 is H, and Vca1 'is output as H in a section where Vc1 is L. do.

However, when Vc1, Vc2, and Vc3 are all L, Vca1 '(OUTPUT) becomes L.

Although not shown, when Vc1, Vc2 and Vc3 are all L, both Vca2 '(OUTPUT) and Vca3' (OUTPUT) are L.

When any one of the control signals inputted as described above is H, an inverter for inverting and outputting the inputted control signal without a separate external power source may be implemented.

Meanwhile, FIG. 6 illustrates the configuration of an inverter in the case of three control signals. In the case of n control signals, the first and second plurality of MOS transistors may be included.

An inverting control signal may be applied to the gate of the first MOS transistor, the source may be grounded, and the drain may be connected to the output terminal.

Two signals of the remaining control signals except for the inverting control signal may be applied to the gate and the source, respectively, and the drain may be connected to the output terminal.

A plurality of second MOS transistors may be provided.

In this case, the remaining control signals except for the inverting target control signal among the n control signals may be selected in consideration of the order in order to reflect the number of all cases.

Also, if the number of all cases is reflected, the second MOS transistor will be _(n-1) P ₂ = (n-1)! / (N-3)! (! Is factorial) according to the permutation formula. Can be.

The first MOS transistor may be an N-type MOS transistor, and the second MOS transistor may be a P-type MOS transistor.

On the other hand, Figure 8 is a view showing the configuration of an inverter according to an embodiment of the present invention, Figure 8 illustrates the case of three control signals, but is not limited thereto.

Referring to FIG. 8, inverting and outputting an inverting target control signal by receiving n control signals, n inverting units including the first and second MOS transistors are provided. An inverter that outputs n inverted signals by inverting each control signal may be configured.

The foregoing detailed description is illustrative of the present invention. It is also to be understood that the foregoing is illustrative and explanatory of preferred embodiments of the invention only, and that the invention may be used in various other combinations, modifications and environments. That is, it is possible to make changes or modifications within the scope of the concept of the invention disclosed in this specification, the disclosure and the equivalents of the disclosure and / or the scope of the art or knowledge of the present invention. The foregoing embodiments are intended to illustrate the best mode contemplated for carrying out the invention and are not intended to limit the scope of the present invention to other modes of operation known in the art for utilizing other inventions such as the present invention, Various changes are possible. Accordingly, the foregoing description of the invention is not intended to limit the invention to the precise embodiments disclosed. Also, the appended claims should be construed to include other embodiments.

100: switching circuit
110:
120:
111: power generation circuit
112: buffer unit
113: inverter unit
121: the first series switch
122: second series switch
123: first shunt switch
124: second shunt switch
125: 3rd series switch
126: third shunt switch
Vc1, Vc2, Vc3: control signal
M1, M2, M3: Most transistors

Claims (7)

In the inverter for receiving the control signal and output the inverted signal,
A first transistor having a first control signal applied to the control terminal and having one end grounded;
A second transistor to which a third control signal is applied to the control terminal and a second control signal is applied to one end; And
A third transistor to which the second control signal is applied to a control terminal and the third control signal is applied to one end;
Including;
Characterized in that the other end of the first transistor, the second transistor and the third transistor is connected to the output terminal.
inverter.
The method of claim 1,
The first control signal, the second control signal and the third control signal are signals having an H or L value, and at least one control signal among the first control signal, the second control signal, and the third control signal. Has a different value from the rest of the control signal
inverter.
The method of claim 1,
The first transistor is an N-type morph transistor,
The second transistor and the third transistor is characterized in that the P-type morph transistor
inverter.
In an inverter receiving n control signals and inverting and outputting an inverting control signal,
A first transistor to which an inverting target control signal is applied to the control terminal and one end of which is grounded; And
A plurality of second transistors having a first control signal selected two by one in consideration of the order of the remaining control signals except for the inverting target control signal, and a second control signal applied at one end;
It includes, the other end of the first transistor and the second transistor is connected to the output terminal
inverter.
5. The method of claim 4,
The second transistor includes (n-1)! / (N-3)! (! Is factorial), and the n control signals are signals having H or L values, and the n control signals At least one of the control signal is characterized in that it has a different value from the remaining control signal
inverter.
6. The method of claim 5,
The first transistor is an N-type MOS transistor, and the second transistor is a P-type MOS transistor.
inverter.
In an inverter receiving n control signals and inverting and outputting an inverting control signal,
A first transistor to which an inverting target control signal is applied to the control terminal and one end of which is grounded; And
A plurality of second transistors having a first control signal selected two by one in consideration of the order of the remaining control signals except for the inverting target control signal, and a second control signal applied at one end;
Includes, the n and the inverting unit is provided with the other end of the first transistor and the second transistor connected to the output terminal to output the n inverted signal by inverting each of the n control signals
inverter.

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