KR101330769B1 - Chalcogenide devices and materials having reduced germanium or telluruim content - Google Patents

Abstract

Chalcogenide memory devices exhibit fast operation (short set pulse times) on chalcogenide materials and extended range of reset state resistance. Electrical components comprising the present chalcogenide material allow for a quick transition from a reset state to a set state for reset and set states having a high resistance ratio. Thus, the devices provide high resistance versus improved memory state readability while maintaining fast operating speeds. The chalcogenide material includes Ge, Sb, and Te, and includes a material having a lower Ge and / or Te content than a commonly used Ge ₂ Sb ₂ Te ₅ chalcogenide composition. In one embodiment, the atomic concentration of Ge is 11% to 22%, the atomic concentration of Sb is 22% to 65%, and the atomic concentration of Te is 28% to 55%. In a preferred embodiment, the atomic concentration of Ge is 15% to 18%, the atomic concentration of Sb is 32% to 35% and the atomic concentration of Te is 48% to 51%.

Description

Chalcogenide devices and materials having reduced germanium or telluruim content}

<Information of related application>

This application is filed on August 9, 2005, and is partly filed under United States Application Serial No. 11 / 200,466, entitled "Chalcogenide Devices Incorporating Chalcogenide Materials having Reduced Germanium or Tellurium Content", the disclosure of which is incorporated herein by reference. to be.

<Technical Field>

The present invention relates to chalcogenide materials for use in electrical memories or switching devices. More specifically, the present invention provides an off-tieline having a relatively low Ge concentration and / or a relatively low Te concentration compared to the Ge ₂ Sb ₂ Te ₅ alloy widely used in the Ge-Sb-Te family. It relates to chalcogenide alloys. Most specifically, the present invention relates to an electric chalcogenide material that exhibits a high set rate from an initial state with high resistance.

Chalcogenide materials are a new family of commercial electronic materials that show switching, memory, logic, and processing capabilities. The basic principle of the chalcogenide material was S.R. It was developed by Ovshinsky, and in the last decades, many of his and other people around the world have made progress in the underlying science that governs the structure and properties of chalcogenide materials. The range is widened.

Early achievements in chalcogenide devices demonstrated the electrical switching behavior that switching from resistive to conductive states was induced when a threshold or higher voltage was applied. Although the threshold voltage is inherently a property of the device, the response of the active chalcogenide material to the voltage is a potential determinant of the magnitude of the threshold voltage. The resistance induced by voltage-conductive transformation is the basis of the Ovonic Threshold Switch (OTS) and leaves important practical characteristics of chalcogenide materials. The OTS provides high reproducible switching even at ultrafast switching speeds over 10 ¹³ cycles. The basic principles and operational features of the OTS are described, for example, in SR Ovshinsky, "Reversible Electrical Switching Phenomena in Disordered Structures", Physical Review Letters, vol. 21, p. 1450-1453 (1969); SR Ovshinsky and H. Fritzsche, "Amorphous Semiconductors for Switching, Memory, and Imaging Applications," IEEE Transactions on Electron Devices, vol. ED-20, p. United States Patent No. 3,271,591, which is incorporated by reference herein as well as in several journal articles including 91-105 (1973); No. 5,543,737; 5,694,146; 5,694,146; And 5,757,446.

Another important application of chalcogenide materials includes electrical and optical memory devices. A type of chalcogenide memory device utilizes a wide resistance range of the material as the basis of memory operation. Each resistance value corresponds to the identified structural state of the chalcogenide material and can be used to define a memory state that operates by selecting one or more of the states. The chalcogenide material may show a crystalline state or phase as well as an amorphous state or phase. The different structural states of the chalcogenide material depend on the relative proportions of the crystalline and amorphous phases in a given volume or region of the chalcogenide material. The range of resistance values is bounded by the set and reset states of the chalcogenide material. The set state is a low resistance structure state in which the electrical properties are mainly controlled by the crystalline portion of the chalcogenide material, and the reset state is a high resistance in which the electrical properties are mainly controlled by the amorphous portion of the chalcogenide material. It is a rescue state.

Each memory state of the chalcogenide memory material corresponds to a resistance value that is distinct from each other, and each memory resistance value represents a unique information content. In operation, the chalcogenide material can be programmed to a particular memory state by applying a current pulse having an amplitude and duration suitable for transitioning the chalcogenide material to a structural state having a desired resistance. By controlling the amount of energy applied to the chalcogenide material, it is possible to adjust the relative ratios of crystalline and amorphous regions within a given volume in the material, thereby adjusting the structural (and memory) state of the chalcogenide material. Can be controlled.

Each memory state can be programmed by providing a current pulse specific to that state, and each state can be identified or read in a non-destructive manner by measuring its resistance. Programming between different states is completely reversible and can provide robust and reliable operation because memory elements can be written and read out over a substantially infinite number of cycles. The variable resistance memory function of chalcogenide materials is currently being pioneered in OUM (Ovonic Universal (or Unified) Memory) devices that are beginning to appear on the market. The basic principle and operation of OUM type devices are described, for example, in IEEE Transactions on Electron Devices, vol. 51, p. "Low Field Amorphous State Resistance and Threshold Voltage Drift in Chalcogenide Materials", published by Pirovana et al., 714-719 (2004), and in IEEE Spectrum, vol. 167, p. United States Patent No. 6,859,390, which is incorporated herein by reference, as well as several journal articles, including Weiss's "Morphing Memory" published by 363-364 (2005); No. 6,774,387; No. 6,687,153; And 6,314,014.

The general behavior (switching, memory and accumulation) and chemical composition of chalcogenide materials can be found in the following U.S. Pat. No. 6,714,954; No. 6.087,674; 5,166,758; 5,166,758; 5,296,716; 5,296,716; 5,536,947; 5,536,947; No. 5,596,522; No. 5,825,046; 5,687,112; 5,687,112; No. 5,912,839; And 3,530,441. These documents also describe the mechanisms proposed to govern the behavior of chalcogenide materials, and from a crystalline state to an amorphous state (and through a series of partial crystallization states that underlie the operational characteristics of electrical and optical chalcogenide materials). Vice versa).

Current commercial development of such chalcogenide materials and devices is also directed to the fabrication of device arrays. Chalcogenide materials offer the prospect as dense memory, logic and neural network arrays that can operate using traditional binary data storage protocols or non-binary multilevel protocols. Chalcogenide arrays also offer the prospect of integrating memory and processing functions on a single chip.

In order to further extend the commercial prospects of chalcogenide phase change memory, it is necessary to devise additional improvements in the chemical and physical properties of the chalcogenide material, as well as the manufacturing process. The current issue in terms of the properties of chalcogenide materials is the need to improve the thermal stability of the materials. The data in the chalcogenide material is maintained as the structural state of the material, so any tendency for the structural state to transition with temperature means a potential and undesirable deletion or loss mechanism of the data. Many chalcogenide memory materials maintain their structural state for a long time at room temperature, but as the temperature increases, the structural state tends to change. In practical terms, this limits the temperature at which the chalcogenide memory device can be used as well as the temperature that can be employed in the process or manufacture. It is desirable to develop new chalcogenide compositions that have a stable structural state over ever increasing temperature ranges.

In most memory applications currently planned, the set states and reset states provide the greatest contrast in resistance, which makes it easier to distinguish between states of material during readout, so that memory states correspond to or approximate set states and reset states. The chalcogenide materials operate in binary mode. In most manufacturing processes expected for the commercial manufacture of chalcogenide memory devices, the chalcogenide material is deposited over a substrate, electrical contact layer or other layer. After deposition, the chalcogenide material is in an amorphous or other disordered state and converted to a crystalline state during subsequent processing. In finished and fully fabricated devices, it is sometimes necessary to electrically execute or “form” the chalcogenide material in order to prepare the device for consistent operation as the active material of the memory element. The annealing process includes the step of transferring the chalcogenide device in a manufactured state to an optimal state for product use. In devices employing widely used Ge ₂ Sb ₂ Te ₅ alloys, the annealing process requires several cycles of setting and resetting to achieve a set state resistance that stabilizes to a desirable and reproducible value.

In order to increase manufacturing efficiency, it is desirable to develop chalcogenide materials and device structures that can be electrically set to actual operation in minimum time. In US patent application Ser. No. 11 / 200,466 (the '466 application), the inventors of the present invention identified a series of new chalcogenide compositions that require little or no annealing. It is preferable that the said alloy contains Ge and group V elements, and the said group V element is Sb. In some embodiments, the alloy further includes Te. Compared to the widely used Ge ₂ Sb ₂ Te ₅ compositions, the alloys contain less Ge and / or Te. The alloy of the '466 application may be referred to as an "off-tieline" alloy, in which the composition of the alloy extends beyond the tieline connecting Sb ₂ Te ₃ and GeTe in the Ge-Sb-Te _ternary phase diagram. Because it is located.

It is more desirable to develop chalcogenide alloys that not only have less severe post-fabrication requirements but also exhibit rapid crystallization rates in a series of memory states that extend over a wide dynamic range of resistance.

In one embodiment, the present invention provides chalcogenide alloy compositions that exhibit desirable annealing properties with short crystallization times. In another embodiment, the present invention provides chalcogenide alloy compositions that exhibit only a slight change in crystallization time in different structural states in which the resistance extends to one or more orders of magnitude. When used in electric chalcogenide device applications, the alloys of the present invention provide desirable annealing properties of a plurality of states extending over a high set speed and / or a wide resistance range. The alloy of the present invention also provides the desired threshold voltage, reset current and reset resistance.

The alloy of the present invention generally comprises Ge, Sb, and / or Te, wherein the atomic concentration of Ge is generally in the range of 11% to 22%, and the atomic concentration of Sb is generally of 22% to 65% In the range, and the atomic concentration of Te is generally in the range of 28% to 55%. In one embodiment, the atomic concentration of Ge in the alloy of the invention is generally in the range of 13% to 20%, the atomic concentration of Sb is generally in the range of 28% to 43%, and the atomic concentration of Te is generally In the range of 43% to 55%. In another embodiment, the atomic concentration of Ge in the alloy of the invention is generally in the range of 15% to 18%, the atomic concentration of Sb is generally in the range of 32% to 35%, and the atomic concentration of Te is general In the range of 48% to 51%.

The present invention includes electrical devices comprising the chalcogenide materials of the present invention. The elements are elements comprising a layer of chalcogenide material in electrical communication with two electrical terminals or contacts. The invention further includes an array of such devices. In one embodiment, a device comprising one of the alloys of the present invention requires a set pulse time of less than 100 ns when the reset resistance is ≦ 200 kΩ. In another embodiment, a device comprising one of the alloys of the present invention requires a set pulse time of less than 40 ns when the reset resistance is ≦ 100 kΩ. In a preferred embodiment, the device comprising one of the alloys of the present invention requires a set pulse time of less than 20 ns when the reset resistance is ≤ 40 kΩ. In a preferred embodiment, a device comprising one of the alloys of the present invention requires a set pulse time of less than 30 ns when the reset resistance is ≦ 60 kΩ.

1 is a conceptual diagram showing the resistance of a chalcogenide material as a function of energy or current.

Figure 2 shows a change in the set pulse width as a function of the reset resistance of several two-terminal electronic devices comprising different chalcogenide alloys according to the present invention.

3 shows the set pulse width from a reset state with a resistance of more than 100 kΩ to a set state with a resistance of less than 5 kΩ of a two-terminal electrical element of the atomic concentrations of Ge, Sb and Te in the active chalcogenide material of the device. A graph represented by a function.

4 is a graph showing the reset current in a saturated reset state of a two-terminal electrical device as a function of the atomic concentration of Ge, Sb and Te in the active chalcogenide material of the device.

The present invention provides an electrical device comprising a chalcogenide material and the chalcogenide material of the present invention and exhibiting desirable operating characteristics for practical memory and switching applications. The devices include alloys of the present invention with a short set time from a reset state with high resistance. The devices provide memory states that span a wide range of resistances, with each memory state exhibiting a short set time. Thus, the devices allow for rapid transformation between memory states with significantly different resistances. In particular, devices comprising the chalcogenide alloy of the present invention enable a transition between a high resistance memory state and a low resistance memory state, and both the transition rate and the ratio of resistance between the two states are high. The devices of the present invention further provide the desired threshold voltage and reset current.

The devices have similar desirable annealing properties to those described in the '466 application for similar alloy compositions. In some embodiments, devices comprising the chalcogenide materials of the present invention do not require an annealing step to adjust the device for practical application after manufacture. In these embodiments, the set resistor becomes stable upon cycling between the set and reset states immediately following the deposition of the device, and the stabilized set resistance deviates only slightly from the virgin resistance of the device. As a result, the need for post-process electrical execution of the device prior to actual use is greatly reduced. Additional information regarding the annealing process can be found in the '466 application.

Since the basis underlying the improved set rate properties of the alloy of the present invention relates to the structural properties of the chalcogenide material, it is helpful to examine the basic working principle of the chalcogenide material. An important feature of chalcogenide materials during operation of chalcogenide memory devices and device arrays is the ability that phase transitions can occur between two or more structural states. (The importance of phase transitions in memory applications has led some people to call chalcogenide materials phase change materials and may be referred to here as such.) The chalcogenide materials are in a crystalline state, one or more partially-crystalline states. And structural states, including amorphous states. The crystalline state may be a monocrystalline state or a polycrystalline state. As used herein, a partially-crystalline state refers to a structural state in which a volume of chalcogenide comprises an amorphous portion and a crystalline portion. In general, in a phase change material a plurality of partially-crystalline states can be distinguished according to the relative proportions of amorphous and crystalline portions. Fractional crystallinity is one method of characterizing the structural state of chalcogenide phase-change materials. The partial crystallinity of the crystalline state is 100%, the partial crystallinity of the amorphous state is 0%, and the partial-crystalline state has a partial crystallinity that varies continuously between 0% (amorphous limit) and 100% (crystalline limit). Thus, phase change chalcogenide materials can transition between a plurality of structural states that vary over the full range between 0% and 100% partial crystallinity.

The transition between the structural states of the chalcogenide material is caused by energizing the chalcogenide material. Various forms of energy can affect the partial crystallinity of the chalcogenide material and cause structural transitions. Suitable forms of energy that cause electrical, thermal or optical effects on the chalcogenide material include electrical energy, thermal energy, optical energy or other forms of energy (eg, particle-beam energy). Combinations of different forms of energy can also cause structural transitions. The continuity and reversible variability of the partial crystallinity can be achieved by controlling the energy environment of the chalcogenide material. By appropriately adjusting the energy environment of the chalcogenide material, the crystalline state can be transitioned to a partially-crystalline or amorphous state, and the partially-crystalline state can be transitioned to not only the crystalline or amorphous state but also to other partial-crystalline state, The state can transition into a partially crystalline or crystalline state. Considerations regarding the use of thermal, electrical and optical energy to induce structural transitions are provided in the discussion that follows.

The use of thermal energy to induce structural transitions utilizes thermodynamics and kinetics associated with the transition from crystalline to amorphous or from amorphous to crystalline phase. The amorphous state is cooled, for example, at a rate sufficient to heat the chalcogenide material above its melting point and prevent the formation of the crystalline phase from any state before it (including partially-crystalline, crystalline or amorphous states). It can be formed by. The crystalline state affects nucleation and / or crystal domain growth from any state before it (including partially crystalline, crystalline or amorphous state), eg, chalcogenide material above the crystallization temperature. It can be formed by heating for a time sufficient for the cycle. The crystallization temperature is lower than the melting point and corresponds to the temperature at which crystallization occurs. The driving force for crystallization is usually thermodynamic in that the free energy in the crystalline or partially-crystalline state is lower than the free energy in the amorphous state so that the total energy of the chalcogenide material decreases as the partial crystallinity increases. Formation (nucleation and growth) of the crystalline domains in the crystalline or partially-crystalline state is made dynamically possible, so that heating below the melting point facilitates rearrangement of the atoms required to form the crystalline phase or domains. Promotes crystallization by providing energy. The degree of partial crystallinity of the partially-crystalline state can be controlled by adjusting the heating temperature or time of the previous amorphous chalcogenide material, or by adjusting the cooling temperature or rate of the previous amorphous chalcogenide material.

The use of electrical energy to cause structural transitions typically depends on the application of electrical (current or voltage) pulses to the chalcogenide material. By adjusting the magnitude and / or duration of the electrical pulses applied to the chalcogenide material, it is possible to continuously change the partial crystallinity. The effect of electrical energy on the structure of the chalcogenide material is dependent on the low field electrical resistance of the chalcogenide material depending on the amount of electrical energy provided to the chalcogenide material or the magnitude of the applied current or voltage pulse. It is described as a change of). A representative example describing the low electric field electrical resistance R of the chalcogenide material as a function of electrical energy or current pulse magnitude (energy / current) is provided in FIG. 1. 1 shows the change in low electric field electrical resistance of a chalcogenide material caused by varying magnitudes of electrical energy or current pulses and may generally be referred to as a resistance plot.

The resistance plot includes two characteristic response regions of the chalcogenide material to electrical energy. The regions are roughly separated by the vertical dashed line 10 shown in FIG. 1. The left region of the vertical dotted line 10 may be referred to as the cumulative region of the chalcogenide material. The cumulative region is distinguished by an electrical resistance that changes substantially constant or gradually with increasing electrical energy and terminates with a sharp decrease in resistance at threshold energy and above. Thus, the cumulative region is flat (generally denoted by 30) from the leftmost point 20 of the resistance plot relative to the direction in which the energy increases, corresponding to a range of points where the resulting change in resistance is small or progressive. Past the zone it extends to a set point or state 40 followed by a sharp decrease in electrical resistance. The flat zone 30 may be horizontal or inclined. The left side of the resistance plot is called the cumulative region because the structural state of the chalcogenide material changes continuously with the degree of partial crystallinity of the structural state, associated with the total cumulative amount of energy applied as the energy is applied. The leftmost point 20 corresponds to the structural state with the lowest partial crystallinity in the cumulative region. This state may be completely amorphous or may contain some residual crystalline content. As energy is applied, the degree of partial crystallinity increases, and the chalcogenide material transitions along the planar zone 30 in the direction of increasing energy applied among the plurality of partially-crystalline states. The selected cumulative state (structural state in the cumulative region) is represented by a square in FIG. By accumulating the threshold amount of applied energy, the partial crystallinity of the chalcogenide material increases enough to affect the setting transition characterized by stabilization in the set state 40 and a sharp decrease in electrical resistance. . The structural transition in the cumulative region proceeds only in the direction of increasing energy applied in the flat region 30 and is unidirectional in the sense that it is reversible only by the first amorphous nitriding or resetting of the chalcogenide material. to be. The behavior shown in FIG. 1 is reproducible by applying the necessary energy or current for the setting and resetting of numerous cycles of the device comprising the chalcogenide material. Once the reset state is obtained, lower amplitude current pulses can be applied again and the cumulative response of the chalcogenide material can be repeated. Thus, it is possible to cycle between set and reset states over several cycles, which is a necessary feature for high memory cycle life.

Without wishing to be bound by theory, the inventors of the present invention have found that energizing chalcogenides in the cumulative region leads to an increase in partial crystallization through nucleation of new crystalline domains or growth of existing crystalline domains or combinations thereof. Believe that. In spite of an increase in the degree of crystallinity, the electrical resistance causes the flat region 30 to increase because the crystalline domains are formed or grown relatively apart from each other to prevent formation of adjacent crystalline networks across the chalcogenide material between the two device electrodes. It is believed to change only gradually. This form of crystallization may be referred to as sub-percolation crystallization. The setting transition coincides with the percolation threshold in which adjacent and interconnected crystalline networks are formed in the chalcogenide material between the two device electrodes. Such a network can be formed, for example, when the size of the crystalline domain is sufficiently increased to collide with neighboring domains. Since the crystalline phase of the chalcogenide material has a lower resistance than the amorphous phase, the percolation threshold corresponds to the formation of an adjacent low resistance conductive path through the chalcogenide material. As a result, the percolation threshold is manifested by a sharp decrease in the resistance of the chalcogenide material. The leftmost point of the cumulative region may be in an amorphous state or in a partially crystalline state without adjacent crystalline networks. Sub-percolation crystallization initially begins in an amorphous or partially-crystalline state and proceeds through a plurality of partially-crystalline states with increasing partial crystallinity until the percolation threshold is reached until a setting transition occurs.

The right region of the dotted line 10 in FIG. 1 may be referred to as a grayscale region or a grayscale region. The grayscale region extends from the set state 40 past a plurality of intermediate states (typically denoted by 50) to a reset point or state 60. Various points in the grayscale region may be referred to as the grayscale state of the chalcogenide material. In Figure 1, the selected grayscale states are indicated by circles. Structural transitions in the grayscale region can be caused by applying an electrical current or energy pulse to the chalcogenide material as indicated in FIG. 1. In the grayscale region, the resistance of the chalcogenide material changes with the magnitude of the applied electric pulse. The resistance of a particular state in the grayscale region is a characteristic of the structural state of the chalcogenide material, and the structural state of the chalcogenide material depends on the magnitude of the current pulse applied to the grayscale region. The partial crystallinity of the chalcogenide material decreases with increasing magnitude of the current pulse. The partial crystallinity is highest at or near the set point 40 with respect to the grayscale state and gradually decreases as the reset state 60 approaches. The chalcogenide material transitions from a structural state having an adjacent crystalline network of the set state 40 to a structural state that is amorphous or substantially amorphous or partially crystalline without an adjacent crystalline network of the reset state 60. The application of increasing magnitudes of current pulses has the effect of converting portions of the crystalline network into the amorphous phase, ultimately leading to obstructing or blocking adjacent high-conducting crystalline pathways in the chalcogenide material. As a result, the resistance of the chalcogenide material increases as the magnitude of the current pulse applied in the grayscale region increases.

In contrast to the cumulative region, structural transitions occurring in the grayscale region are reversible and bi-directional. For this reason, the grayscale region may be referred to as a direct overwrite region of the resistance plot. As pointed out above, each state in the grayscale region can be identified by its resistance and current pulse magnitude, and application of that current pulse magnitude causes a change in the degree of crystallinity that results in a particular resistance value of the state. Application of subsequent current pulses may increase or decrease the partial crystallinity as compared to the partial crystallinity of the initial state of the chalcogenide material. If a subsequent current pulse is larger than the pulse used to create the initial state, the partial crystallinity of the chalcogenide material is reduced and the structural state is directed from the initial state toward the higher resistance reset state along the grayscale resistance curve. Is transferred. Similarly, if the subsequent current pulse is smaller than the pulse used to create the initial state, the partial crystallinity of the chalcogenide material is increased and the structural state is lower in resistance set along the grayscale resistance curve from the initial state. Transition in the direction of the state.

In an OUM (Ovonic Unified (or Universal) Memory) application, the gray scale states of the chalcogenide material are used to define memory states of the memory device. Most commonly, the memory elements are binary memory elements that use two of the grayscale states as memory states and associate distinct information values (eg, "0" or "1") with each state. Thus, each memory state corresponds to a distinct structural state of the chalcogenide material, and each structural state may be characterized by a distinctive resistance value, for example as illustrated by the grayscale state in FIG. 1. As such, reading or identifying the state can be accomplished by measuring the resistance of the material (or device). The act of transitioning a chalcogenide material to a structural state associated with a particular memory state may be referred to as programming the chalcogenide material, writing to the chalcogenide material, or storing information in the chalcogenide material.

In order to facilitate reading and minimize read errors, the memory states of the binary memory device are preferably selected so that the resistance of the two states is large. Typically, the set state (or state close to the set state) and the reset state (or state close to the reset state) are selected as memory states in a binary memory application. The contrast of the resistance depends on such details as the chemical composition of the chalcogenide, the thickness of the chalcogenide material in the device and the geometry of the device. In a phase-change material layer having a composition of Ge ₂₂ Sb ₂₂ Te _{56 in} a conventional two-terminal device structure, a thickness of ˜600 μs, and a pore diameter of less than ˜0.1 μm, for example, The resistance is -100-1000 kΩ and the set state resistance is less than -10 kΩ. Typical phase change materials exhibit resistances ranging from -100 to 1000 kΩ in the reset state and resistances from 0.5 kΩ to 50 kΩ in the set state. In a preferred phase-change material, the resistance of the reset state is at least two greater than the resistance of the three states, more generally by an order of magnitude or more. In addition to binary (single bit per device) memory applications, chalcogenide materials select three or more states from grayscale states and associate each state with information values to allow for non-binary or multiple bit per device elements. It may also be used as. Here, each memory state corresponds to a distinct structural state of the chalcogenide and is characterized by a distinct resistance value.

One embodiment of the present invention provides chalcogenide materials that allow devices to have improved operating speed. Device speed here refers to the time required to induce a transition between structural states. As described above, the storage of information in the chalcogenide material involves the process of energizing the chalcogenide material to cause a structural transition of the memory state that represents an item of information that the user wishes to store. . The speed of the device is governed by the rate at which structural transitions occur, which ultimately depends on the kinetics of the transition between the crystalline and amorphous (or vice versa) states of the chalcogenide material. From a phenomenological point of view, structural transitions that lead to an increase in partial crystallinity are expected to be slower than structural transitions that cause a decrease in partial crystallinity. Formation of a crystalline phase from an amorphous phase requires the creation of an ordered phase from an disordered phase, and achieving an ordered phase necessarily necessitates an atomic rearrangement requiring significant repositioning of atoms over one or more atomic distances. This entails this expectation. In periodic and ordered arrays, the required time scale for the required atomic motion and reorientation of atomic bonds is required, and the crystallization process is necessarily an equilibrium process.

Structural transitions that reduce partial crystallinity, in contrast, are inherently non-equilibrium processes that readily occur on a shorter time scale than the equilibrium time scale associated with crystallization of the same material. Reduction in partial crystallinity involves the transition of ordered crystalline regions into disordered amorphous regions. The crystalline region is first melted and then cooled to form an amorphous phase. The melting process is not limited by the time scale associated with the atomic motion of the material, and the cooling process generally takes place on a shorter time scale than the crystallization process. The rate of addition of energy to cause melting and the rate of removal of energy to cool the molten state determine the time scale of the transition. Both speeds can be controlled by external experimental conditions and can occur on an extremely short time scale. In conventional chalcogenide materials, the equilibrium time scale associated with the crystallization process is typically in the range of 10 to 1000 nanoseconds, whereas the amorphous (melt-cooling) process occurs on a time scale of less than 10 seconds to 10 nanoseconds, controlling the experimental conditions. This allows picoseconds and even femtoseconds to occur on time scales.

From the discussion above, it has been found that the operating speed of the chalcogenide memory device is determined, in part, by the rate of transition from a state with low partial crystallinity to a state with high partial crystallinity. In a typical binary device, the two memory states are the reset state (the state with the low partial crystallinity) and the set state (the state with the high partial crystallinity), and the operation speed is largely determined by the time scale of the transition from the reset state to the set state. It is expected to be affected.

In addition to the rate of transition from the amorphous phase to the crystalline phase, the time required to set up the chalcogenide device depends on the volume fraction of crystalline in the initial state of the device. As described above with respect to FIG. 1, the memory states of the chalcogenide device may be selected from grayscale states 50 extending from the set state 40 to the reset state 60. The set state 40 may be formed from the reset state 60 or any grayscale state 50 by applying and accumulating an increment of energy as described above to achieve the percolation condition. The magnitude of the energy increment required to achieve the percolation required to set one of the grayscale states is less than the energy required to cause a transition from the reset state of region 60 in FIG.

Grayscale states close to the set state have resistance and partial crystallinity similar to those of the set state. These states have a relatively low resistance and require a relatively low net accumulation energy to make the setting transition. The similarity in partial crystallinity of the low resistance grayscale state to the set state implies a structural configuration or condition for the low resistance grayscale states that do not deviate much from the percolated configuration of the set state. Because only small transitions are required in the structural configuration to achieve the set state, the time required to induce the setting transition is shorter and a faster transition between the low resistance grayscale states and the set state is possible.

However, as the resistance of the grayscale state increases, the structural composition deviates from the crystalline and more significantly from the percolated composition of the set state. More energy is accumulated and an increase in the actual transition of the structural composition is necessary to achieve the three states. Thus, the time scale of the setting transition increases. This leads to a slower operating speed for memory devices that use high resistance grayscale states as the memory state.

The above discussion shows that the intrinsic rate of crystallization of the working chalcogenide material from an amorphous or low partial crystallinity state and the initial state of crystallinity of the chalcogenide material are the rate of transition between the memory states, and thus, the operating rate of the memory device. It indicates two important factors that govern. While it is true that fast operating speeds can be achieved by selecting memory states having a structural configuration that does not deviate much from the percolated configuration of the set state, this approach is inadequate in many cases. The main drawback in this approach is that the readout between the different memory states is more difficult to read because the resistances between the different memory states are low and the resistances of the different states are similar.

In the present invention, a more effective approach to achieving faster operating speeds is realized through chalcogenide compositions showing an improved intrinsic rate of crystallization. The chalcogenide alloy of the present invention enables chalcogenide memory devices that exhibit a rapid transition from grayscale states to three states that extend over a wider range of resistance than was possible with conventional alloys. Fast intrinsic crystallization rates are fast in the transition from high-resistance grayscale states to set states, since it is less important for creating a transition rate that the structural deviation of the grayscale state initially out of the percolated configuration of the set state is faster. Enable the transition. The high crystallization rate can compensate for the increased structural differences between the high resistance memory state and the set state. The chalcogenide alloy of the present invention thus enables memory devices that simultaneously provide high operating speeds and high resistance contrast between memory states.

Without wishing to be bound by theory, the inventors of the present invention have found that the process of crystallization in chalcogenide materials can occur through one or more of the following mechanisms: nucleation of crystalline domains from amorphous domains Growth of the nucleated phases, and growth of existing crystalline regions. Improvements in the rate of one or more of these mechanisms are expected to increase the rate of crystallization. Improving the rate of nucleation will provide an increase in the concentration of crystalline nuclei, which will result in faster crystallization rates as they act as seeds of the crystallization process. Growth is a process in which the size of an existing crystalline region is increased by interfacing an amorphous material to a crystalline material at the boundary of the crystalline domain. Improved growth rates will promote expansion of the crystalline domains and will promote transition to percolated structural configurations.

Formation of the crystalline phase from the amorphous phase is generally preferred thermodynamically but inhibited kinetically. At temperatures below the melting point, the free energy of the crystalline phase is lower than the free energy of the amorphous phase, with the result that there is a thermodynamic driving force for crystallization. However, as mentioned above, to crystallize, it is necessary for a material to undergo atomic rearrangements necessary to realize an ordered crystalline state. Energy barriers must be overcome to cause the necessary rearrangements, which act to inhibit crystallization. Both nucleation and growth processes involve energy barriers. As the size of the energy barrier increases, the dynamic probability of the crystallization process decreases. A possible explanation of the improved crystallization rate observed in the alloy of the present invention is the reduction of the energy barrier associated with either or both nucleation and growth processes. Reduced energy barriers will occur in chalcogenide compositions that show easy atomic rearrangement at temperatures between crystallization and melting temperatures. Easy rearrangement will be expected in compositions with reduced structural stiffness, especially in the amorphous phase.

Possible explanations for improved crystallization rates can be found in the relative atomic concentrations between the different elements of the compositions of the present invention. Materials of the invention generally include Ge, Sb, and Te. These elements are tetravalent, trivalent and divalent, respectively. On many amorphous chalcogenides, Te serves as a modifying element, which promotes the formation of extended chain structures and Ge and Sb serve to promote crosslinks between the chains. Sb is only a medium crosslinking element, while Ge is a highly crosslinkable element. Crosslinking acts to increase the rigidity of the amorphous phase structure, and therefore, a decrease in Ge and / or Sb concentration may tend to make the amorphous phase less rigid. However, as the concentration of Ge and / or Sb decreases, the concentration of Te increases, which has the effect of increasing the chain length. Long chain lengths are disadvantageous in terms of crystallization because long chains are difficult to rearrange and make them orderly, which helps crystallization.

The chalcogenide material of the present invention generally has a lower atomic concentration of Ge and Te and a higher atomic concentration of Sb than conventional materials. Reduction of Ge implies a reduction in the tendency to form crosslinks in the amorphous phase and may serve to promote crystallization through a reduction in structural rigidity. Reduction of Te may serve to reduce the number and / or length of similar structures in the chain in the amorphous phase, which may promote crystallization by facilitating atomic rearrangement. Although Sb is a crosslinkable element, it is less effective than Ge in forming crosslinks. Given the reduced Te concentration, the effect of increased Sb concentration on structural stiffness may not be significant. Accordingly, the chalcogenide compositions of the present invention may exhibit an optimal match of the factors underlying the crystallization tendency of the chalcogenide material.

In one embodiment, the alloy is a material having a Ge concentration in the range of 11%-22%, an Sb concentration in the range of 22%-65%, and a Te concentration in the range of 28%-55%. In another embodiment, the alloy is a material having a Ge concentration in the range of 13% -20%, an Sb concentration in the range 28% -43%, and a Te concentration in the range 43% -55%. In one embodiment, the alloy is a material having a Ge concentration in the range of 15%-18%, an Sb concentration in the range of 32%-35%, and a Te concentration in the range of 48%-51%.

Illustrative illustrations of chalcogenide compositions within the scope of the present invention and the properties of devices comprising the chalcogenide compositions of the present invention are described in the following examples.

&Lt; Example 1 >

In this embodiment, the manufacture of a memory device having an active chalcogenide layer according to the present invention is described. The structure of the device is a commonly used two-terminal device design having an active chalcogenide layer as electrical contact in the pores, along with the top and bottom electrodes. Two different device configurations were used and similar results were obtained for each. Both designs were deposited on a Si wafer with a thick SiO ₂ surface oxide layer.

In one design, a chalcogenide layer having a thickness of 500 mm ₃ was deposited over a circular bottom electrode surrounded by a SiO ₂ layer and having dimensions of <1000 mm 3. Next, the top electrode was deposited in situ, and the top electrode included a 400 Å carbon layer deposited on top of the chalcogenide layer and one or more conductive layers deposited on the carbon layer. The conductive layers typically included a 300 kPa TiN layer and a 500 kPa Ti layer.

In a second design, a 350 kV bottom electrode layer (eg titanium aluminum nitride) was deposited over the surface oxide layer and an insulating layer (eg SiO ₂ ) was deposited over the bottom electrode. Pores having a diameter of about 800 mm 3 were formed in the insulating layer. Then, a chalcogenide layer having a thickness of 500 kPa was deposited. The chalcogenide layer extended laterally over the surrounding insulating layer, covering the pores. Next, an upper electrode was deposited in situ, and the upper electrode included a 400 kPa carbon layer deposited on top of the chalcogenide layer and one or more conductive layers deposited on top of the carbon layer. The conductive layers typically included a 300 kPa TiN layer and a 500 kPa Ti layer.

Appropriate lithography and patterning were performed for each device design to process the devices and the devices were annealed at 300 ° C. for 30 minutes. Both device designs are well known in the art, and additional information regarding chalcogenide phase change memory cells is described, for example, in US Pat. No. 5,166,758, the disclosure of which is incorporated herein by reference; 5,296,716; 5,296,716; 5,414,271; 5,414,271; 5,359,205; 5,359,205; And 5,534,712.

The chalcogenide layer of each memory element of this embodiment was deposited using an RF co-sputtering process at 200 ° C. Ge ₂ Sb ₂ Te ₅ , Ge and Sb targets were used for deposition. Chalcogenide films of different compositions were produced by the use of different targets in the control of power, ion energetics, exposure time and sputtering process. Memory devices with chalcogenide layers having the following compositions were fabricated:

designation Chalcogenide material Ge (at.%) Sb (at.%) Te (at.%) o5133 Ge _22.2 Sb _22.2 Te _55.6 22.2 22.2 55.6 o5134 Ge _20.0 Sb _25.5 Te _54.5 20.0 25.5 54.5 o5135 Ge _17.8 Sb _33.3 Te _48.9 17.8 33.3 48.9 o5136 Ge _15.6 Sb _41.1 Te _43.4 15.6 41.1 43.4 o5137 Ge _13.3 Sb _48.8 Te _37.8 13.3 48.8 37.8 o5138 Ge _11.1 Sb _56.6 Te _32.3 11.1 56.6 32.3 o5142 Ge _25.0 Sb _45.5 Te _29.5 25.0 45.5 29.5 o5143 Ge _25.2 Sb _40.7 Te _35.1 25.2 40.7 35.1 o5139 Ge _8.9 Sb _64.4 Te _26.7 8.9 64.4 26.7 o5140 Ge _6.7 Sb _72.2 Te _21.2 6.7 72.2 21.2 o5144 Ge _25.0 Sb _35.5 Te _39.5 25.0 35.5 39.5 o5145 Ge _20.0 Sb _60.5 Te _19.5 20.0 60.5 19.5 o5146 Ge _31.0 Sb _49.5 Te _19.5 31.0 49.5 19.5 o5147 Ge _42.0 Sb _38.5 Te _19.5 42.0 38.5 19.5

The composition is listed as the atomic percentage of elements contained in the chalcogenide material. The atomic percentage may be referred to herein as atomic concentration. Many devices were fabricated in this example using each of the chalcogenide compositions. The chalcogenide materials and devices comprising them may be called by the compositions listed above or by the name shown in the left column.

The devices of this embodiment are chalcogenide compositions indicated above as electrical elements comprising a chalcogenide material, a first terminal in electrical communication with the chalcogenide material, and a second terminal in electrical communication with the chalcogenide material. One or more devices using each of have been fabricated. The operating characteristics of the devices are qualitatively shown in FIG. 1 because each device can operate in a plurality of reset states (right states) or in a plurality of cumulative states (left states) or a combination of reset and cumulative states. Similar to behavior. Different chalcogenide compositions resulted in differences in the operating characteristics of the devices, which differences are described in Example 2 below.

<Example 2>

In this embodiment, an improved crystallization rate of a device comprising chalcogenide materials according to the invention is described. The element structures used in this embodiment correspond to those described in Example 1 of the right. Crystallization rates of the devices including the various chalcogenide composition layers listed in Example 1 were measured. During the measurement, a current pulse was applied to the device to transfer the chalcogenide to the initial state of the grayscale portion of the response curve. The resistance of the initial state was recorded. In the next step of the experiment, the time required to energize the device and set it up was recorded. The energy applied was in the form of current pulses with constant amplitude and varying width. The energy of the pulse is the resistance of the device vs. The device was to operate in the cumulative response region of the current plot (see FIG. 1). The resistance of the device was monitored as a function of the time that pulses were applied to the device at various pulse widths from 20 ns to 5 μs. The setting transition was indicated by the decrease in resistance described in connection with FIG. 1 above. The pulse time required to achieve the set state was recorded. For each device, the experiment was repeated by identifying several different initial states in the grayscale region over a wide range of resistors, and the relationship between the resistance of the initial state and the pulse time required to set the device was determined.

2 shows the dependence of the pulse time required to set the device on the resistance of the initial state used in the experiment. The pulse time required to set the device may be referred to as set pulse width, which is denoted Wset in FIG. The set pulse time is reported in units of seconds. The resistance of the initial state used in the experiment may be referred to as the reset resistance of the device because it represents the resistance of the grayscale state in which the device was reset prior to commencement of the experiment. (Within this terminology, the reset state with the maximum resistance may be referred to as a saturation reset state). The resistance of the initial state is denoted by Rrs in FIG. 2 and is reported in units of Ohms. 2 shows several data curves. Each data curve corresponds to a device that contains a different chalcogenide composition, and the points on each curve correspond to different reset states for the device. The legend of FIG. 2 identifies chalcogenide compositions associated with each data curve by their name in the table of compositions provided above. The data curve labeled “Control” refers to the device comprising the Ge ₂ Sb ₂ Te ₅ composition of the prior art.

The data curves for the control device are typical responses of chalcogenide materials of the prior art. When the resistance of the reset state of the control element is less than about 4.5 kΩ, the set pulse time is about 20 ns. However, if it exceeds about 4.5 kΩ, the set pulse time increases significantly and has a value of about 400 ns at a resistance of about 11.9 kΩ. The results show that the set pulse time is about twenty-fold different for memory states that differ by a factor slightly greater than two in resistance. In practical memory applications, the resistance ratio between memory states is desired to be able to reliably distinguish different states while reading at least a factor of two. In the case of the control element, the data show that a doubling increase in resistance involves a significant increase in set pulse time. In terms of operating speed, the longer set pulse time of the higher resistance state is a controlling factor.

Consideration of the data curves for a device comprising alloys according to the invention shows a much more desirable relationship between set pulse time and reset resistance. The data curves of the devices comprising the alloys of the invention generally fall significantly below the data curve of the control device. Devices comprising the alloy of the present invention provide an advantageous property of providing a short set pulse time for a state with a higher reset resistance. Representative data points in the selected data curve of FIG. 2 are summarized in the following table.

Data curve Furtherance Rrs (Ω) Wset (ns) o5134 Ge _20.0 Sb _25.5 Te _54.5 6.3 24 o5134 Ge _20.0 Sb _25.5 Te _54.5 8.3 60 o5134 Ge _20.0 Sb _25.5 Te _54.5 245 149 o5135 Ge _17.8 Sb _33.3 Te _48.9 11 20 o5135 Ge _17.8 Sb _33.3 Te _48.9 103 24 o5135 Ge _17.8 Sb _33.3 Te _48.9 252 86 o5136 Ge _15.6 Sb _41.1 Te _43.4 9.7 29 o5136 Ge _15.6 Sb _41.1 Te _43.4 37 33 o5136 Ge _15.6 Sb _41.1 Te _43.4 175 60 o5136 Ge _15.6 Sb _41.1 Te _43.4 296 124 o5137 Ge _13.3 Sb _48.8 Te _37.8 21 20 o5137 Ge _13.3 Sb _48.8 Te _37.8 94 50 o5138 Ge _11.1 Sb _56.6 Te _32.3 6.6 20 o5138 Ge _11.1 Sb _56.6 Te _32.3 34 20 o5138 Ge _11.1 Sb _56.6 Te _32.3 48 60

The data points show that the alloy of the present invention has certain advantages over the control alloy of the prior art. Short set pulse times have been observed for much higher reset resistors (over a much wider range or reset resistor) for devices comprising the inventive alloys. In devices comprising a Ge _17.8 Sb _33.3 Te _48.9 alloy, for example, the increase in set pulse time accompanying a rise in resistance of more than twenty times was only a factor of 4.3. Equally desirable results have been observed for other alloys disclosed herein, including those listed in the table above.

Thus, devices operating with the alloy of the present invention exhibit faster set transitions over a wider range of reset resistors than equivalent devices operating with prior art alloys. From an application point of view, the extended resistance range in which fast set transitions are observed is advantageous because it allows the operation of binary devices that use memory states with widely dropped resistances without sacrificing operating speed. For example, in the case of the control element, a set pulse time of 400 ns allows operation between memory states where the resistance has fallen by a factor slightly larger than two. In the case of devices comprising Ge _17.8 Sb _33.3 Te _48.9 , in contrast, a set pulse time of only 86 ns enables operation between memory states with a resistance greater than 20. Operation between widely separated memory states in a resistor is desirable because it is easier to distinguish when reading the states and is more tolerant of cell-to-cell programming variations. Greater resistance contrast reduces read errors.

Devices comprising the alloys of the present invention are also advantageous for multi-state memory applications. The extended range of resistive states in which fast set transitions occur for the alloys of the present invention means that more memory states can be operated at the expense of device speed. For example, if a minimum resistance contrast of about 2 factors is desired to ensure sufficiently accurate readability of the memory states, the control element only needs two if it wishes to operate at a speed limited to a set pulse time of 400 ns. Only memory states are possible. On the other hand, for devices containing Ge _17.8 Sb _33.3 Te _48.9 alloy, there are five consecutive memory states with a factor of 2 resistance versus faster operation speed defined by a set pulse time of 86 ns. Can be defined.

The present invention provides an electrical device comprising a chalcogenide material in electrical communication with at least two terminals. The device can operate between a plurality of states determined by the structural characteristics of the chalcogenide material. In one implementation, the operating states of the device include two or more reset states, wherein the resistance of one of the reset states is at least three greater than the resistance of the other of the reset states and at a higher resistance state. The set pulse time required is at least 20 less than the set pulse time required for the lower resistance reset state. In another embodiment, the operating states of the device include two or more reset states, wherein the resistance of one of the reset states is at least three greater than the resistance of the other of the reset states and at a higher resistance state. The set pulse time required is greater than at least 10 factors greater than the set pulse time required for the lower resistance reset state. In another embodiment, the operating states of the device include two or more reset states, wherein the resistance of one of the reset states is at least three greater than the resistance of the other of the reset states and at a higher resistance state. The set pulse time required is greater than the set pulse time required by the lower resistance reset state by a factor of at least 5 less. In another embodiment, the operating states of the device include two or more reset states, wherein the resistance of one of the reset states is at least three greater than the resistance of the other of the reset states and at a higher resistance state. The set pulse time required is at least a factor less than 2 greater than the set pulse time required for the lower resistance reset state.

In one implementation, the operating states of the device include two or more reset states, wherein the resistance of one of the reset states is at least 10 greater than the resistance of the other of the reset states and at a higher resistance state. The set pulse time required is at least 20 less than the set pulse time required for the lower resistance reset state. In another embodiment, the operating states of the device include two or more reset states, wherein the resistance of one of the reset states is at least 10 greater than the resistance of the other of the reset states and at a higher resistance state. The set pulse time required is greater than at least 10 factors greater than the set pulse time required for the lower resistance reset state. In another embodiment, the operating states of the device include two or more reset states, wherein the resistance of one of the reset states is at least 10 greater than the resistance of the other of the reset states and at a higher resistance state. The set pulse time required is greater than the set pulse time required by the lower resistance reset state by a factor of at least 5 less.

In one implementation, the operating states of the device include two or more reset states, wherein the resistance of one of the reset states is at least 20 greater than the resistance of the other of the reset states and at a higher resistance state. The set pulse time required is at least 20 less than the set pulse time required for the lower resistance reset state. In another embodiment, the operating states of the device include two or more reset states, wherein the resistance of one of the reset states is at least 20 greater than the resistance of the other of the reset states and at a higher resistance state. The set pulse time required is greater than at least 10 factors greater than the set pulse time required for the lower resistance reset state. In another embodiment, the operating states of the device include two or more reset states, wherein the resistance of one of the reset states is at least 20 greater than the resistance of the other of the reset states and at a higher resistance state. The set pulse time required is at least 5 less than the set pulse time required for the lower resistance reset state.

FIG. 3, derived from FIG. 2, summarizes the set pulse width data borrowed for the control device and devices including the alloys of the present invention. Figure 3 specifically illustrates the set pulse time from a reset state with a resistance in excess of 100 kΩ for the control alloy and the devices comprising the various alloys of the present invention. At the transition of each device, the set state had a resistance of less than 5 kΩ. In Figure 3, the set pulse width is shown as a function of the atomic percentage of Ge, Sb and Te in the active chalcogenide layer of the device. The atomic percentages of Ge, Sb and Te are represented by diamond symbols, triangle symbols and square symbols, respectively. The atomic percentage of each element is shown for each of the various compositions such that each composition is represented by the three symbols of FIG. 3. Since one set pulse width was reported for each composition in FIG. 3, the three symbols representing each composition are aligned horizontally. The set of three uppermost symbols corresponds to the set pulse width of the reference device using Ge ₂₂ Sb ₂₂ Te ₅₅ as the active chalcogenide material. The composition shows the longest set pulse width shown in FIG. 3.

In addition, three ellipses representing the preferred atomic percentages of each element of the chalcogenide material are included in FIG. 3. The approximate ranges associated with the ellipses are based on the desirability of short set pulse widths and fast operation of the device. The ellipse on the left represents the preferred range of atomic percentages of Ge and extends from about 13.5% to about 18%. In this Ge composition range, the set pulse width of the device is either a device comprising Ge ₂₀ Sb ₃₀ Te ₅₀ as the active chalcogenide material or a control device (including a chalcogenide material having a Ge atomic percentage of 22%). Is much shorter than the set pulse width.

The ellipse in the middle represents the preferred range of atomic percentages of Sb, extending from about 33.0% to about 41%. In this range of Sb compositions, the set pulse width of the device is determined by a device comprising Ge _20.0 Sb _25.5 Te _54.5 as the active chalcogenide material or a control device (comprising a chalcogenide material having an Sb atomic percentage of 22%). Much shorter than the set pulse width.

The ellipses on the right represent the preferred range of atomic percentages of Te and extend from about 37% to about 48%. In this Te composition range, the set pulse width of the device is determined by the device comprising Ge _20.0 Sb _25.5 Te _54.5 as the active chalcogenide material or the control device (including the chalcogenide material having a Te atomic percentage of 55%). Much shorter than the set pulse width.

4 is derived from the results provided in FIG. 2 and provides a summary of the required reset current of the devices. The reset current is provided as a function of the atomic percentage of elements contained in the active chalcogenide charge of the devices. As in FIG. 3, atomic percentages of Ge, Sb, and Te are shown for each composition, each composition being represented by three horizontally aligned symbols. The atomic percentages of Ge, Sb, and Te are represented by diamonds, triangles and squares, respectively. The reset current is expressed in amperes (A) and corresponds to the current required to transition the device to its saturated reset state. As described above, the saturated reset state of the device is a reset state with a maximum resistance. In order to minimize the power required for the operation of the device, devices with low reset currents are preferred.

4 shows a preferred range of atomic percentages of Ge, Sb, and Te. The preferred ranges correspond to the atomic percentages of the different elements that allow for a lower reset current. The ellipse on the left represents the preferred range of atomic percentages of Ge and extends from about 14% to about 22%. In this range of Ge compositions, the reset current of the device is generally reduced compared to compositions having more or less Ge atomic percentages. The middle ellipse represents the preferred range of atomic percentages of Sb and extends from about 17% to about 33%. In this range of Sb compositions, the reset current of the device is generally reduced compared to compositions having more or less Sb atomic percentages. The ellipse on the right represents the preferred range of atomic percentages of Te and extends from about 43% to about 55%. In this range of Te composition, the reset current of the device is generally reduced compared to compositions having more or less Te atomic percentages.

In addition to the results described in Example 2 above, additional experiments were conducted using the devices and compositions described in Example 1 above. These experiments include the set pulse width needed to transition the device from a reset state with a resistance of 50 kΩ to a set state with a resistance of less than 5 kΩ; A threshold voltage in the device's saturation reset state; Holding voltage of the device; And the virgin resistance of the device was measured. The parameter sets included in these experiments and the experiments described in Example 2 above correspond to several device characteristics that are more important for practical memory applications. The results generally show small changes in the optimal range of atomic percentages of Ge, Sb, and Te for different properties. As a result, in the design of new devices, the importance of different properties is taken into account in order to achieve an optimal level of overall performance.

The present invention generally provides a chalcogenide material comprising Ge and Sb. In one embodiment, the atomic concentration of Ge is between 11% and 21%. In a preferred embodiment, the atomic concentration of Ge is between 13% and 20%. In another preferred embodiment, the atomic concentration of Ge is between 15% and 18%. In one embodiment, the atomic concentration of Sb is between 22% and 65%. In a preferred embodiment, the atomic concentration of Sb is between 28% and 43%. In another preferred embodiment, the atomic concentration of Sb is between 32% and 35%. In each of the above embodiments, the composition range indicated for each element includes the upper and lower limits of the composition.

The present invention further provides chalcogenide materials comprising Ge and Sb as well as Te in the concentration ranges described above. In one embodiment, the atomic concentration of Te is between 28% and 55%. In a preferred embodiment, the atomic concentration of Te is between 43% and 55%. In another preferred embodiment, the atomic concentration of Te is between 48% and 51%. In each of the above embodiments, the composition range indicated for each element includes the upper and lower limits of the composition.

The invention further includes embodiments having functional equivalents to the example embodiments described above. As described in various US patents incorporated herein by reference, chalcogenide materials generally include chalcogenide elements and one or more chemical or structural modification elements. The chalcogenide elements (eg, Te, Se) are selected from the group VI columns of the periodic table, and the modifying elements are the group III columns (eg Ga, Al, In) of the periodic table, and the group IV columns (eg, Si, Ge, Sn) or Group V columns (eg, P, As, Sb). The role of the modifying elements includes providing branching or crosslinking points between chains containing chalcogenide elements. Group IV column modifiers can act as coordinating modifiers comprising a coordination site in the chalcogenide chain and a coordination site allowing branching or crosslinking from the chalcogenide chain. Group III and Group V column modifiers can act as triconfiguration modifiers comprising a coordination site in the chalcogenide chain and a single coordination site to allow branching or crosslinking from the chalcogenide chain. Although the embodiments described above show features of the present invention using chalcogenide materials including Ge, Sb and / or Te, Ge may be substituted in whole or in part by other Group IV column elements (eg Si). Sb may be substituted in whole or in part with another Group V column element (eg As), and Te may be substituted in whole or in part with another Group VI column element (eg Se) Will be understood by those skilled in the art.

In addition to the individual devices, the present invention extends further to an array of devices. Chalcogenide materials and devices of the present invention are described in US Pat. No. 5,694,146, the disclosure of which is incorporated herein by reference; No. 5,912,839; And X-Y arrays, such as those described in US Pat. No. 6,141,241. Chalcogenide device arrays can be used for both memory and processing power, including logic and parallel computing.

The foregoing discussion and description are not intended to limit the practice of the invention, but rather are illustrative. It will be understood by those skilled in the art that there are numerous equivalents of the exemplary embodiments disclosed herein. The following claims, all equivalents and obvious variations thereof, combined with the above disclosure, define the scope of the invention.

Claims (17)

delete delete delete delete delete delete delete delete delete An electrical device comprising a chalcogenide material, a first terminal in electrical communication with the chalcogenide material, and a second terminal in electrical communication with the chalcogenide material, wherein the device is in a first reset state and a second Has a reset state, the resistance of the first reset state is greater by at least three factors than the resistance of the second reset state, and the set pulse time required for the first reset state is in the second reset state; An electrical element that is larger than a factor of less than 20 than the required set pulse time. 11. The electrical device of claim 10 wherein the set pulse time required for the first reset state is greater than the set pulse time required for the second reset state by a factor less than five. 11. The electrical device of claim 10 wherein the resistance of the first reset state is at least 10 greater than the resistance of the second reset state. 13. The electrical device of claim 12 wherein the set pulse time required for the first reset state is greater than the set pulse time required for the second reset state by a factor less than 10. 13. The electrical device of claim 12 wherein the set pulse time required for the first reset state is greater than a factor less than 5 than the set pulse time required for the second reset state. 11. The electrical device of claim 10 wherein the resistance of the first reset state is greater by at least 20 factors than the resistance of the second reset state. 16. The electrical device of claim 15 wherein the set pulse time required for the first reset state is greater than a factor less than 10 than the set pulse time required for the second reset state. 16. The electrical device of claim 15 wherein the set pulse time required for the first reset state is greater than a factor less than 5 greater than the set pulse time required for the second reset state.

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