KR101289631B1 - OrgAniC Light Emitting Diode DisplAy And Driving Method Thereof - Google Patents

Abstract

The present invention relates to an organic light emitting diode display and a method of driving the same which can improve display quality by minimizing the amount of change in driving current.

An organic light emitting diode display device according to the present invention includes an organic light emitting diode device intersecting data lines and gate lines and formed between a driving voltage source and a base voltage source, and connected between a first node and the base voltage source. An organic light emitting diode display device having a capacitor and a driving device for controlling a current flowing through the organic light emitting diode device according to a voltage applied to a gate through the first node, the organic light emitting diode display device comprising: a data line to which a data voltage is supplied; A first gate line supplied with a first scan pulse; A second gate line supplied with a second scan pulse subsequent to the first scan pulse; After charging the first node with a reset voltage obtained by subtracting a threshold voltage of a first switch element disposed in one pixel together with the driving element from the voltage of the first scan pulse, the data voltage is applied to the data line. Charging the second node to the data voltage by turning on a third switch element between the second node separated from the first node and the data line in response to the second scan pulse supplied to the second period. And discharging the reset voltage to a data voltage to which the threshold voltage of the second switch element is added by using a second switch element between the first node and the second node, and simultaneously discharging the reset voltage to the capacitor. After charging the data voltage to which the threshold voltage of the device is added, the switch device is turned off for a third period to drive the driving device to the voltage of the first node. A switch driving circuit for driving is provided.

Description

Organic Light Emitting Diode Display and Driving Method {OrgAniC Light Emitting Diode DisplAy And Driving Method Thereof}

1 is a diagram illustrating a light emitting principle of a conventional organic light emitting diode display.

2 is a block diagram schematically illustrating a conventional organic light emitting diode display.

3 is a circuit diagram illustrating in detail a pixel illustrated in FIG. 2;

4 is a diagram illustrating an example in which a threshold voltage of a driving TFT is increased due to a positive gAte-BiAs stress.

FIG. 5 is a diagram illustrating a current decrease of an organic light emitting diode device according to an increase in a threshold voltage of a driving TFT.

6 is a block diagram illustrating an organic light emitting diode display device according to a first embodiment of the present invention.

7 is a timing diagram of a scan pulse supplied to any one of the pixels of FIG. 6.

8 is a circuit diagram illustrating a pixel included in an organic light emitting diode display according to a first embodiment of the present invention.

FIG. 9 is an equivalent circuit diagram of a pixel for the reset period A of FIG. 7.

FIG. 10 is an equivalent circuit diagram of a pixel for the compensation period B of FIG. 7.

FIG. 11 is an equivalent circuit diagram of a pixel for the light emission period C of FIG. 7.

FIG. 12 is a diagram illustrating a simulation result showing a transient state of a voltage applied to a first node in sections A, B, and C of FIG. 7.

FIG. 13 is a diagram showing a simulation result for showing that the reduction in driving current is minimized in response to the increase in the threshold voltage of the driving TFT when the same gray scale is expressed. FIG.

14 is a block diagram illustrating an organic light emitting diode display device according to a second exemplary embodiment of the present invention.

15 is a circuit diagram illustrating a pixel included in an organic light emitting diode display according to a second exemplary embodiment of the present invention.

16 is a block diagram illustrating an organic light emitting diode display device according to a third exemplary embodiment of the present invention.

FIG. 17 is a circuit diagram illustrating a pixel included in an organic light emitting diode display according to a third exemplary embodiment of the present invention. FIG.

18A to 18C illustrate transient states of a driving current according to a voltage applied to a first node during sections A, B, and C of FIG. 7.

FIG. 19 is a view illustrating an amount of change in driving current of each of FIGS. 18A to 18C according to an increase in the threshold voltage of the driving TFT during the section A of FIG.

Description of the Related Art

116: display panel 118: gate driving circuit

120: data driving circuit 122,222,322: pixels

124: timing controller 130: organic light emitting diode element driving circuit

S [n-1]: front end scan pulse S [n]: back end scan pulse

Vd: Data Voltage DR: Driving TFT

SW1, SW2, SW3: first, second and third switch TFT

SWa: Overcurrent Suppression Switch TFT C: Capacitor

Ca: Overcurrent Suppression Capacitor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting diode display and a driving method thereof, and more particularly, to an organic light emitting diode display and a driving method thereof capable of minimizing the amount of change in driving current and improving display quality.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Such a flat panel display device is a liquid crystal display device (Liquid CrystAl DisplAy: hereinafter referred to as "LCD"), a field emission display (Field Emission DisplAy: FED), a plasma display panel (PlAsmA DisplAy PAnel: hereinafter, "PDP") And an organic light emitting diode display (OrgAniC Light Emitting Diode DisplAy).

Among these PDPs, PDPs are attracting attention as a display device that is most advantageous for large screen size but large screen size because of simple structure and manufacturing process, but it has disadvantage of low luminous efficiency, low luminance and high power consumption. In addition, an active matrix LCD having a thin film transistor (“TFT”) applied as a switching device has a disadvantage in that it is difficult to make a large screen due to the semiconductor process and consumes a lot of power due to the backlight unit.

In contrast, organic light emitting diode display devices are classified into inorganic light emitting diode display devices and organic light emitting diode display devices according to the material of the light emitting layer. The organic light emitting diode display devices are self-luminous devices that emit light and have high response speed, high luminous efficiency, high luminance, and a wide viewing angle. . In comparison with the organic light emitting diode display, the inorganic light emitting diode display has higher power consumption and cannot obtain high brightness, and cannot emit various colors of R (Red), G (Green), and B (Blue). On the other hand, the organic light emitting diode display is driven at a low DC voltage of several tens of volts, has a fast response speed, obtains high luminance, and emits various colors of R, G, and B, which is suitable for next-generation flat panel display devices. Do.

In the organic light emitting diode display, when a voltage is applied between the anode 100 and the cathode 70 as shown in FIG. 1, electrons generated from the cathode 70 are transferred to the electron injection layer 78A and the electron transport layer ( 78B) is moved toward the organic light emitting layer 78C. Further, holes generated from the anode 100 move toward the organic light emitting layer 78C through the hole injection layer 78e and the hole transport layer 78d. Accordingly, in the organic light emitting layer 78C, light is generated by collision and recombination of electrons and holes supplied from the electron transport layer 78B and the hole transport layer 78d, and the light is emitted to the outside through the anode 100. The image is displayed.

FIG. 2 is a block diagram schematically illustrating a conventional organic light emitting diode display. Referring to FIG. 2, a conventional organic light emitting diode display is arranged in an area defined by the intersection of a gate line GL and a data line DL. The display panel 20 including the pixels 28, the gate driving circuit 22 driving the gate lines GL of the display panel 20, and the data lines DL of the display panel 20. For controlling the data driver circuit 24 for driving the data driver circuit 24, the gamma voltage generator 26 for supplying a plurality of gamma voltages to the data driver circuit 24, and the data driver circuit 24 and the gate driver circuit 22. A timing controller 27 is provided.

In the display panel 20, pixels 28 are arranged in a matrix. In addition, the display panel 20 is provided with a supply pad 10 for receiving a high potential voltage from an external high potential voltage source VDD and a base pad 12 for receiving a base voltage from an external base voltage source GND. do. (For example, the supply voltage source VDD and the ground voltage source GND may be supplied from the power supply unit.) The high potential voltage supplied to the supply pad 10 is supplied to each of the pixels 28. The base voltage supplied to the base pad 12 is supplied to the respective pixels 28.

The gate driving circuit 22 sequentially drives the gate lines GL by supplying gate signals to the gate lines GL.

The gamma voltage generator 26 supplies a gamma voltage having various voltage values to the data driving circuit 24.

The data driving circuit 24 converts the digital data signal input from the timing controller 27 into an analog data signal using the gamma voltage from the gamma voltage generator 26. The data driving circuit 24 supplies an analog data signal to the data lines DL whenever the gate signal is supplied.

The timing controller 27 generates a data control signal for controlling the data driving circuit 24 and a gate control signal for controlling the gate driving circuit 22 using a plurality of synchronization signals. The data control signal generated by the timing controller 27 is supplied to the data driving circuit 24 to control the data driving circuit 24. The gate control signal generated by the timing controller 27 is supplied to the gate driving circuit 22 to control the gate driving circuit 22. In addition, the timing controller 27 supplies a digital data signal supplied from the scaler to the data driving circuit 24.

Each of the pixels 28 receives a data signal from the data line DL when the gate signal is supplied to the gate line GL, and generates light corresponding to the data signal.

To this end, each of the pixels 28 includes an organic light emitting diode OLED and a gate line connected to a base voltage source GND (voltage supplied from the base pad 12) as shown in FIG. 3. GL, a data line DL, and a high potential voltage source VDD (voltage supplied from the supply pad 10) and an anode of the organic light emitting diode OLED to connect the organic light emitting diode OLED. A cell driving circuit 30 for driving is provided.

The cell driving circuit 30 includes a switching TFT T1 having a gate connected to the gate line GL, a source connected to the data line DL, and a drain connected to the node N, and a node N. A driving TFT T2 having a gate connected to it, a source connected to the high potential voltage source VDD, and a drain connected to the organic light emitting diode element OLED, and a connection between the high potential voltage source VDD and the node N; Capacitor C is provided.

The switching TFT Tl is turned on when a gate signal is supplied to the gate line GL to supply a data signal supplied to the data line DL to the node N. [ The data signal supplied to the node N is charged to the capacitor C and supplied to the gate of the driving TFT T2. The driving TFT T2 controls the amount of light emitted from the organic light emitting diode OLED by controlling the amount of current I supplied from the high potential voltage source VDD to the organic light emitting diode OLED in response to the data signal supplied to the gate. Done. Then, even when the switching TFT T1 is turned off, the driving TFT T2 maintains the driving current I to emit light of the organic light emitting diode OLED by one frame by the data signal stored in the capacitor C. To be. Here, the actual cell driving circuit 30 may be set in various structures in addition to the above-described structure.

However, in general, when the gate voltage of the same polarity is applied for a long time in the organic light emitting diode display device driven as described above, the threshold voltage Vth of the driving TFT T2 increases, causing a change in operating characteristics. Such a change in the operating characteristics of the driving TFT T2 can also be seen from the experimental results of FIG. 4.

FIG. 4 shows a case where positive gAte-BiAs stress is applied to a hydrogenated amorphous silicon TFT (A-Si: H TFT) for a sample having a channel width / channel length (W / L) of 120 μm / 6 μm. It is an experimental result showing that the characteristic change of the A-Si: H TFT for a sample is brought about. In Fig. 4, the horizontal axis represents the gate voltage [V] of the sample A-Si: H TFT, and the vertical axis represents the current [A] between the source terminal and the drain terminal of the sample A-Si: H TFT. The index in the box represents the gate voltage application time [seC] for each graph color.

4 shows the shift of the threshold voltage and the transfer characteristic curve of the TFT according to the voltage application time when a voltage of +30 V is applied to the gate terminal of the sample A-Si: H TFT. As can be seen in FIG. 4, as the time for applying the positive voltage to the gate terminal of the A-Si: H TFT increases, the transfer characteristic curve of the TFT shifts 31 to the right, and the threshold of the A-Si: H TFT Voltage rises. (Threshold voltage rises from Vth ₁ to Vth ₄ )

When the threshold voltage of the driving TFT T2 rises as described above, the operation of the driving TFT T2 becomes unstable, so that the current I flowing through the organic light emitting diode OLED is reduced even when the same data voltage Vd is applied. Done.

FIG. 5 is a diagram illustrating a decrease in current I of the organic light emitting diode OLED according to an increase in the threshold voltage Vth of the driving TFT T2. As shown in FIG. 5, when the threshold voltage Vth of the driving TFT T2 rises from 1V to 5V, the current flowing through the organic light emitting diode OLED even if the same data voltage (when Vd = 4V) is applied. (I) gradually decreases from 550nA and eventually converges to 0A.

As a result, in the conventional organic light emitting diode display, even if the same data voltage Vd is applied, luminance unevenness occurs due to the deviation of the driving current I depending on the threshold voltage characteristic of the driving TFT T2. There is a problem that the quality is degraded.

Accordingly, it is an object of the present invention to provide an organic light emitting diode display and a method of driving the same which can improve display quality by minimizing the amount of change in driving current.

In order to achieve the above object, according to an embodiment of the present invention, an organic light emitting diode device, a first node and the base voltage source, the data lines and the gate lines are intersected and formed between a driving voltage source and a base voltage source to emit light by a driving current. An organic light emitting diode display device having a capacitor connected therebetween and a driving element controlling a current flowing through the organic light emitting diode element according to a voltage applied to a gate through the first node, the data line to which a data voltage is supplied. ; A first gate line supplied with a first scan pulse; A second gate line supplied with a second scan pulse subsequent to the first scan pulse; After charging the first node with a reset voltage obtained by subtracting the threshold voltage of the first switch element disposed in one pixel with the driving element from the voltage of the first scan pulse, the data voltage is set to the data. During the second period supplied to the line, in response to the second scan pulse, a third switch device between the second node separated from the first node and the data line is turned on to turn the second node to the data voltage. Charging and discharging the reset voltage to a data voltage to which the threshold voltage of the second switch element is added using a second switch element between the first node and the second node and simultaneously charging the second capacitor to the capacitor. After charging the data voltage to which the threshold voltage of the switch device is added, the switch device is turned off for a third period to drive the driving device to the voltage of the first node. A switch driving circuit for driving is provided.

The first period is determined as a period including a high logic period of the first scan pulse and a rising edge of the second scan pulse, and the second period is a high logic period of the second scan pulse and the second scan. The third period is determined as the low logical period of the second scan pulse.

The driving element and the plurality of switch elements are N-type electron metal oxide semiconductor field effect transistors.

The driving device and the plurality of switch devices include a semiconductor layer formed of an amorphous silicon layer.

The drive element includes a gate connected to the first node, a drain connected to the cathode of the organic light emitting diode element, and a source connected to the base voltage source.

The first switch element includes a gate and a drain commonly connected to the first gate line, and a source connected to the first node.

The second switch element includes a gate and a drain commonly connected to the first node, and a source connected to the second node.

The third switch element includes a gate connected to the second gate line, a drain connected to the data line, and a source connected to the second node.

The current I _OLED flowing through the organic light emitting diode device during the third period is represented by the following equation.

Here, Vth _DR is a driving device threshold voltage for turning on the driving device, Vth2 is the second switching device threshold voltage, I _OLED is a driving current, and kn is a constant value determined by mobility and parasitic capacitance of the driving device. , Vgs denotes the voltage difference between the gate and the source of the driving element, and Vd denotes the data voltage, respectively.

In addition, the organic light emitting diode display according to the exemplary embodiment of the present invention may suppress the overcurrent flowing through the organic light emitting diode element during the first period due to the reset voltage charged in the first node. An overcurrent suppression capacitor is further provided between the cathodes of the light emitting diodes.

In addition, the organic light emitting diode display according to the exemplary embodiment of the present invention has a gate of the first switch element in order to suppress an overcurrent flowing through the organic light emitting diode element during the first period due to the reset voltage charged to the first node. And an overcurrent suppression switch element between the drain and the cathode of the organic light emitting diode.

According to an exemplary embodiment of the present invention, an organic light emitting diode device intersecting data lines and gate lines and formed between a driving voltage source and a base voltage source to emit light by a driving current, a capacitor connected between a first node and the base voltage source, and In a driving method of an organic light emitting diode display device having a driving element that controls a current flowing through the organic light emitting diode element according to a voltage applied to a gate through the first node, a first scan pulse is supplied to a first gate line. Then supplying a second scan pulse to the second gate line; Charging the first node with a reset voltage which lowers the voltage of the first scan pulse by a threshold voltage of a first switch element disposed in one pixel together with the driving element for a first period; During the second period in which the data voltage is supplied to the data line, the second node separated from the first node is charged with the data voltage in response to the second scan pulse and disposed in one pixel together with the driving element. Discharging the reset voltage to the data voltage to which the threshold voltage of the second switch element is added and simultaneously charging the capacitor with the data voltage to which the threshold voltage of the second switch element is added; And driving the driving device with the voltage of the first node for a third period of time.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6 to 19.

6 to 13 show a first embodiment of the present invention.

6 is a block diagram illustrating an organic light emitting diode display according to a first exemplary embodiment of the present invention, and FIG. 7 is a scan pulse S [n-1], which is supplied to any one of the pixels 122 of FIG. S [n]) is a timing diagram.

6 and 7, an organic light emitting diode display according to a first embodiment of the present invention includes a display panel 116 on which m × n pixels 122 are formed, and data lines DL1 to DLm. Scan pulses S1 [0] through the data driving circuit 120 for supplying the data voltage to the gate lines and gate lines GL1 [0] through GL1 [n] crossing the data lines DL1 through DLm. A gate driving circuit 118 for supplying S1 [n], and a timing controller 124 for controlling the data driving circuit 120 and the gate driving circuit 118.

The display panel 116 includes pixels 122 formed in pixel areas defined by intersections of n gate lines GL1 [1] to GL1 [n] and m data lines DL1 to DLm. . Signal lines for supplying a driving voltage to the respective pixels 122 are formed in the display panel 116. Although not shown, signal lines for supplying a base voltage to each of the pixels 122 are formed in the display panel 116. The gate line GL [0] is for supplying a reset voltage to the pixels 122 positioned in the first horizontal line.

The data driving circuit 120 converts the digital video data RGB from the timing controller 124 into an analog data voltage. The data driving circuit 120 supplies the data voltages to the data lines DL1 to DLm in response to the control signal DDC from the timing controller 124. This data voltage is supplied to the pixels 122 connected to the data lines DL1 to DLm.

The gate driving circuit 118 sequentially scans the scan pulse S shown in FIG. 7 to the gate lines GL1 [0] to GL1 [n] in response to the control signal GDC from the timing controller 124. Supply. The scan pulse S is supplied to the pixels 122 connected to the gate lines GL1 [1] to GL1 [n].

The timing controller 124 supplies digital video data RGB to the data driving circuit 120 and operates timings of the gate driving circuit 118 and the data driving circuit 120 using vertical / horizontal synchronization signals and clock signals. It generates a control signal (DDC, GDC) for controlling.

In the timing diagram of FIG. 7, A is a reset section for supplying a reset voltage to the gate of the driving TFT for driving the pixels 122, and B is an organic light emitting diode element corresponding to a change in the threshold voltage of the driving TFT. Compensation section for minimizing the variation of the driving current flowing through the OLED), and C denotes that the organic light emitting diode (OLED) is emitted by an analog gamma voltage corresponding to the gray level of the digital video data regardless of the threshold voltage change of the driving TFT. Light emitting section. Here, the reset section A is determined by the period between the high logic period of the front scan pulse S [n-1] and the rising edge of the rear scan pulse S [n], and the compensation section B is the rear end. It is determined by the period between the high logic period of the scan pulse S [n] and the falling edge of the subsequent scan pulse S [n]. In addition, the light emitting period C is determined by the low logic period of the trailing scan pulse S2 [n]. The operation of the pixels 122 in A, B, and C will be described in detail with reference to FIGS. 9 to 11.

The display panel 116 is connected to a driving voltage source VDD for supplying a driving voltage to the pixels 122, and a ground voltage source GND for supplying a base voltage to the pixels 122.

Each of the pixels 122 includes an organic light emitting diode OLED, one driving TFT, three switch TFTs, and one capacitor as shown in FIG. 8.

8 is a circuit diagram illustrating a pixel 122 included in an organic light emitting diode display according to a first exemplary embodiment of the present invention.

Referring to FIG. 8, the pixel 122 according to the first exemplary embodiment of the present invention emits organic light according to driving signals supplied from the data lines DL1 to DLm and the gate lines GL [0] to GL [n]. The organic light emitting diode device driving circuit 130 for driving the diode device OLED is connected between the organic light emitting diode device driving circuit 130 and the driving voltage source VDD and emits light according to the driving signal. OLED).

The organic light emitting diode driving circuit 130 includes a driving TFT DR for controlling the driving current I _OLED of the organic light emitting diode _OLED , and a gate G of the first node N1: the driving TFT DR. The first switch TFT (SW1) for supplying the reset voltage to the)), the third switch TFT (SW3) for supplying the data voltage (Vp) to the second node (N2) charged in the first node (N1) And a second switch TFT (SW2) for discharging the reset voltage to the compensation voltage value, and a capacitor (C) for storing the reset voltage and the compensation voltage. Here, the TFTs are N-type electron metal oxide semiconductor field effect transistors (MOSFETs, MetAl-Oxide SemiConduCtor Field EffeCt TrAnsistor). In particular, the semiconductor layers of the TFTs are formed of an amorphous silicon layer so that the amount of change in the threshold voltage between the TFTs due to the same gate bias stress is almost the same.

The gate G of the driving TFT DR is connected to the first node N1, the drain D of the driving TFT DR is connected to the cathode of the organic light emitting diode device OLED, and the driving TFT DR The source of is connected to the ground voltage source GND. The driving TFT DR controls the current flowing through the organic light emitting diode OLED according to the voltage applied to the gate G through the first node N1.

The gate G and the drain D of the first switch TFT SW1 are commonly connected to the front gate line GL [n-1], and the source S of the first switch TFT SW1 is the first node. It is connected to (N1). The first switch TFT SW1 is turned on in response to the front end scan pulse S [n-1] from the front end gate line GL [n-1], whereby the reset voltage is applied to the first node N1. To be supplied. Here, the reset voltage is defined as the difference voltage between the high logic voltage VGH of the front end scan pulse S [n-1] and the threshold voltage Vth1 of the first switch TFT SW1. The reset voltage VGH-Vth1 is charged to the first node N1 through the capacitor C.

The gate G of the third switch TFT SW3 is connected to the rear gate line GL [n], and the drain D of the third switch TFT SW3 is connected to the data line DLk (1 ≦ k ≦ m). ), And the source S of the third switch TFT SW3 is connected to the second node N2. The third switch TFT SW3 is turned on in response to the trailing scan pulse S [n] from the trailing gate line GL [n], so that the data voltage Vd is supplied to the second node N2. To be.

The gate G and the drain D of the second switch TFT SW2 are commonly connected to the first node N1, and the source S of the second switch TFT SW2 is connected to the second node N2. do. The second switch TFT SW2 is turned on in response to the reset voltage VGH-Vth1 charged in the first node N1 to compensate for the reset voltage VGH-Vth1 charged in the first node N1. Discharge to voltage value. The compensation voltage is defined as the sum voltage Vd + Vth2 of the data voltage Vd and the threshold voltage Vth2 of the second switch TFT SW2. The compensation voltage Vd + Vth2 is charged to the first node N1 through the capacitor C.

One side of the capacitor C is connected to the first node N1, and the other side of the capacitor C is connected to the ground voltage source GND. The capacitor C stores the reset voltage VGH-Vth1 supplied to the first node N1 during the high logic period (section A in FIG. 7) of the front end scan pulse S [n-1]. The voltage of the first node N1 during the high logic period (B section in FIG. 7) of the trailing scan pulse S [n] and the low logic period (C section in FIG. 7) of the trailing scan pulse S [n]. Is maintained at the compensation voltage (Vd + Vth2).

The anode of the organic light emitting diode OLED is connected to the driving voltage source VDD, and the cathode is connected to the drain D of the driving TFT DR. The organic light emitting diode OLED has a structure as shown in FIG. 1 and is applied to a driving current I _OLED controlled according to a voltage applied to the gate G of the driving TFT DR through the first node N1. Emits light. Here, the anode of the organic light emitting diode OLED formed of the transparent electrode is formed on the opposite side of the substrate on which the driving TFT DR is formed. Accordingly, the pixels 122 of the organic light emitting diode display according to the present invention emit light according to a top emission method.

The operations of the pixels 122 will be described below with reference to FIGS. 9 through 12.

FIG. 9 is an equivalent circuit diagram of the pixel 122 for the reset period A of FIG. 7.

Referring to FIG. 9, during the reset period A, the front end scan pulse S [n-1] is generated at the high logic voltage VGH to turn on the first switch TFT SW1 and the rear end scan pulse S [n] is generated at the low logic voltage VGL to turn off the third switch TFT SW3. Accordingly, the first switch TFT SW1 operates as a diode turned on at a voltage higher than or equal to the threshold voltage Vth1. Since the forward bias is applied to the diode SW1, the reset voltage Vr as shown in Equation 1 below is charged to the first node N1 through the capacitor C.

Here, VGH denotes a high logic voltage of the front end scan pulse S [n-1], and Vth1 denotes a threshold voltage of the first switch TFT SW1.

This reset voltage Vr is stored and maintained in the capacitor C during the reset period A.

FIG. 10 is an equivalent circuit diagram of the pixel 122 with respect to the compensation section B of FIG. 7.

Referring to FIG. 10, during the compensation period B, the front end scan pulse S [n-1] is inverted to the low logic voltage VGL to turn off the first switch TFT SW1 and the rear end scan pulse. (S [n]) is inverted to the high logic voltage VGH to turn on the third switch TFT SW3. As the third switch TFT SW3 is turned on, the data voltage Vd is supplied to the second node N2. In this case, the second switch TFT SW2 operates as a diode turned on at a voltage equal to or higher than the threshold voltage Vth1. Accordingly, since the reset voltage Vr charged in the first node N1 has a higher potential than the data voltage Vd applied to the second node N2, a forward bias is applied to the diode SW2. Accordingly, the voltage of the first node N1 is discharged from the reset voltage Vr value and converges to the compensation voltage Vd + Vth2 value.

The compensation voltage Vc is stored and maintained in the capacitor C during the compensation period A and the light emission period C.

Here, since the semiconductor layers of the TFTs according to the exemplary embodiment of the present invention are formed of amorphous silicon, the threshold voltage Vth _DR of the driving TFT DR and the threshold voltage Vth2 of the second switch TFT SW2 are almost equal. same. Therefore, the threshold voltage Vth _DR of the driving TFT DR is erased as in Equation 2 below, and as a result, the driving current I _OLED becomes a function of only the data voltage Vd.

Here, Vth _DR is a threshold voltage of the driving TFT DR, Vth2 is a threshold voltage of the second switch TFT SW2, I _OLED is a driving current, and kn is a constant determined by mobility and parasitic capacitance of the driving TFT DR. The value Vgs denotes the difference voltage between the gate and the source of the driving TFT DR, and Vd denotes the data voltage, respectively.

As shown in Equation 2, since the driving current I _OLED is determined as a function of only the data voltage Vd, the driving current I even if the threshold voltage Vth _DR of the driving TFT DR is changed due to the gate bias stress. _OLED ) has little effect.

FIG. 11 is an equivalent circuit diagram of the pixel 122 for the light emitting period C of FIG. 7.

Referring to FIG. 11, the front end scan pulse S [n−1] maintains the low logic voltage VGL to maintain the turn-off state of the first switch TFT SW1 during the light emitting period C, and scans the rear end. The pulse S [n] is inverted to the low logic voltage VGL to turn off the third switch TFT SW3. As the third switch TFT SW3 is turned off, as shown in Equation 2, the organic light emitting diode OLED emits light by the driving current I _OLED determined as a function of the data voltage Vd alone. .

FIG. 12 is a simulation result illustrating a transient state of the voltage V (N1) applied to the first node N1 in the sections A, B, and C of FIG.

Referring to FIG. 12, the voltage V (N1) applied to the first node N1 during the reset period A is charged to the reset voltage Vr = VGH−Vth1 and then discharged during the compensation period B. FIG. It can be seen that the convergence to the compensation voltage (Vc = Vd + Vth2) to satisfy the equation (2).

FIG. 13 is a simulation result to show that the reduction of the driving current is minimized in response to the increase in the threshold voltage Vth _DR of the driving TFT DR when the same gray scale is represented.

As shown in FIG. 5, when the threshold voltage Vth of the driving TFT T2 rises from 1V to 5V, the change amount of the driving current flowing to the organic light emitting diode OLED is applied even if the same data voltage is applied. I) was 100%.

However, as shown in FIG. 13, in the exemplary embodiment of the present invention, even when the threshold voltage Vth _DR of the driving TFT DR rises from 1V to 5V, the driving current flowing through the organic light emitting diode device OLED in the same gray level is measured. It can be seen that the change amount ΔI _OLED is significantly reduced within a maximum of 10%.

In an ideal case, as shown in Equation 2, the variation amounts of the threshold voltages Vth2 and Vth _{DR of} the second switch TFT SW2 and the driving TFT DR are completely the same due to the gate bias stress. In this ideal case, since the driving current I _OLED is determined as a function of the data voltage Vd only, the change amount of the driving current ΔI _OLED with respect to the change of the threshold voltage Vth _DR of the driving TFT DR is 0%. Indicates. However, in actual cases, the second switch TFT SW2 and the driving TFT DR may cause the second by the parasitic capacitance Cgs and Cgd generated by different sizes and the coupling of these Cgd and Cgs. The amount of change in the threshold voltages Vth2 and Vth _{DR of the} switch TFT SW2 and the driving TFT DR is not necessarily the same. Here, Cgs denotes a gate-source parasitic capacitance, and Cgd denotes a gate-drain parasitic capacitance Cgd. As a result, the change amount ΔI _OLED of the driving current with respect to the change of the threshold voltage Vth _DR of the driving TFT DR represents a value of 1% to 10% in inverse proportion to the magnitude of the data voltage applied.

14 to 19 show a second and a third embodiment of the present invention.

14 is a block diagram illustrating an organic light emitting diode display according to a second exemplary embodiment of the present invention.

Referring to FIG. 14, the organic light emitting diode display according to the second exemplary embodiment of the present invention has the same configuration as the organic light emitting diode display according to the first exemplary embodiment except for the pixels 222. Except for the constituent means except for the same reference numerals as in the first embodiment, detailed description thereof will be omitted.

Each of the pixels 222 includes an organic light emitting diode (OLED), one driving TFT, three switch TFTs, and two capacitors as shown in FIG. 15.

15 is a circuit diagram illustrating a pixel 222 included in an organic light emitting diode display according to a second exemplary embodiment of the present invention.

Since the pixel 222 according to the second embodiment of the present invention has the same configuration as the pixel 122 according to the first embodiment except for the overcurrent suppression capacitor Ca, the pixel 222 according to the second embodiment excludes the overcurrent suppression capacitor Ca. The remaining elements are given the same reference numerals as in the first embodiment, and detailed descriptions of their operations will be omitted.

During the reset period (A in FIG. 7), the organic light emitting diode device OLED has a driving current (about 1 mA) corresponding to the white gray level due to the reset voltage (Vr = VGH-Vth1) charged to the first node N1. Large overcurrent will flow instantaneously (see FIG. 18A).

In order to suppress such overcurrent, one side of the overcurrent suppression capacitor Ca is connected to the first node N1, and the other side of the overcurrent suppression capacitor Ca is connected to the drain D of the driving TFT DR. The overcurrent suppression capacitor Ca capacitor-couples the first node N1 and the drain D of the driving TFT DR to thereby convert the potential of the drain D of the driving TFT DR into the overcurrent suppression capacitor Ca. It is raised than before connection. Accordingly, the potential difference between the driving voltage source VDD and the drain D of the driving TFT DR is reduced, so that the amount of overcurrent flowing through the organic light emitting diode OLED is reduced as shown in FIG. 18B.

16 is a block diagram illustrating an organic light emitting diode display according to a third exemplary embodiment of the present invention.

Referring to FIG. 16, the organic light emitting diode display device according to the third embodiment of the present invention has the same configuration as the organic light emitting diode display device according to the first embodiment except for the pixels 322, and thus, the pixels 322. Except for the constituent means except for the same reference numerals as in the first embodiment, detailed description thereof will be omitted.

Each of the pixels 322 includes an organic light emitting diode (OLED), one driving TFT, four switch TFTs, and one capacitor as shown in FIG. 17.

17 is a circuit diagram illustrating a pixel 322 included in an organic light emitting diode display according to a third exemplary embodiment of the present invention.

Since the pixel 322 according to the third embodiment of the present invention has the same configuration as the pixel 122 according to the first embodiment except for the overcurrent suppression switch TFT SWa, the overcurrent suppression switch TFT SWa has the same configuration. Except for the constituent means except for the same reference numerals as in the first embodiment, the detailed description of the operation thereof will be omitted.

During the reset period (A in FIG. 7), the organic light emitting diode device OLED has a driving current (about 1 mA) corresponding to the white gray level due to the reset voltage (Vr = VGH-Vth1) charged to the first node N1. Large overcurrent will flow instantaneously (see FIG. 18A).

In order to suppress such an overcurrent, the gate G and the drain D of the overcurrent suppression switch TFT SWa are commonly connected to the front gate line GL [n-1] and the source of the overcurrent suppression switch TFT SWa. S is connected to the drain D of the driving TFT DR. The overcurrent suppression switch TFT SWa is turned on in response to the front end scan pulse S [n-1] from the front end gate line GL [n-1] and acts as a diode, thereby resetting the reset voltage Vr =. A high potential voltage VGH-Vtha having a magnitude similar to VGH-Vth1 is supplied to the drain D of the driving TFT DR. Accordingly, the potential difference between the driving voltage source VDD and the drain D of the driving TFT DR is reduced than before the overcurrent suppression switch TFT SWa is connected, so that the amount of overcurrent flowing through the organic light emitting diode device OLED as shown in FIG. 18C. Will decrease.

18A to 18C are simulation results illustrating the transient state of the driving current according to the voltage V (N1) applied to the first node N1 during the sections A, B, and C of FIG. FIG. 7A is a simulation result illustrating changes in driving currents of FIGS. 18A to 18C according to an increase in the threshold voltage Vth _DR of the driving TFT DR during the section A of FIG. 7.

18A to 18B, the horizontal axis represents time (s), and the vertical axis represents driving current I _OLED . In FIG. 19, the horizontal axis represents the threshold voltage Vth _DR of the driving device, and the vertical axis represents the driving current I _OLED .

When the overcurrent suppressing means is not provided as in the first embodiment of the present invention, the overcurrent is relatively generated during the reset period A as shown in Fig. 18A. However, when the overcurrent suppressing means Ca and SWa are provided as in the second and third embodiments of the present invention, it is understood that the overcurrent is relatively small during the reset period A as shown in FIGS. 18B and 18C, respectively. Can be. As shown in FIG. 19, the overcurrent generated during the reset period A gradually decreases in inverse proportion to the increase in the threshold voltage Vth _DR of the driving TFT DR.

As described above, the organic light emitting diode display and the driving method thereof according to the embodiment of the present invention allow the driving current flowing through the organic light emitting diode element to be changed only by the data voltage regardless of the threshold voltage change of the driving TFT. The display quality can be improved by minimizing the amount of change in the driving current due to the change of the threshold voltage.

In addition, the organic light emitting diode display and the driving method thereof according to an embodiment of the present invention include an overcurrent suppression means to reduce the magnitude of the instantaneous overcurrent flowing to the organic light emitting diode element during a period in which the reset voltage is supplied to the gate of the driving TFT. Can be.

Furthermore, the organic light emitting diode display and the driving method thereof according to the embodiment of the present invention improve the reliability by minimizing the amount of change of the driving current according to the change of the threshold voltage of the driving TFT, thereby improving the reliability and at the same time the threshold of the driving TFT. It is possible to simply design the display module by omitting additional configuration means for keeping the voltage constant.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (14)

An organic light emitting diode device intersecting the data lines and the gate lines and formed between the driving voltage source and the base voltage source to emit light by the driving current, a capacitor connected between the first node and the base voltage source, and a gate through the first node An organic light emitting diode display device comprising: a driving element for controlling a current flowing through the organic light emitting diode element according to a voltage applied to the organic light emitting diode element; A data line to which a data voltage is supplied; A first gate line supplied with a first scan pulse; A second gate line supplied with a second scan pulse subsequent to the first scan pulse; After charging the first node with a reset voltage obtained by subtracting a threshold voltage of a first switch element disposed in one pixel together with the driving element from the voltage of the first scan pulse, the data voltage is applied to the data line. Charging the second node to the data voltage by turning on a third switch element between the second node separated from the first node and the data line in response to the second scan pulse supplied to the second period. And discharging the reset voltage to a data voltage to which the threshold voltage of the second switch element is added by using a second switch element between the first node and the second node, and simultaneously discharging the reset voltage to the capacitor. After charging the data voltage to which the threshold voltage of the device is added, the switch device is turned off for a third period to drive the driving device to the voltage of the first node. An organic light emitting diode display device comprising: a switch driving circuit for driving. The method of claim 1, The first period is determined as a period including a high logic period of the first scan pulse and a rising edge of the second scan pulse, and the second period is a high logic period of the second scan pulse and the second scan. And a third period is determined by a low logic period of the second scan pulse. The method of claim 2, And the driving elements and the plurality of switch elements are N-type electron metal oxide semiconductor field effect transistors. The method of claim 3, wherein And the driving device and the plurality of switch devices include a semiconductor layer formed of an amorphous silicon layer. 5. The method of claim 4, The driving device, And a gate connected to the first node, a drain connected to the cathode of the organic light emitting diode element, and a source connected to the base voltage source. 6. The method of claim 5, The first switch device, And a gate and a drain commonly connected to the first gate line, and a source connected to the first node. The method of claim 6, The second switch device, And a gate and a drain commonly connected to the first node, and a source connected to the second node. The method of claim 7, wherein The third switch device, And a gate connected to the second gate line, a drain connected to the data line, and a source connected to the second node. The method of claim 1, An organic light emitting diode display device, wherein the current I _OLED flowing through the organic light emitting diode device during the third period is as follows.

Here, Vth _DR is a driving device threshold voltage for turning on the driving device, Vth2 is the second switching device threshold voltage, I _OLED is a driving current, and kn is a constant value determined by mobility and parasitic capacitance of the driving device. , Vgs denotes the voltage difference between the gate and the source of the driving element, and Vd denotes the data voltage, respectively. 9. The method of claim 8, An overcurrent suppression capacitor is further provided between the first node and the cathode of the organic light emitting diode to suppress the overcurrent flowing through the organic light emitting diode element during the first period due to the reset voltage charged in the first node. An organic light emitting diode display device. 9. The method of claim 8, Overcurrent suppression switch element between the gate and the drain of the first switch element and the cathode of the organic light emitting diode to suppress the overcurrent flowing in the organic light emitting diode element during the first period due to the reset voltage charged to the first node An organic light emitting diode display further comprising. An organic light emitting diode device intersecting the data lines and the gate lines and formed between the driving voltage source and the base voltage source to emit light by the driving current, a capacitor connected between the first node and the base voltage source, and a gate through the first node A driving method of an organic light emitting diode display device having a driving element for controlling a current flowing through the organic light emitting diode element according to a voltage applied to the organic light emitting diode device, Supplying a second scan pulse to the second gate line after supplying the first scan pulse to the first gate line; Charging the first node with a reset voltage which lowers the voltage of the first scan pulse by a threshold voltage of a first switch element disposed in one pixel together with the driving element for a first period; During the second period in which the data voltage is supplied to the data line, the second node separated from the first node is charged with the data voltage in response to the second scan pulse and disposed in one pixel together with the driving element. Discharging the reset voltage to the data voltage to which the threshold voltage of the second switch element is added and simultaneously charging the capacitor with the data voltage to which the threshold voltage of the second switch element is added; And And driving the driving device with the voltage of the first node for a third period of time. 13. The method of claim 12, The first period is determined as a period including a high logic period of the first scan pulse and a rising edge of the second scan pulse, and the second period is a high logic period of the second scan pulse and the second scan. And a third period is determined by a low logic period of the second scan pulse. 14. The method of claim 13, The current (I _OLED ) flowing in the organic light emitting diode device during the third period is as shown in the following equation.

Here, Vth _DR is a driving device threshold voltage for turning on the driving device, Vth2 is the second switching device threshold voltage, I _OLED is a driving current, and kn is a constant value determined by mobility and parasitic capacitance of the driving device. , Vgs denotes the voltage difference between the gate and the source of the driving element, and Vd denotes the data voltage, respectively.

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