KR101287202B1 - Image display device - Google Patents

Abstract

The present invention relates to an image display apparatus capable of reducing power consumption.

An image display device according to the present invention comprises a liquid crystal panel in which a liquid crystal cell is formed in an area defined by a plurality of data lines and a plurality of gate lines, a first synchronization signal and data, and generating a mode signal according to the image mode of the data. A system for generating an image, a panel driver for displaying an image on the liquid crystal panel, a timing controller for driving the panel driver in a normal mode or a power saving mode according to the mode signal, and a backlight for irradiating light to the liquid crystal panel. Characterized in that it comprises a.

According to this configuration, the present invention can reduce the overall power consumption due to the power saving mode by switching to the normal mode or the power saving mode according to the mode signal corresponding to the still image or the moving image of the input data. By modulating, the response speed of the liquid crystal cell may be increased to reduce motion blur when moving images are implemented.

Power Consumption, Power Saving Mode, Normal Mode

Description

Image display device {IMAGE DISPLAY DEVICE}

1 is a diagram schematically showing a conventional image display apparatus.

2 is a diagram schematically showing an image display device according to a first embodiment of the present invention;

3 is a circuit diagram schematically illustrating a mode signal generator according to a first embodiment of the present invention.

4 is a view illustrating a signal flow in a normal mode according to the present invention.

5 is a view showing a signal flow in the power saving mode according to the present invention.

6 is a state transition diagram showing mode switching by a mode signal according to the present invention.

7 is a waveform diagram showing power consumption of an image display device according to a first embodiment of the present invention;

8 is a diagram schematically showing an image display device according to a second embodiment of the present invention.

9 is a diagram schematically showing an image display device according to a third embodiment of the present invention.

10 is a circuit diagram schematically illustrating a mode signal generator according to a second embodiment of the present invention.

FIG. 11 schematically illustrates an image display device according to a fourth embodiment of the present invention. FIG.

12 is a circuit diagram schematically illustrating a mode signal detector according to a first embodiment of the present invention.

13 is an input / output waveform diagram of a mode signal detector according to a first embodiment of the present invention;

14 is a circuit diagram schematically illustrating a mode signal detector according to a second embodiment of the present invention.

15 is a circuit diagram schematically illustrating a mode signal detector according to a third embodiment of the present invention.

FIG. 16 schematically shows an image display device according to a fifth embodiment of the present invention; FIG.

17 is a block diagram schematically illustrating an image analyzer according to an exemplary embodiment of the present invention.

18 is a waveform diagram showing power consumption of an image display device according to a fifth embodiment of the present invention;

19 is a diagram schematically showing an image display device according to a sixth embodiment of the present invention.

20 schematically illustrates an image display device according to a seventh embodiment of the present invention.

21 is a diagram schematically showing an image display device according to an eighth embodiment of the present invention.

Description of the Related Art [0002]

102: liquid crystal panel 104: data driver

106: gate driver 108: gamma voltage supply

110: timing controller 112: memory

114: Lookup Table 120: System

122: central processing unit 124: graphics chip

128: mode signal generator 130: power supply

134: inverter 136: backlight

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display apparatus, and more particularly to an image display apparatus capable of reducing power consumption.

Recently, various flat panel display devices that can reduce weight and volume, which are disadvantages of cathode ray tubes, have emerged. Examples of such flat panel display devices include a liquid crystal display, a field emission display, a plasma display panel, and a light emitting display.

Among the flat panel displays, liquid crystal displays are actively applied to notebooks, desktop monitors, and mobile terminals due to their excellent resolution, color display, and image quality.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel having a liquid crystal cell, a backlight for irradiating light to the liquid crystal panel, and a driving circuit for driving the liquid crystal cell.

1 is a block diagram schematically showing an image display apparatus according to the prior art.

Referring to FIG. 1, an image display apparatus according to the related art includes a liquid crystal panel 2 in which a liquid crystal cell Clc is formed in a region defined by a plurality of data lines DL1 through DLm and a plurality of gate lines GL1 through GLn. ), A data driver 4 for supplying a video signal to the data lines DL1 to DLm of the liquid crystal panel 2, and a gate driver 6 for supplying a scan signal to the gate lines GL1 to GLn. ), The gamma voltage supply unit 8 for supplying the gamma voltage to the data driver 4, and the synchronization driver CS supplied from the system 20, thereby providing the data driver 4 and the gate driver 6 with each other. A timing controller 10 for controlling, a power supply unit 30 for generating voltages for driving, a backlight 36 for irradiating light to the liquid crystal panel 2, and driving the backlight 36. An inverter 34 is provided.

The system 20 supplies a synchronization signal CS including a vertical / horizontal synchronization signal, a clock signal, and a data enable signal, and source data Data to the timing controller 10, and supplies power to the power supply unit 30. Supply the voltage Vin.

To this end, the system 20 includes a central processing unit 22, a graphic chip 24, and a peripheral 26.

The central processing unit 22 controls the driving of the graphics chip 22 and the peripheral device 26.

The graphic chip 22 generates the synchronization signal CS and the source data Data under the control of the CPU 22 and supplies the same to the timing controller 10.

The peripheral device 26 is a device driven under the control of the CPU 22, and may be a storage medium or a communication device of a computer system or a notebook system.

The liquid crystal panel 2 includes a thin film transistor formed at each intersection of the data lines DL1 to DLm and the gate lines GL1 to GLn, and the liquid crystal cell Clc connected to the thin film transistor. Each thin film transistor supplies a video signal supplied from the data lines DL1 to DLm to the liquid crystal cell Clc in response to a scan signal supplied from the gate line GL. In addition, a storage capacitor Cst is formed in each of the liquid crystal cells Clc. The storage capacitor Cst is formed between the pixel electrode of the liquid crystal cell Clc and the front gate line, or is formed between the pixel electrode of the liquid crystal cell Clc and the common electrode line to maintain a constant voltage of the liquid crystal cell Clc. Let's do it.

On the other hand, since the response speed of the liquid crystal cell Clc is longer than one frame period (NTSC: 16.67 ms) of the video, the video is displayed in the video because the voltage charged in the liquid crystal cell Clc proceeds to the next frame before reaching the desired voltage. This blurring motion burring phenomenon appears.

In order to solve the slow response speed of the liquid crystal cell, an image display apparatus according to the related art uses a memory 12 and a look up table 14 to modulate a data signal according to a change in a data signal. It further comprises a driving circuit.

The timing controller 10 generates gate and data control signals GCS and DCS for controlling the gate driver 6 and the data driver 4 using the synchronization signal CS input from the system 20. The gate control signal GCS includes a gate start pulse, a gate shift clock, and a gate output enable. The data control signal DCS includes a source start pulse, a source shift clock, a source output signal, and a polarity signal.

The timing controller 10 aligns the source data Data supplied from the graphic chip 24 of the system 20 and stores the aligned data signals in the memory 12 in units of frames. The lookup table 14 includes modulation data for increasing the response speed of the liquid crystal cell.

Accordingly, the timing controller 10 compares the aligned data signal of the current frame with the data signal of the previous frame stored in the memory 12, and according to the comparison result, modulated data RGB listed in the lookup table 14. Supply to the data driver 4.

The gamma voltage supply unit 8 generates a plurality of gamma reference voltages using the driving voltage supplied from the power supply unit 30, and supplies the generated gamma reference voltages to the data driver 4.

The data driver 4 converts the modulation data RGB into an analog gamma voltage (video signal) corresponding to the gray scale value in response to the data control signal DCS from the timing controller 10, and converts the analog gamma voltage into data. Supply to the lines DL1 to DLm.

The gate driver 6 sequentially supplies a scan signal to the gate lines GL1 to GLn in response to the gate control signal GCS from the timing controller 10, so that the video signal is supplied horizontally. Select a line.

The power supply unit 30 generates a voltage necessary for driving the liquid crystal panel 2 using the power supply voltage Vin supplied from the system 20 and supplies it to each device.

The inverter 34 generates a lamp driving voltage VL for driving the backlight 36 using the power supply voltage Vin supplied from the system 20 and supplies it to the backlight 36.

The backlight 36 generates light corresponding to the lamp driving voltage VL supplied from the inverter 34 and irradiates the rear surface of the liquid crystal panel 2.

Such a conventional image display device generates a modulation data according to the change of the source data (Data) from the system 20 to drive the liquid crystal cell (Clc) to increase the response speed of the liquid crystal when the video is implemented, the motion blur phenomenon Can be reduced.

However, the conventional image display device has a problem that power consumption is increased because it modulates the source data into modulated data regardless of a moving picture or a still image and always generates light of a constant brightness. There is a problem that the use time is short.

Accordingly, in order to solve the above problems, an object of the present invention is to provide an image display device capable of reducing power consumption.

An image display device according to an exemplary embodiment of the present invention for achieving the above object generates a liquid crystal panel in which a liquid crystal cell is formed in an area defined by a plurality of data lines and a plurality of gate lines, and a first synchronization signal and data. A system for generating a mode signal in accordance with an image mode of the data, a panel driver for displaying an image on the liquid crystal panel, a timing controller for driving the panel driver in a normal mode or a power saving mode in accordance with the mode signal; It characterized in that it comprises a backlight for irradiating light to the liquid crystal panel.

The system includes a graphics chip for generating the first synchronization signal and the data, a mode signal generator for generating a mode signal according to the image mode of the data, and the system in the power saving mode or the normal mode according to the mode signal. And a central processing unit for generating a variable brightness signal corresponding to the input signal of the user for controlling the brightness of the liquid crystal panel.

The panel driver includes a data driver for supplying a video signal to the data line under control of the timing controller, a gate driver for supplying a scan signal to the gate line under control of the timing controller, and the brightness variable signal. In accordance with, characterized in that configured to include an inverter for driving the backlight.

The image display device may further include a first memory for storing the data supplied from the timing controller, and a lookup table including modulation data for increasing a response speed of the liquid crystal cell.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

2 is a schematic view of an image display device according to a first embodiment of the present invention.

Referring to FIG. 2, in the image display apparatus according to the first exemplary embodiment, the liquid crystal cell Clc is formed in an area defined by the plurality of data lines DL1 through DLm and the plurality of gate lines GL1 through GLn. The formed liquid crystal panel 102, a system 120 for generating a first synchronization signal CS1 and source data Data1 and generating a mode signal SSR according to the image mode of the source data Data1, and a liquid crystal panel The panel driver 140 for displaying an image on the 102, the timing controller 110 for driving the panel driver 140 in the normal mode or the power saving mode according to the mode signal SSR, and the liquid crystal panel 102. And a backlight 136 for irradiating light.

The liquid crystal panel 102 includes a thin film transistor formed at each intersection of the data lines DL1 to DLm and the gate lines GL1 to GLn, and the liquid crystal cell Clc connected to the thin film transistor. Each thin film transistor supplies a video signal supplied from the data lines DL1 to DLm to the liquid crystal cell Clc in response to a scan signal supplied from the gate line GL. In addition, a storage capacitor Cst is formed in each of the liquid crystal cells Clc. The storage capacitor Cst is formed between the pixel electrode of the liquid crystal cell Clc and the front gate line, or is formed between the pixel electrode of the liquid crystal cell Clc and the common electrode line to maintain a constant voltage of the liquid crystal cell Clc. Let's do it.

The system 120 supplies the first synchronization signal CS1 and the source data Data1 including the vertical / horizontal synchronization signal, the clock signal, and the data enable signal to the timing controller 110, and supplies a power supply voltage Vin. Supply to the panel driver 140.

To this end, the system 120 includes a central processing unit 122, a graphic processing unit 124, a peripheral device 126, and a mode signal generator 128. Here, the graphic chip 124 and the mode signal generator 128 may be configured as one graphic module.

The CPU 122 controls the graphic chip 124, the peripheral device 126, and the mode signal generator 128. In addition, the CPU 122 drives the system 120 in the normal mode or the power save mode according to the mode signal SSR from the mode signal generator 128.

The graphic chip 124 generates the first synchronization signal CS1 and the source data Data1 under the control of the CPU 122, and supplies the generated graphics signal to the timing controller 110.

The peripheral device 126 is a device driven under the control of the central processing unit 122 and may be a storage medium or a communication device of a computer system or a notebook system.

The mode signal generator 128 includes a memory 200 and a comparator 202 as shown in FIG. 3.

The memory 200 stores the source data Data1 from the graphic chip 124 in units of frames and supplies the stored source data Data1 in units of frames to the comparator 202. Here, the memory 200 may be mounted as the peripheral device 126 of the system 120 or may be a memory means that is one of the peripheral devices 126.

The comparator 202 compares the source data Data1 of the current frame Fn supplied from the graphic chip 124 with the source data Data1 of the previous frame Fn-1 supplied from the memory 200. Generate signal SSR. That is, when the image of the current frame Fn and the image of the previous frame Fn-1 are the same, the comparator 202 generates a mode signal SSR having a high state by determining that the image is a still image. If not, it determines to be a moving image and generates a mode signal SSR in a low state. The mode signal SSR is supplied to the CPU 122 and the timing controller 110.

The CPU 122 switches the system 120 to the power saving mode in response to the mode signal SSR in the high state from the mode signal generator 128. In the power saving mode, the devices inside the system 120 are switched to the power saving mode except for the central processing unit 122 to the standby mode consuming the minimum power. Therefore, the first synchronization signal CS1 and the source data Data1 supplied from the graphic chip 124 to the timing controller 110 are blocked.

In addition, the CPU 122 switches the system 120 to the normal mode in response to the mode signal SSR in the low state from the mode signal generator 128. In the normal mode, the devices inside the system 120 perform normal operations under the control of the CPU 122. Therefore, the graphic chip 124 generates the first synchronization signal CS1 and the source data Data1 and supplies the same to the timing controller 110.

The central processing unit 122 generates a brightness variable signal LVS corresponding to a user input signal for adjusting the brightness of the liquid crystal panel 102 and supplies it to the inverter 134.

In FIG. 2, the timing controller 110 drives the panel driver 140 in a power saving mode according to a high mode signal SSR input from the system 120, or a low mode input from the system 120. The panel driver 140 is driven in the normal mode according to the signal SSR.

In the normal mode, as shown in FIG. 4, the timing controller 110 controls the gate driver 106 and the data driver 104 by using the first synchronization signal CS1 input from the system 120. The gate and data control signals GCS and DCS are generated. The gate control signal GCS includes a gate start pulse, a gate shift clock, and a gate output enable. The data control signal DCS includes a source start pulse, a source shift clock, a source output signal, and a polarity signal.

The timing controller 110 generates the modulation data RGB for increasing the response speed of the liquid crystal cell using the memory 112 and the lookup table 114 and supplies the modulation data RGB to the data driver 104. In detail, the timing controller 110 aligns the source data Data1 supplied from the graphic chip 124 of the system 120 and stores the aligned data signal Data1 in the memory 112 in units of frames. The lookup table 114 includes modulation data for increasing the response speed of the liquid crystal cell.

Accordingly, the timing controller 110 compares the sorted data signal Data1 of the current frame with the sorted data signal Data2 of the previous frame stored in the memory 112, and the lookup table 114 according to the comparison result. Modulated data (RGB) listed in the above is supplied to the data driver 104.

On the other hand, in the power saving mode, as shown in FIG. 5, the timing controller 110 controls the gate driver 106 and the data driver 104 by using a second synchronization signal generated from an internal clock generator (not shown). To generate gate and data control signals GCS and DCS. Here, the internal clock generator generates a second synchronization signal identical to the first synchronization signal CS1 generated by the graphic chip 124 of the system 120.

The timing controller 110 supplies the data signal Data2 of the previous frame stored in the memory 112 to the data driver 104. At this time, in the power saving mode, the memory 112 may only perform a read operation.

As a result, the timing controller 110 reads the data signal Data2 of the previous frame stored in the memory 112 and supplies it to the data driver 104 until the power saving mode is switched to the normal mode.

In FIG. 2, the panel driver 140 provides a data driver 104 for supplying a video signal to the data lines DL1 to DLm of the liquid crystal panel 102 and scan signals to the gate lines GL1 to GLn. The gate driver 106 for supplying, the gamma voltage supply 108 for supplying the gamma voltage to the data driver 104, the power supply 130 for generating the voltages required for driving, and the backlight 136 And an inverter 134 for driving.

The gamma voltage supply unit 108 generates a plurality of gamma reference voltages using the driving voltage supplied from the power supply unit 130, and supplies the generated gamma reference voltages to the data driver 104.

The data driver 104 supplies the modulated data RGB or the previous signal data signal Data2 supplied from the timing controller 110 according to the mode signal SSR in response to the data control signal DCS from the timing controller 110. ) Is converted into an analog gamma voltage (video signal) corresponding to the gray scale value, and the analog gamma voltage is supplied to the data lines DL1 to DLm.

The gate driver 106 sequentially supplies a scan signal to the gate lines GL1 to GLn in response to the gate control signal GCS from the timing controller 110 to supply the video signal to the horizontal line of the liquid crystal panel 102. Select a line.

The power supply unit 130 generates a voltage for driving the liquid crystal panel 102 by using the power supply voltage Vin supplied from the system 120 and supplies the generated voltage to each device.

The inverter 134 generates a lamp driving voltage VL for driving the backlight 136 using the power supply voltage Vin supplied from the system 120 and supplies the generated driving voltage VL to the backlight 136. In this case, the inverter 134 adjusts the brightness of the backlight 136 by varying the lamp driving voltage VL according to the brightness variable signal VLS supplied from the central processing unit 122. That is, the inverter 134 generates the lamp driving voltage VL corresponding to the brightness variable signal VLS when the brightness variable signal VLS is supplied from the central processing unit 122, and always generates a constant lamp drive. Generate the voltage VL.

The backlight 136 generates light corresponding to the lamp driving voltage VL supplied from the inverter 134 and irradiates the rear surface of the liquid crystal panel 102. To this end, the backlight 136 includes at least one lamp that is lit according to the lamp driving voltage VL to generate light.

As shown in FIG. 6, the image display device according to the first exemplary embodiment generates a mode signal SSR according to the image mode of the source data Data1 and saves power in response to the mode signal SSR. Mode or normal operation.

Accordingly, the image display device according to the first embodiment of the present invention is the power saving mode of the system 120 is switched to the standby mode that consumes the minimum power as shown in FIG. The reduction of power consumption (A) of the devices can reduce the overall power consumption.

8 is a schematic view of an image display device according to a second embodiment of the present invention.

Referring to FIG. 8, the image display device according to the second embodiment of the present invention has the same configuration as the first embodiment of the present invention described above. However, the image display device according to the second embodiment of the present invention is driven in a different manner from the first embodiment of the present invention in the power saving mode.

Specifically, in the power saving mode, the CPU 222 of the system 220 sets the graphic chip 224 and the peripheral device 226 to the power saving mode according to the mode signal SSR in the high state. In this case, the CPU 222 controls the graphic chip 224 such that only the first synchronization signal CS1 is supplied to the timing controller 110 from the graphic chip 224. That is, the source data Data1 supplied from the graphic chip 224 to the timing controller 110 is blocked by the CPU 222.

In the power saving mode, the timing controller 110 controls the data and the gate drivers 104 and 106 using the first synchronization signal CS1 supplied from the graphic chip 224 of the system 220. The DCS and the GCS are generated and the data signal Data2 of the previous frame stored in the memory 112 is supplied to the data driver 104.

On the other hand, the image display device according to the second embodiment of the present invention is driven in the same manner as the first embodiment of the present invention described above in the normal mode.

9 is a schematic view of an image display device according to a third embodiment of the present invention.

Referring to FIG. 9, the image display apparatus according to the third exemplary embodiment of the present invention is the first exemplary embodiment of the present invention except for the timing controller 310 and the mode signal generator 328 of the system 320. Has the same configuration as Accordingly, in the third embodiment of the present invention, descriptions of other components except the timing controller 310 and the mode signal generator 328 of the system 320 will be replaced with the above description.

The timing controller 310 aligns the source data Data1 supplied from the graphic chip 324 of the system 320 and stores the aligned data signal Data1 in the memory 112 in units of frames. Then, the data signal Data1 of the aligned current frame and the data signal Data2 of the previous frame stored in the memory 112 are compared to determine whether the image is a still picture or a moving picture to generate an image determination signal LSR. The timing controller 310 supplies the generated image determination signal LSR to the mode signal generator 328 of the system 320.

The mode signal generator 328 includes a memory 300, a comparator 302, and a determiner 304 as shown in FIG. 10.

The memory 300 stores the source data Data1 from the graphic chip 324 in units of frames, and supplies the stored source data Data1 in units of frames to the comparator 302. Here, the memory 300 may be mounted as the peripheral device 326 of the system 320 or may be a memory means that is one of the peripheral devices 326.

The comparison unit 302 compares the source data Data1 of the current frame Fn supplied from the graphic chip 324 with the source data Data1 of the previous frame Fn-1 supplied from the memory 200. Generate signal CS. That is, the comparator 202 determines that the picture is the still picture when the picture of the current frame Fn and the picture of the previous frame Fn-1 are the same, and generates a comparison signal CS in a high state. In response to the determination, the comparison signal CS in the low state is generated.

The determination unit 304 includes an AND gate 306 and an OR gate 308.

The AND gate 306 performs an AND operation on the image determination signal LSR from the timing controller 310 and the system flag signal SFS from the outside, and outputs the AND result to the AND gate 308. Here, the system flag signal SFS becomes a low state when the user sets the power saving mode or the normal mode using the comparison signal CS generated from the system, and the image determination signal LSR generated by the timing controller 310. If power save mode or normal mode is set by using

The OR gate 308 generates an mode signal SSR by performing an OR operation on the comparison signal CS from the comparator 302 and the output signal AS from the AND gate 306.

Therefore, the determination unit 304 generates the mode signal SSR as shown in Table 1 below and supplies it to the timing controller 310 and the central processing unit 322.

SFS LSR CS SSR MODE Low Low Low Low Normal mode Low Low High High Power saving mode Low High Low Low Normal mode Low High High High Power saving mode High Low Low Low Normal mode High Low High High Power saving mode High High Low High Power saving mode High High High High Power saving mode

As described above, the image display apparatus according to the third exemplary embodiment of the present invention may be configured in the power saving mode described in the first or second exemplary embodiment of the present invention as described above according to the high mode signal SSR generated by the determination unit 304. It operates in the normal mode according to the mode signal SSR in the low state.

11 is a schematic view of an image display device according to a fourth embodiment of the present invention.

Referring to FIG. 11, an image display apparatus according to a fourth exemplary embodiment of the present invention may include a source data Data1, a first synchronization signal CS1, and a mode signal SSR between the system 420 and the timing controller 410. Except for the interfacing, it has the same configuration as the image display device according to the first or third embodiment of the present invention described above.

That is, in the image display apparatus according to the first or third embodiment of the present invention, the mode signal SSR is transmitted to the timing controller through a separate mode signal transmission line.

On the other hand, in the fourth embodiment of the present invention, the mode signal SSR is included in the blank period of the first vertical synchronization signal Vsync1 among the first synchronization signal CS1 and transmitted.

Specifically, the graphics chip 424 of the system 420 is in a high state in the blank period of the first vertical synchronization signal Vsync1 of the first synchronization signal CS1 under the control of the central processing unit 422 as described above. The mode signal SSR is included and transmitted to the timing controller 410. At this time, the CPU 422 switches the graphics chip 424 to the power saving mode immediately after the high mode signal SSR is included in the first vertical synchronization signal Vsync1 and transmitted to the timing controller 410.

Meanwhile, the timing controller 410 may detect the mode signal SSR included in the first vertical synchronization signal Vsync1, as shown in FIG. 12, according to the first embodiment of the present invention. It includes.

The mode signal detector 450 according to the first embodiment of the present invention includes a negative gate 452 and a negative AND gate 454.

The negative gate 452 inverts the first vertical synchronizing signal Vsync1 from the system 420 and supplies it to the negative AND gate 454.

A negative vertical sum gate 454 is supplied with a second vertical synchronizing signal Vsync2 supplied from an internal clock generator mounted inside the timing controller 410 and a first vertical synchronizing signal BVsync1 inverted from the negative gate 452. ) Is supplied.

The negative OR gate 454 is a high state or low state mode by performing an NOR operation on the inverted first vertical sync signal BVsync1 and the second vertical sync signal Vsync2 as shown in FIG. 13. The signal SSR is detected.

As described above, the image display device according to the fourth exemplary embodiment of the present invention may be configured according to the high mode signal SSR detected by the mode signal detector 450 according to the first exemplary embodiment of the present invention. The device operates in the power saving mode described in the image display apparatus according to the first or third embodiment, and operates in the normal mode according to the mode signal SSR in the low state.

FIG. 14 is a view schematically illustrating a mode signal detector according to a second embodiment of the present invention shown in FIG. 13.

Referring to FIG. 14, the mode signal detector 460 according to the second embodiment of the present invention includes a delay unit 462, a negative gate 464, and an AND gate 466. Here, the mode signal detection unit 460 according to the second embodiment of the present invention does not have an internal clock generator built in the timing controller 410, that is, according to the second or third embodiment of the present invention described above. It is applied to an image display apparatus.

On the other hand, the graphic chip 424 of the system 420 is in a high state in the blank period of the first vertical synchronization signal Vsync1 of the first synchronization signal CS1 under the control of the central processing unit 422 as described above. The mode signal SSR is included and transmitted to the timing controller 410. In this case, the CPU 422 switches the graphic chip 424 into a power saving mode such that only the first synchronization signal CS1 is transmitted from the graphic chip 424 to the timing controller 410.

The delay unit 462 delays the first vertical synchronization signal Vsync1 including the mode signal SSR by one clock in response to the clock signal CLK transmitted from the graphic chip 424, and supplies the delayed signal to the negative gate 464. .

The negative gate 464 inverts the first vertical synchronization signal Vsync1 delayed by one clock and supplies it to the AND gate 466.

The AND gate 466 is supplied with the first vertical synchronization signal Vsync1 inverted from the negative gate 464 and the first vertical synchronization signal Vsync1 including the mode signal SSR is supplied from the graphic chip 424. Supplied. Accordingly, the AND gate 466 performs an AND operation on the inverted first vertical synchronizing signal Vsync1 and the first vertical synchronizing signal Vsync1 including the mode signal SSR, thereby raising the high or low mode signal. (SSR) is detected.

As described above, the image display device according to the fourth embodiment of the present invention may be configured according to the high mode signal SSR detected by the mode signal detection unit 460 according to the second embodiment of the present invention. The device operates in the power saving mode described in the image display apparatus according to the second or third embodiment, and operates in the normal mode according to the mode signal SSR in the low state.

FIG. 15 is a view schematically illustrating a mode signal detector according to a third embodiment of the present invention shown in FIG. 13.

Referring to FIG. 15, the mode signal detector 470 according to the third embodiment of the present invention includes a negative gate 472, a delay unit 474, and a negative AND gate 476. Here, the mode signal detection unit 470 according to the third embodiment of the present invention has no internal clock generator built in the timing controller 410, that is, according to the second or third embodiment of the present invention described above. It is applied to an image display apparatus.

On the other hand, the graphic chip 424 of the system 420 is in a high state in the blank period of the first vertical synchronization signal Vsync1 of the first synchronization signal CS1 under the control of the central processing unit 422 as described above. The mode signal SSR is included and transmitted to the timing controller 410. In this case, the CPU 422 switches the graphic chip 424 into a power saving mode such that only the first synchronization signal CS1 is transmitted from the graphic chip 424 to the timing controller 410.

The negative gate 472 inverts the first vertical synchronization signal Vsync1 including the mode signal SSR according to the clock signal CLK transmitted from the graphic chip 424, and supplies the inverted gate 472 to the delay unit 474.

The delay unit 474 delays the inverted first vertical synchronizing signal Vsync1 by one clock in response to the clock signal CLK transmitted from the graphic chip 424 and supplies it to the negative logic gate 476.

The negative vertical sum gate 476 is supplied with the inverted first vertical synchronization signal Vsync1 output from the delay unit 474 and the first vertical synchronization signal Vsync1 including the mode signal SSR from the graphic chip 424. ) Is supplied. Accordingly, the negative OR gate 476 performs an NOR operation on the inverted and delayed first vertical sync signal Vsync1 and the first vertical sync signal Vsync1 including the mode signal SSR, thereby performing a high or low mode. The signal SSR is detected.

As described above, the image display device according to the fourth embodiment of the present invention may be configured according to the mode signal SSR of the high state detected by the mode signal detection unit 470 according to the third embodiment of the present invention. The device operates in the power saving mode described in the image display apparatus according to the second or third embodiment, and operates in the normal mode according to the mode signal SSR in the low state.

16 is a schematic view of an image display device according to a fifth embodiment of the present invention.

Referring to FIG. 16, the image display apparatus according to the fifth exemplary embodiment of the present invention is the first to third embodiments of the present invention except that the brightness variable signal LVS is transmitted and the inverter 534 is controlled. It has the same structure as the image display apparatus which concerns on one Embodiment of an example. Accordingly, in the image display apparatus according to the fifth embodiment of the present invention, only the central processing unit 522, the timing controller 510, and the inverter 534 will be described, and the description of other components will be replaced with the above description. do.

The CPU 522 controls the graphic chip 124, the peripheral device 126, and the mode signal generator 128. The CPU 522 drives the system 120 in the normal mode or the power save mode according to the mode signal SSR from the mode signal generator 128.

In addition, the CPU 522 generates a brightness variable signal LVS corresponding to a user's input signal for adjusting the brightness of the liquid crystal panel 102 and supplies it to the timing controller 510.

The timing controller 510 reduces the power consumption by driving the panel driver 140 in the normal mode or the power save mode according to the mode signal SSR from the system 120.

In addition, the timing controller 510 may adjust brightness information of the data signal Data1 or Data2 supplied from the system 120 or the memory 112 or the brightness variable signal from the central processing unit 522 according to the mode signal SSR. The luminance of the backlight 136 is varied according to LVS.

To this end, the timing controller 510 includes an image analyzer 550 for generating a dimming signal Di by analyzing an image of an input data signal Data1 or Data2 as shown in FIG. 17.

The image analyzer 550 includes a luminance component separator 552, a histogram analyzer 554, and a dimming signal generator 556.

The luminance component separator 552 separates the luminance component Y from the data signal Data1 or Data2 input in units of frames.

The histogram analyzer 554 extracts a histogram by dividing the luminance component Y in units of frames into a plurality of steps. That is, the histogram analyzer 554 accumulates the luminance component Y in each stage to generate histograms for each stage, and supplies the brightness information LCS of the data signal Data1 or Data2 to the dimming signal generator 556. . For example, if the histogram is skewed to the right (higher level), it will be seen as a brighter screen, and if it is skewed to the left (lower level), it will be viewed as a darker screen.

The dimming signal generator 556 generates a dimming signal Dim corresponding to the brightness information LCS from the histogram analyzer 554.

Meanwhile, the timing controller 510 adds the brightness variable signal LVS from the central processing unit 522 to the dimming signal Dim generated by the dimming signal generator 556 and supplies it to the inverter 534. That is, when the brightness variable signal LVS is generated by the user, the timing controller 510 adds the brightness variable signal LVS to the dimming signal Dim generated by the dimming signal generator 556, while not. If not, the dimming signal Dim generated by the dimming signal generator 556 is supplied to the inverter 534.

The inverter 534 generates the lamp driving voltage VL corresponding to the dimming signal Dim supplied from the timing controller 510 and supplies it to the backlight 136. Thus, the brightness of light irradiated from the backlight 136 to the liquid crystal panel 102 is adjusted according to the dimming signal Dim.

As such, the image display device according to the fifth embodiment of the present invention can reduce power consumption A by selectively driving the power saving mode and the normal mode according to the mode signal SSR as shown in FIG. 18. The power consumption B of the backlight 136 may be reduced by adjusting the brightness of the backlight 136 according to the image.

Accordingly, the image display device according to the fifth embodiment of the present invention consumes power due to a reduction in power consumption A according to the mode signal SSR and a reduction in power consumption B of the backlight 136 according to the image. Can be further reduced.

19 is a schematic view of an image display device according to a sixth embodiment of the present invention.

Referring to FIG. 19, the image display apparatus according to the sixth exemplary embodiment of the present invention has the same configuration as the image display apparatus according to the fifth exemplary embodiment of the present invention except for the transmission of the mode signal SSR. That is, in the image display apparatus according to the sixth embodiment of the present invention, the mode signal SSR is the first vertical synchronization of the first synchronization signal CS as in the image display apparatus according to the fourth embodiment of the present invention described above. The mode signal SSR is included in the signal and transmitted to the timing controller 510. Accordingly, the description of the image display device according to the sixth embodiment of the present invention will be replaced with the description of the image display device according to the fourth and fifth embodiments of the present invention described above.

Therefore, the image display device according to the sixth embodiment of the present invention provides the same effects as the image display device according to the fifth embodiment of the present invention described above.

20 is a schematic view of an image display device according to a seventh embodiment of the present invention.

Referring to FIG. 20, the image display apparatus according to the seventh exemplary embodiment has the same configuration as the fifth exemplary embodiment of the present invention except for controlling the inverter 634.

The timing controller 610 receives a dimming signal Dim corresponding to brightness information of the data signal Data1 or Data2 supplied from the system 120 or the memory 112 through the image analyzer 550 illustrated in FIG. 17. It generates and supplies to the central processing unit (622).

The CPU 622 generates a brightness variable signal LVS by adding a user input signal for adjusting the brightness of the liquid crystal panel 102 to the dimming signal Dim supplied from the timing controller 610. Supplied brightness variable signal LVS to inverter 634.

The inverter 634 generates a lamp driving voltage VL corresponding to the brightness variable signal LVS supplied from the central processing unit 622 and supplies it to the backlight 136. Thus, the brightness of light irradiated from the backlight 136 to the liquid crystal panel 102 is adjusted according to the brightness variable signal LVS.

Therefore, the image display device according to the seventh embodiment of the present invention provides the same effects as the image display device according to the fifth embodiment of the present invention described above.

21 is a schematic view of an image display apparatus according to an eighth embodiment of the present invention.

Referring to FIG. 21, the image display apparatus according to the eighth exemplary embodiment has the same configuration as the image display apparatus according to the seventh exemplary embodiment of the present invention except for the transmission of the mode signal SSR. That is, the mode signal SSR in the image display apparatus according to the eighth embodiment of the present invention is the first vertical synchronization of the first synchronization signal CS as in the image display apparatus according to the fourth embodiment of the present invention described above. The signal is included in the signal and transmitted to the timing controller 610. Accordingly, the description of the image display device according to the eighth embodiment of the present invention will be replaced with the description of the image display device according to the fourth and seventh embodiments of the present invention described above.

Therefore, the image display device according to the eighth embodiment of the present invention provides the same effects as the image display device according to the fifth embodiment of the present invention described above.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Will be apparent to those of ordinary skill in the art.

The image display apparatus according to the embodiment of the present invention can reduce the overall power consumption due to the power saving mode by switching to the normal mode or the power saving mode according to the mode signal corresponding to the still or moving image of the input data. By modulating the data into modulated data in the mode, the response speed of the liquid crystal cell may be increased to reduce the operation flow phenomenon in the implementation of moving images. The present invention can further reduce power consumption by adjusting the brightness of the backlight according to the brightness of the image input in the normal mode and the power saving mode. Therefore, the present invention can increase the use time of the portable computer.

Claims (46)

A liquid crystal panel in which a liquid crystal cell is formed in an area defined by a plurality of data lines and a plurality of gate lines; A system for generating a first synchronization signal and data and generating a mode signal in accordance with the image mode of the data; A panel driver for displaying an image on the liquid crystal panel; A timing controller for driving the panel driver to a normal mode or a power saving mode according to the mode signal; A backlight for irradiating light to the liquid crystal panel; The system A graphics chip which generates the first synchronization signal and the data; A mode signal generator for generating the mode signal in accordance with the image mode of the data; A central processing unit for controlling the system in the power saving mode or the normal mode according to the mode signal; And the central processing unit stops driving the graphic chip in the power saving mode, or controls the graphic chip so that only the first synchronization signal is supplied from the graphic chip to the timing controller. The method of claim 1, The central processing unit And a brightness variable signal corresponding to an input signal of a user for adjusting the brightness of the liquid crystal panel. The method of claim 2, The panel driver, A data driver for supplying a video signal to the data line under control of the timing controller; A gate driver for supplying a scan signal to the gate line under control of the timing controller; And an inverter for driving the backlight according to the brightness variable signal. The method of claim 3, wherein A first memory for storing the data supplied from the timing controller; And a lookup table including modulation data for increasing a response speed of the liquid crystal cell. 5. The method of claim 4, The mode signal generator, A second memory for storing the data supplied from the graphics chip; And a comparator for comparing the data of the previous frame from the second memory with the data of the current frame from the graphics chip to generate the mode signal. 6. The method of claim 5, The comparison unit compares data of the previous and current frames to generate a mode signal of a first logic state corresponding to the power saving mode when the data is identical, and compares the data of the previous and current frames to the normal mode if different. And generating a mode signal in a second logic state corresponding to. 5. The method of claim 4, And the timing controller compares data of a current frame from the graphic chip with data of a previous frame stored in the first memory to generate an image determination signal and supply the image determination signal to the system. The method of claim 7, wherein The mode signal generator, A second memory for storing the data supplied from the graphics chip; A comparator configured to compare data of a previous frame from the second memory with data of a current frame from the graphic chip to generate a comparison signal; And a judging section for generating the mode signal by using a system flag signal from the outside, the comparison signal, and the image judging signal. 9. The method of claim 8, The determination unit, An AND gate for performing an AND operation on the image determination signal and the system flag signal; And a logic sum gate configured to perform an OR operation on the comparison signal and the output signal from the AND gate to generate a mode signal of a first logic state corresponding to the power saving mode or a mode signal of a second logic state corresponding to the normal mode. And an image display device. 5. The method of claim 4, And the central processing unit controls the graphic chip to include the mode signal in a blank section of the first vertical synchronizing signal of the first synchronizing signal and transmit the same to the timing controller. 11. The method of claim 10, The timing controller includes a mode signal detector for detecting a mode signal of a first logic state corresponding to the power saving mode or a mode signal of a second logic state corresponding to the normal mode from the first vertical synchronization signal. An image display device. The method of claim 11, The mode signal detector, A negative gate for inverting the first vertical synchronizing signal including the mode signal; And a negative OR gate for detecting the mode signal by performing a negative OR operation on a second vertical sync signal identical to the first vertical sync signal and an output signal of the negative gate. The method of claim 11, The mode signal detector, A delay unit configured to delay a first vertical synchronization signal including the mode signal in a clock signal among the first synchronization signals; A negative gate for inverting the delayed first vertical synchronization signal output from the delay unit; And an AND gate for detecting the mode signal by performing an AND operation on the first vertical synchronization signal and the output signal of the negative gate. The method of claim 11, The mode signal detector, A negative gate for inverting the first vertical synchronizing signal including the mode signal; A delay unit for delaying an output signal of the negative gate according to a clock signal of the first synchronization signal; And a non-OR gate that detects the mode signal by performing an NOR operation on the delayed first vertical synchronizing signal and the first vertical synchronizing signal outputted from the delay unit. The method according to claim 13 or 14, And the central processing unit stops driving the graphic chip immediately after the mode signal is included in the first vertical synchronization signal. The method according to claim 6 or 9, The central processing unit switches the system to a power saving mode in response to a mode signal in the first logic state, and switches the system to a normal mode in response to a mode signal in the second logic state. Device. 17. The method of claim 16, The timing controller compares the data of the current frame supplied from the graphic chip with the data of a previous frame stored in the first memory according to the mode signal of the second logic state, and compares the modulation data listed in the lookup table. An image display apparatus, which is supplied to a data driver. delete The method of claim 1, And the timing controller includes a clock generator for generating a second synchronization signal identical to the first synchronization signal according to a mode signal in a first logic state. 20. The method of claim 19, And the timing controller supplies data of a previous frame stored in a first memory to a data driver according to the mode signal of the first logic state by using the second synchronization signal. delete The method of claim 1, And the timing controller supplies data of a previous frame stored in a first memory to a data driver according to a mode signal of a first logic state by using the first synchronization signal. The method of claim 2, And the timing controller includes an image analyzer configured to generate a dimming signal according to brightness information corresponding to brightness of data supplied from the graphic chip or the first memory. 24. The method of claim 23, The image analysis unit, A luminance component separator for separating the luminance component from the data; A histogram analyzer for extracting a histogram using the luminance component and analyzing the brightness of the data to generate the brightness information; And a dimming signal generator configured to generate a dimming signal according to the brightness information. 24. The method of claim 23, The panel driver, A data driver for supplying a video signal to the data line under control of the timing controller; A gate driver for supplying a scan signal to the gate line under control of the timing controller; And an inverter for driving the backlight according to at least one of the brightness variable signal and the dimming signal. 25. The method of claim 24, Wherein either one of the timing controller and the system adds the brightness variable signal to the dimming signal and supplies it to the inverter. delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete The method of claim 2, And the graphic chip and the mode signal generator are configured as one graphic module.

Images