KR101267322B1 - Ldpc decoder and decoding method thereof - Google Patents

Abstract

PURPOSE: An LDPC decoding and a decoding method thereof are provided to improve a decoding speed by reducing the number of access to an off-chip memory in case of LDPC decoding. CONSTITUTION: A processor decodes a code word by passing a first message and a second message. An on-chip memory stores address conversion data. In case of passing the first message, a combined memory read and a combined memory write are used. In case of passing the second message, a first address system conversion and a second address system conversion are performed before random memory read and before random memory write. The first message and the second message have the same address system.

Description

LDPC decoder and its decoding method {LDPC Decoder and Decoding Method approximately}

The present invention relates to an LDPC decoder and a decoding method thereof. In particular, the present invention relates to a hardware-based LDPC decoder and a decoding method thereof, including for example, a GPU.

Low Density Parity Check (LDPC) codes have been adopted as the standard for various communication systems, including IEEE 802.2an, IEEE 802.11n, WiMax, and DVB-S2, based on their robust error correction capabilities. However, due to the lack of a mathematical tool that can accurately calculate the error correction capability of LDPC codes, analysis through simulation is required.

The decoding algorithm of the LDPC code is based on the message passing algorithm. The message passing algorithm is divided into two processes, and bit-to-check message passing is performed first. In bit-check message passing, bit nodes bound to the same check node exchange messages with each other to inform information of other bit nodes in the same group. Check-bit message passing is performed after the bit-check message passing process. In check-bit message passing, check nodes bound to the same bit node send and receive messages. Bit-check message passing and check-bit message passing may be repeated until decoding is performed with a valid codeword or until a maximum number of iterations is reached. Due to the nature of this iterative decoding process, the implementation of the LDPC code has a high complexity.

In particular, since the address system of the bit-check message and the check-bit message is different from each other due to the characteristics of the LDPC code structure, an address conversion process is required during LDPC decoding. This not only causes high complexity in operating the decoder, but also takes a long time for decoding.

Accordingly, there is a need for an LDPC decoding technique having low complexity and improved speed and performance.

Korean Laid-Open Publication No. 10-2006-0064491 (2006.06.13.)

The present invention has been made to solve the problems of the prior art, and an object thereof is to provide an LDPC decoder and decoding method with low complexity and improved decoding speed and performance.

The technical objects to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical subjects which are not mentioned can be clearly understood by those skilled in the art from the description of the present invention .

An LDPC decoder according to an embodiment of the present invention includes a processor for decoding a codeword by performing a first message passing and a second message passing; And an on-chip memory capable of storing address translation data, wherein a merged memory read and a merged memory write are used at the time of the first message passing, and a random memory read and a random memory write at the time of the second message passing. Each of the first address system conversion and the second address system conversion is performed, and the first message and the second message may be preset to have the same address system.

The first message may be a bit-check message and the second message may be a check-bit message.

The first message and the second message may be loaded into the cache memory.

In an embodiment of the present invention, an LDPC decoding method includes performing first message passing using a merged memory read and a merged memory write; And decoding the codeword, including performing a second message passing, wherein the first message and the second message may be preset to have the same address system.

The performing of the second message passing may include: reading a random memory by converting an address system of the first message into an address system of a second message; And converting the address system of the second message into the address system of the first message and writing a random memory.

According to the present invention, since the number of accesses to the off-chip memory can be reduced by using the on-chip memory during LDPC decoding, the decoding speed can be improved. In addition, according to the present invention, by unifying a message address system into one, two address system conversions are required only when passing a check-bit message. At this time, only one address translation data is stored and used in the on-chip memory, thereby accessing the off-chip memory. You can reduce the number of times. In addition, according to the present invention, since the check-bit message and the bit-check message are cached and used in the on-chip cache memory, the LDPC decoding speed can be improved. In addition, the decoding speed can be improved by using the merged memory connection twice when passing the bit-check message according to the present invention.

1A and 1B illustrate conventional bit-check message passing and check-bit message passing methods.
2A and 2B illustrate a bit-check message passing and check-bit message passing algorithm according to an embodiment of the present invention.
3 illustrates a codeword processing technique using an external chip memory in address translation.
4 illustrates a codeword processing technique using an internal chip memory in address translation according to an embodiment of the present invention.
5 is a table comparing speeds of a CPU-based LDPC decoding method and a GPU-based LDPC decoding method according to an embodiment of the present invention.
6 is a graph comparing the speed of the CPU-based LDPC decoding method and the GPU-based LDPC decoding method according to an embodiment of the present invention according to SNR.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a detailed description of preferred embodiments of the present invention will be given with reference to the accompanying drawings. However, the embodiments of the present invention may be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. The shape and the size of the elements in the drawings may be exaggerated for clarity of explanation and the same reference numerals are used for the same elements and the same elements are denoted by the same quote symbols as possible even if they are displayed on different drawings Should be. In the following description, well-known functions or constructions are not described in detail to avoid unnecessarily obscuring the subject matter of the present invention.

In general, a GPU (Graphics Processing Unit) -based simulator is not only easy to implement but also uses parallel arithmetic, which is very fast. An embodiment of the present invention proposes an LDPC decoder and a decoding method using a GPU. However, this is only an embodiment and the present invention can be applied to other hardware.

In general, GPU-based LDPC decoding requires access to off-chip memory. In addition, the merged memory access can greatly improve the operation speed by enabling access to multiple memories in one operation. The use of on-chip memory has the advantage of being faster than the use of off-chip memory. However, the chip internal memory has a capacity limitation in processing large data.

In view of the above, an embodiment of the present invention is to propose a technique for minimizing access to an external chip memory and improving LDPC decoding speed and performance by using an internal chip memory. In addition, embodiments of the present invention seek to improve LDPC decoding speed and performance by using merged memory connections.

In addition, an embodiment of the present invention seeks to improve LDPC decoding speed and performance by using a cache memory inside a chip.

A general LDPC decoding technique includes repeatedly performing bit-check message passing and check-bit message passing as shown in FIGS. 1A and 1B.

At this time, the bit-check message and the check-bit message have different address systems. Because of this characteristic, it is necessary to convert the address system between two messages during message operation. At this time, the information about the address (or order) of the two messages is based on the parity check matrix of the LDPC code.

Conventional bit-check message passing is described with reference to FIG. 1A. One arrow in FIGS. 1A and 1B represents the operation of an independent thread. As shown in Fig. 1A, the check-bit message is first read through a merged memory read. In this case, in order to write the message in memory after calculating the bit-check message, an operation of converting the address system of the message into the address system of the check-bit message is required.

In this case, the first address system translation data is used, and the first address system translation data is stored in off-chip memory, for example, a global memory of the GPU. Thus, this address system translation requires access to off-chip memory.

In the step of writing the message, the merged memory write may not be used, and the random message is written in a random order.

Conventional check-bit message passing is described with reference to FIG. 1B. As shown in Fig. 1B, the bit-check message is first read through a merged memory read. In this case, through the address translation of FIG. 1A, the address system of the bit-check message has the address system of the check-bit message, and thus the merged memory may be read. In order to write the message in memory after calculating the check-bit message, an operation of converting the address system of the message into the address system of the bit-check message is required.

In this case, the second address system translation data is used, and the second address system translation data is stored in off-chip memory such as global memory of the GPU. Thus, this address system translation requires access to off-chip memory.

Since the second address system translation data is different from the first address system translation data, it is necessary to store and access two address system translation data separately in the conventional LDPC decoding technique.

In the step of writing the message, the merged memory write may not be used, and the random message is written in a random order.

That is, the conventional bit-check message and check-bit message have different address systems, so that the merged memory accesses are possible for read operations and merged for write operations when bit-check message passing and check-bit message passing. The memory connection cannot be used. This is because address translation takes place before each message is written at each message passing step. Furthermore, one address system translation is required for each bit-check message passing and check-bit message passing. In this case, the first address system translation data and the second address system translation data for address system translation are different from each other and stored in the off-chip memory. Therefore, access to off-chip memory is essential for address translation.

Bit-check message passing and check-bit message passing techniques according to embodiments of the present invention are described with reference to FIGS. 2A and 2B. Hereinafter, the present invention will be described with an example of matching the address systems of the bit-check message and the check-bit message with the address system of the bit-check message, but this is only an example, and addresses of the bit-check message and the check-bit message are described below. It is also possible to match the scheme to the address scheme of check-bit messages.

2A illustrates a bit-check message passing algorithm according to an embodiment of the present invention. First, the check-bit message is read through the merged memory connection. At this time, since the check-bit message and the bit-check message are both stored with the address system of the bit-check message, the merged memory can be read. After the bit-check message operation is performed, the message can be written through the merged memory connection without any translation of the addressing scheme.

That is, the check-bit message is read through the merged memory connection, the bit-check message is computed, and the message is written over the merged memory connection to the location where the bit-check message will be placed. These steps are represented by the first to third arrays of Figure 2A, respectively. In this case, computing refers to computing a bit-check message. For example, as a process of reading and adding all check-bit messages coming in one bit, an operation as shown in FIG. 2A may be repeatedly performed by the number of checks belonging to one bit to accumulate the values.

Thus, according to an embodiment of the present invention, address system translation is not required when bit-check message passing, and merged memory read and write may be used.

2B illustrates a check-bit message passing algorithm according to an embodiment of the present invention. At this time, since all the messages are stored according to the address scheme of the bit-check message, an address scheme conversion process is required for both read and write operations.

First, a first address system conversion process of converting an address system into a check system of a check-bit message is performed on the bit-check message. Address system translation data is used during the first address system translation process. Such address system translation data may be stored in off-chip memory, such as global memory of the GPU. The address system translation data stored in the off-chip memory is transferred to the on-chip memory for the first address system translation. The on-chip memory may be, for example, shared memory or local memory of the GPU.

A read operation is performed through a random memory access to the corresponding message on which the first address system conversion process is performed. After the operation on the check-bit message is performed, a second address system conversion process of converting the address system of the check-bit message into the address system of the bit-check message is performed again for the message. During the second address system conversion process, the same address translation data used in the first address system conversion process may be used. In this case, since the address translation data is stored in the on-chip memory during the first address system conversion process, the off-chip memory does not need to be accessed in the second address system conversion process. Only by accessing the on-chip memory can the address translation data be used.

Subsequently, the corresponding message on which the second address system conversion is performed may be written to the memory using a random memory access. Thus, bit-check message passing may then be performed by reading the check-bit message through the merged memory connection.

As described above, in the LDPC decoding scheme according to the embodiment of the present invention, the performance and speed of LDPC decoding may be improved by using merged memory reads and writes when bit-check message passing. In the case of check-bit message passing, off-chip memory is accessed to obtain address translation data during the initial address system translation. However, in the second address system translation, the address translation data is already stored in the on-chip memory. There is no need to access the memory again. Therefore, since the number of times of accessing the off-chip memory as a whole can be reduced by half compared to the conventional technique, the LDPC decoding speed can be improved.

In an embodiment of the present invention, one address translation data may be used to perform two address system translations. In this case, the address translation data is transferred from the off-chip memory to the on-chip memory in the first address system conversion process. For example, the on-chip memory can be shared memory or local memory of the GPU.

However, shared memory is an on-chip memory, and its size is very small, which limits its use. Therefore, address system translation data should be divided and stored in shared memory. As a result, the codeword processing method is different from the case of using off-chip memory.

3 illustrates a codeword processing technique using an external chip memory in address translation. As shown in Fig. 3, when the address translation data is stored in the chip external memory, the address translation data does not need to be divided because its capacity is large. Therefore, one codeword may be processed for each block of the GPU. That is, one codeword may be decoded for each block. The first codeword may be processed in the first block block1, the second codeword may be processed in the second block block2, and the third codeword may be processed in the third block block3. Here, each block of threads is provided with shared memory. Thus, threads running in the same block can share shared memory.

4 illustrates a codeword processing technique using an internal chip memory in address translation according to an embodiment of the present invention. At this time, since the shared memory has a very small capacity, address translation data should be divided and stored. Thus, one codeword cannot be processed in each GPU block. According to an embodiment of the present invention, a plurality of pieces of codewords may be processed simultaneously in each GPU block. Here, the pieces of the plurality of codewords are parts that can be decoded using the divided address translation data.

That is, in the first block block1, part of the first codeword, part of the second codeword, and part of the third codeword are simultaneously processed. Then, in the second block, another part of the first codeword, another part of the second codeword, and another part of the third codeword may be processed simultaneously. Subsequently, in the third block, the remaining part of the first codeword, the remaining part of the second codeword, and the remaining part of the third codeword may be processed simultaneously. This is shown in FIG.

By implementing in this way, the number of codewords processed in the entire block of GPU while using the small shared memory is not reduced. Therefore, the effect of increasing the driving speed can be obtained. According to the exemplary embodiment of the present invention, when using the shared memory existing inside the chip of the GPU, a decoding speed improvement effect of about 14% may be obtained as compared with the case where it is not.

In addition, according to an embodiment of the present invention, the bit-check message and / or check-bit message may be loaded into the on-chip cache memory. That is, in the LDPC decoding technique, the process of bit-check message passing, check-bit message passing, and calculating all information for each bit is performed repeatedly, so it is necessary to access the off-chip memory repeatedly to obtain necessary information. have. Accordingly, an embodiment of the present invention proposes a technique for loading and using data that can be repeatedly used in a cache memory implemented on chip.

For example, a bit-check message, a check-bit message, a parity check matrix for an LDPC code, etc. repeatedly used in the LDPC decoding scheme according to an embodiment of the present invention may be loaded and used in a cache memory. For example, the cache memory may be a texture cache of the GPU. In addition, the data loaded into the cache memory may include other data as necessary.

As such, by repeatedly loading the data to be used in the cache memory, the speed and performance of the LDPC decryption according to the embodiment of the present invention can be improved. For example, by using the texture cache inside the chip of the GPU, an improvement in decoding speed of about 7% or more can be achieved compared to otherwise.

The LDPC decoding described above may be performed in, for example, a processor of a GPU. In this case, the processor of the GPU may be a manycore microprocessor. In addition, the LDPC decoding algorithm according to the embodiment of the present invention may be programmed and implemented in software.

Hereinafter, the performance of the LDPC decoding algorithm according to the embodiment of the present invention is compared with the conventional decoding technique. The LDPC decoding technique according to the embodiment of the present invention is a GPU-based LDPC decoding technique, and the conventional decoding technique to be compared is a CPU-based LDPC decoding technique. The LDPC code used here is an IEEE 802.3an standard LDPC code, which is a (6,32) -regular code having a length of 2048 and a code rate of 0.84. As a result of fixing and fixing the maximum number of iterations of bit-check message passing and check-bit message passing to 10, the speed of the LDPC decoding scheme according to the embodiment of the present invention is improved by about 35% compared to the conventional GPU-based LDPC decoding scheme. Indicated.

5 is a table showing decoding times of a CPU-based LDPC decoding method and a GPU-based LDPC decoding method according to an embodiment of the present invention according to the maximum number of repetitions. Each decoding time is a time taken to decode one codeword. When the maximum number of iterations is 20, it can be seen that the GPU-based LDPC decoder according to the embodiment of the present invention has a 250 times faster speed than the conventional CPU-based LDPC decoder.

6 is a graph comparing the speed of the CPU-based LDPC decoding method and the GPU-based LDPC decoding method according to an embodiment of the present invention according to SNR. The maximum number of repetitions was 50 times. In FIG. 6, when the noise is 13 dB, it can be seen that the LDPC decoder according to the embodiment of the present invention exhibits about 330 times faster speed than the conventional CPU-based LDPC decoder.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. will be. Therefore, it should be understood that the above-described embodiments are to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than the foregoing description, It is intended that all changes and modifications derived from the equivalent concept be included within the scope of the present invention.

Claims (16)

A processor for decoding a codeword by performing a first message passing and a second message passing; And
Includes on-chip memory to store address translation data,
Merged memory reads and merged memory writes are used in passing the first message,
When the second message is passed, a first address system conversion and a second address system conversion are performed before a random memory read and a random memory write, respectively.
The first message and the second message, characterized in that predetermined to have the same address system,
LDPC Decoder. The method of claim 1,
And the first message is a bit-check message and the second message is a check-bit message. The method of claim 1,
The LDPC decoder is a GPU-based LDPC decoder, LDPC decoder, characterized in that. 4. The method according to any one of claims 1 to 3,
The first address system conversion converts the address system of the first message into the address system of the second message using the address translation data.
And the second address system translation converts the address system of the second message into the address system of the first message using the address translation data. 4. The method according to any one of claims 1 to 3,
And the first message and the second message are loaded into a cache memory. 4. The method according to any one of claims 1 to 3,
The on-chip memory is a shared memory,
The address translation data is divided into a predetermined number and stored in the shared memory.
And the processor processes the plurality of codewords partially at the same time for each block. delete Performing first message passing using the merged memory read and the merged memory write; And
Decoding the codeword, including performing a second message passing,
And the first message and the second message have a same address system. 9. The method of claim 8,
Performing the second message passing includes:
Converting the address system of the first message into the address system of the second message and reading a random memory; And
And converting the address system of the second message into the address system of the first message and writing a random memory. 10. The method of claim 9,
And the first message is a bit-check message and the second message is a check-bit message. 10. The method of claim 9,
The LDPC decoding method is a GPU-based LDPC decoding method. 12. The method according to any one of claims 9 to 11,
Converting the address system of the first message to the address system of the second message is performed using address translation data, and the address translation data converts the address system of the first message to the address system of the second message. LDPC decoding method characterized in that stored in the on-chip memory before the step. The method of claim 12,
And converting the address system of the second message into the address system of the first message using the address translation data stored in the on-chip memory. The method according to any one of claims 8 to 11,
And the first message and the second message are loaded into a cache memory. The method of claim 12,
The on-chip memory is a shared memory,
The address translation data is divided into a predetermined number and stored in the shared memory.
LDPC decoding method, characterized in that a plurality of codework is processed at the same time for each block. delete

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