KR101265116B1 - Integrated circuit with self-test feature for validating functionality of external interfaces - Google Patents

Abstract

This disclosure describes an integrated circuit with self-test features for validating functionality of external interfaces. Example external interfaces include memory interfaces and bus interfaces, such as a peripheral component interconnect (PCI) bus, an advanced high-performance bus (AHB), an advanced extensible interface (AXI) bus, and other external interfaces that operate a high frequency, e.g., 200 MHz or greater. Test logic may be embedded on the integrated circuit and configured to validate functionality of external interfaces while receiving power and non-test signals from external test equipment. Thus, external test equipment may not supply high frequency test signals to the integrated circuit. The external test equipment may, however, independently validate functionality of a pin interface of the integrated circuit. As a result, the integrated circuit may reduce cost and time required to verify functionality and timing of the external interfaces.

Description

INTEGRATED CIRCUIT WITH SELF-TEST FEATURE FOR VALIDATING FUNCTIONALITY OF EXTERNAL INTERFACES}

This application claims the benefit of US Provisional Application No. 60 / 943,935, filed June 14, 2007, the entire contents of which are incorporated by reference.

The present disclosure relates to integrated circuits, and more particularly to techniques for verifying the functionality and timing of external interfaces for integrated circuits.

Integrated circuit (IC) devices may include many miniaturized circuits implemented in a semiconductor substrate. IC devices are tested after manufacture to ensure proper operation before they are sold and used commercially. Thorough testing of IC devices is typically performed using complex and expensive external test equipment. To test the IC device, the IC device is mounted on test equipment. In particular, the IC device is connected to the test equipment through a pad ring that interconnects the core logic to the input / output (I / O) pins. To test the IC device, the test equipment passes test data defining the test to the IC device through the I / O pins and obtains response signals from the IC device according to the test defined by the test program.

Testing the IC device requires verifying the functionality and timing of the internal and external interfaces of the IC device. Examples of external interfaces include memory interfaces and peripheral component interconnect (PCI) buses, advanced high-performance buses (AHBs), enhanced extensible interface (AXI) interface buses. , Small computer system interface (SCSI) bus, Ethernet bus, Universal Serial Bus (USB), Advanced Graphics Processor (AGP) bus, Serial Serial Advanced Technology Attachment (ATA) Bus interfaces such as a bus and other external interfaces operating at high frequencies are included. Verifying the functionality and timing of the external interfaces includes using the host computer to generate trace files for the external interface under test by developing a test program and running a simulation. When trace files, also called test vectors, vectors, or test data, are prepared, the test data is loaded onto test equipment. The test equipment provides test signals to the IC device in accordance with the test data and obtains response signals from the IC device through the I / O pins.

During the test, the operation of the IC device is tested in both transmit and receive modes. In either the transmit mode or the receive mode, the test equipment provides signal transitions in accordance with the test data and the IC device generates corresponding response signals. The test rig then verifies the responses according to the test data. Once the tests are completed, the test equipment, or more specifically, the host computer interprets the response signals. The host computer interprets the results by comparing the response signals generated by the IC device in the transmit and receive modes with the simulated results. The host computer generates a report indicating whether the IC device passed the test based on the comparison.

In addition, for each test vector, the IC device can be tested for various operating conditions, such as temperature, voltage changes, and process corners. It may also be required for the test equipment to generate a signal at or above the maximum operating frequency of the external interface. As the complexity and clock frequency of IC devices increase, the frequency at which test equipment channels operate also needs to be increased to reliably test the IC device. For example, because the clock frequency of high speed memory devices increases almost every year, test equipment must be upgraded, modified, and even replaced to test these devices at high operating frequencies. In other words, IC devices cannot be tested at the maximum clock frequency of IC devices using old test equipment that was manufactured for test devices operating at low frequencies. Thus, with each improvement in clock frequency, test equipment must be upgraded or purchased and new test programs must be developed, thereby increasing the cost of new IC devices.

This disclosure describes an integrated circuit with self-test features for verifying the functionality of high frequency external interfaces. Exemplary external interfaces include memory interfaces and peripheral component interconnect (PCI), an advanced high-performance bus (AHB), an enhanced extensible interface (AXI) bus, and examples Bus interfaces such as, for example, other external interfaces operating at high frequencies above 200 MHz are included. The test logic may be embedded on the integrated circuit and may be configured to verify the functionality of the external interfaces. For example, the test logic may be configured to verify external interface functionality while receiving power and non-test signals from external test equipment. Thus, external test equipment may not provide high frequency test signals to the integrated circuit.

Verifying the functionality of an external interface generally means verifying transactions sent over the external interfaces based on data associated with the transactions or whether the transactions match a corresponding protocol. External test equipment is used to independently verify the functionality of the pin interface of the integrated circuit, as well as supply power and key signals to the integrated circuit. In this way, the on-chip, self-test features of the integrated circuit substantially eliminate the need for the test equipment to provide high frequency test signals, resulting in the cost and time required to verify the timing and functionality of the external interfaces. Can be reduced.

In one aspect, an integrated circuit includes a processor that executes instructions of a test program to initiate operation in one of a transmit mode and a receive mode, and generate transactions to communicate with the processor with one or more external devices in accordance with the test program. A core logic circuit, the processor generating transactions for communicating with the core logic in accordance with the test program, and verifying one or more of the transactions and indicating a status signal indicating whether the one or more transactions are valid. Contains test logic to output.

In another aspect, a method includes executing instructions of a test program in a processor on an integrated circuit to initiate operation in one of a transmit mode and a receive mode, at the processor to communicate with core logic on the integrated circuit in accordance with the test program. Generating transactions, generating transactions in the core logic to communicate with one or more external devices and the processor in accordance with the test program, and verifying one or more of the transactions through test logic on the integrated circuit. And generating a status signal in the test logic indicating whether the one or more transactions are valid.

In another aspect, an integrated circuit includes means for executing instructions of a test program on an integrated circuit to initiate operation in one of a transmit mode and a receive mode, at the processor to communicate with core logic on the integrated circuit in accordance with the test program. Means for generating transactions, means for generating transactions in the core logic to communicate with one or more external devices in accordance with the test program, and verifying one or more of the transactions through test logic on the integrated circuit. Means for generating, and means for generating a status signal indicating whether the one or more transactions are valid.

In another aspect, a computer program product includes a computer readable medium, the computer readable medium having instructions stored on the computer readable medium. The instructions are code for executing instructions of a test program on an integrated circuit to initiate operation in one of a transmit mode and a receive mode, generating transactions in the processor to communicate with core logic on the integrated circuit in accordance with the test program. Code for generating code in the core logic to communicate with one or more external devices and the processor in accordance with the test program, code for verifying one or more of the transactions through test logic on the integrated circuit, And code for generating a status signal indicating whether the one or more transactions are valid.

In another aspect, a system includes an integrated circuit and test equipment for supplying power and clock signals to the integrated circuit. The integrated circuit includes a processor that executes instructions of a test program to initiate operation in one of a transmit mode and a receive mode, core logic that generates transactions to communicate with the processor with one or more external devices in accordance with the test program. Circuitry, wherein the processor generates transactions for communicating with the core logic in accordance with the test program, and a test that verifies one or more of the transactions and outputs a status signal indicating whether the one or more transactions are valid Contains logic.

The techniques described in this disclosure may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the software may be executed in one or more processors, such as a microprocessor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), or digital signal processor (DSP). Software implementing the techniques may be initially stored on a computer readable medium and loaded and executed on a processor. Thus, the present disclosure also contemplates computer readable media comprising instructions that, when executed, cause a device to perform techniques as described in this disclosure. In some cases, the computer readable medium may form part of a computer program product including the computer readable medium.

One or more aspects of the disclosure are set forth in the following description and the annexed drawings. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.

1 is a block diagram illustrating an integrated circuit with self test features and external test equipment for testing the integrated circuit.
FIG. 2 is a block diagram illustrating the integrated circuit of FIG. 1 in more detail.
3 is a block diagram illustrating exemplary components of the integrated circuit of FIG. 2 in more detail.
4 and 5 are flow diagrams illustrating exemplary self test techniques that may be performed by the integrated circuit of FIG.

Integrated circuits are tested after manufacture to ensure proper operation prior to sales and commercial use. Testing the integrated circuit can include verifying the functionality of the external interfaces used to communicate with the external devices. In general, a host computer is used to run a simulation to develop a test program and generate trace files for external interfaces. When trace files, also referred to as test vectors, vectors, or test data in the present disclosure, are generated, the trace files are loaded onto test equipment that supplies signals to the integrated circuit in accordance with the test data.

Testing an integrated circuit in this manner can be time consuming because it requires multiple test vectors to cover the complex functionality of the external interfaces of the integrated circuit. In addition, test equipment can be expensive because the test equipment must support high frequency integrated circuit operation to verify the timing of the external interface. Because the complexity and clock frequency of integrated circuits increases frequently, the performance of external test equipment can be a limiting factor in testing new integrated circuits. That is, old test equipment that was manufactured to test integrated circuits operating at low frequencies cannot be used to test new integrated circuits at their high operating frequencies. Acquiring new external test equipment that can test integrated circuits at higher frequencies can be expensive and require additional time.

The present disclosure describes an integrated circuit with self test features for verifying the functionality of high frequency external interfaces. Examples of external interfaces include memory interfaces and peripheral component interconnect (PCI) buses, enhanced high-performance buses (AHBs), enhanced extensible interface (AXI) interface buses, Small computer system interface (SCSI) bus, Ethernet bus, Universal Serial Bus (USB), Advanced Graphics Processor (AGP) bus, Serial Serial Technology Attachment (ATA) bus And bus interfaces such as, and other external interfaces operating at high frequencies, for example 200 MHz or more. According to various aspects of the present disclosure, test logic may be embedded on an integrated circuit and configured to verify the functionality of external interfaces. In some aspects, the test logic may be configured to test external interface functionality while receiving power and non test signals from external test equipment. Thus, external test equipment may not provide high frequency test signals to the integrated circuit.

Verifying the functionality of the external interface means verifying transactions sent over the external interfaces based on data associated with the transactions or based on whether the transactions match a corresponding protocol. External test equipment is used to supply power and non-test signals, i.e., signals critical to the operation of the integrated circuit, to the integrated circuit and to independently verify the functionality of the integrated circuit's pin interface. In this way, the on-chip, self-test features of the integrated circuit substantially eliminate the need for the test equipment to provide high frequency test signals, resulting in the cost and time required to verify the timing and functionality of the external interfaces. Can be reduced.

1 is a block diagram illustrating a system 10 for verifying the functionality of high frequency external interfaces of an integrated circuit 12. As shown in FIG. 1, system 10 includes integrated circuit 12 and test equipment 22. In general, integrated circuit 12 has self-test features that substantially eliminate the need for test equipment 22 to provide high frequency test signals to verify the functionality of the high frequency external interfaces. As a result, the test rig 22 may be a relatively inexpensive test rig that provides power and non-test signals, i.e., critical signals for operation, to the integrated circuit 12 during the test process.

Integrated circuit 12 may include one or more miniaturized circuits implemented on a substrate on a peninsula, such as a silicon chip. In general, integrated circuit 12 may be an application specific integrated circuit (ASIC) or a general purpose integrated circuit that communicates with external devices (not shown) via one or more interfaces. For example, integrated circuit 12 may be configured for use in a personal computer, laptop computer, personal digital assistant (PDA), ultra mobile personal computer (UMPC), mobile phone handset, networking device, or other electronic device. . Integrated circuit 12 includes one or more external devices and external devices, such as system memory, disk drives, keyboards, monitors or displays, mice, printers, scanners, external storage devices, and other external input / output (I / O) devices. It may be configured to communicate via interfaces. Thus, it should be understood that integrated circuit 12 is any integrated circuit configured to communicate with at least one external device, ie, an electrical component located away from the semiconductor substrate.

In FIG. 1, integrated circuit 12 includes a processor 14, a core logic circuit 16, a test logic circuit 18, and a pin interface 20 and is mounted on test equipment 22. The processor 14 is a programmable processor that executes computer program instructions stored in local memory and processes data as indicated by the stored instructions. For example, processor 14 may be a microprocessor, microcontroller, digital signal processor (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA), discrete logic circuit, or a combination of these components. .

The processor 14 generally operates in either a transmit mode or a receive mode. In one embodiment, processor 14 operates in a transmit and receive mode to write data to and receive data from an external device (not shown). In other embodiments, the processor 14 may operate in transmit and receive modes without writing data to or reading data from the external device. Transactions created in transmit mode and receive mode will be referred to as write transactions and read transactions, respectively, in this disclosure. When operating in transmit mode, processor 14 generates write transactions, also called request transactions, which are sent to core logic circuit 16. As an example, the request transaction identifies the external device and includes data to be written to the external device.

Processor 14 operates in a similar manner when operating in receive mode. That is, processor 14 generates read transactions and sends the read transactions to core logic circuit 16. In either case, ie when operating in transmit or receive mode, processor 14 generates a request transaction in accordance with the protocol assigned to core logic circuit 16. As described in greater detail, the core logic circuit 16 may include different blocks that communicate in accordance with different protocols. Thus, processor 14 generates transactions in accordance with the protocols for the corresponding blocks of core logic circuit 16.

The core logic circuit 16 provides an external interface for data transmission between the processor 14 and one or more external devices (not shown). In particular, the core logic circuit 16 manages communication between the processor 14 and external devices by generating transactions and routing transactions between the processor 14 and external devices in accordance with a protocol associated with the corresponding external interface. For example, when operating in transmit mode, core logic circuit 16 generates write transactions and routes the write transaction to the appropriate external device in accordance with the write (request) transaction received from processor 14. In some cases, core logic circuit 16 sends a response message to processor 14 to confirm the write transaction. The core logic circuit 16 may also receive a message from the external device in response to the corresponding write transaction sent to the external device. When the core logic receives a message from an external device, the core logic circuit 16 processes the message and sends an appropriate response to the processor 14.

Similarly, when operating in receive mode, core logic circuit 16 processes read (request) transactions received from processor 14 and generates corresponding read transactions and core logic circuit 16 responds to the corresponding. Send read transactions to the appropriate external interface device. The core logic circuit 16 generates read transactions in accordance with the protocol associated with the external device. In response to the read transaction, the core logic circuit 16 receives a message from an external device. The core logic circuit 16 processes the message and sends the corresponding message to the processor 14. The core logic circuit 16 may also process the message and send the message to the processor 14 in response to a read transaction received from the processor 14.

The core logic circuit 16 and one or more external devices can communicate via a single bus or collection of buses. Each bus may have a different architecture that may connect the core logic circuit 16 to one or more external devices and operate according to specific protocol, timing and bandwidth capabilities. Exemplary bus structures that can be used to interconnect integrated circuit 12 to external devices include, but are not limited to, Industry Standard Architecture (ISA) buses, Enhanced ISA (EISA) buses, peripheral component interconnects. Peripheral Component Interconnect (PCI) bus, Advance Graphics Processor (AGP) bus, universal serial bus (USB), enhanced high-performance bus (AHB), enhanced extensible interface , AXI (AXI) bus, Advanced technology Advancement (ATA) bus, small computer system interface (SCSI) bus, Ethernet bus, Universal Serial Bus (USB), and Serial Serial Advanced Technology Attachment (SATA) bus. Included. Other bus structures may be used to connect the integrated circuit 12 to external devices. The core logic circuit 16 and the processor 14 may communicate over one or more separate buses. In one embodiment, a separate dedicated bus, called the frontside bus, carries the transactions between the processor 14 and the core logic circuit 16.

In one embodiment, integrated circuit 12 may be used within a personal computer. In this example, core logic circuit 16 may manage communication between processor 14 and system memory operating as a central processing unit (CPU) via a high frequency memory bus. The core logic circuit 16 may also manage communication between the processor 14 and one or more keyboards, monitors, and mice via the ISA bus. In addition, the core logic circuit 16 may manage communication between the processor 14 and one or more Ethernet expansion cards, SCSI cards, or other PCI cards via the PCI bus. The core logic circuit 16 also communicates between the processor 14 and a dedicated video processor via an AGP bus, between the processor 14 and a CD-ROM or other hard disk via the ATA bus, and via USB. It may manage communications between the processor 14 and one or more printers, scanners, external mass storage media, or other USB compatible peripheral devices.

In operation within a personal computer, integrated circuit 12 retrieves a file stored in a memory module, such as a hard disk drive, a flash disk drive, or an erasable memory card, and displays the file on a monitor. In this case, the integrated circuit 12 may use a first external interface for communicating with the disk module, a second external interface for communicating with the system memory, and a third external interface for communicating with the display monitor. Each of the external interfaces can communicate according to a different protocol. For example, integrated circuit 12 initially follows the protocol associated with the disk module to request a file. When the disk module receives the request, the disk module provides the file to the integrated circuit 21. The integrated circuit 12 then writes the file to system memory attached to the system memory protocol to store data. When the integrated circuit 12 is ready to display the file on the monitor, the integrated circuit 12 reads data from the system memory and writes it to the display monitor according to the appropriate protocol for the display monitor. Integrated circuit 12 must follow the protocol to read data from and write data to these different modules. Modules that do not follow the protocol will not store or provide correct data.

As another example, integrated circuit 12 may be configured for use in a wireless communication device, such as a mobile radiotelephone handset. In this example, the integrated circuit 12 manages communication between the processor 14 and the system memory via the core logic circuit 16 memory bus, manages communication between the processor 14 and the keypad via the ISA bus, Manages communication between the processor 14 and erasable storage devices such as erasable memory cards via a USB bus, manages communication between the processor 14 and the display screen via a PCI bus, and manages the processor 14 through a different PCI bus. ) And a mobile station modem (MSM) for managing communication between the camera module and the like. In this example, processor 14 may operate as a Universal Mobile Communication System (UMTS), Mobile Communication Globalization System (GSM), Code Division Multiple Access (CDMA) protocol, and / or General Packet Radio Service (GPRS) processor. .

In the case where the integrated circuit 12 is configured to operate as an MSM chip, the integrated circuit 12 may interface with a camera module, a memory module, a system memory, and a display screen for taking a picture. Integrated circuit 12 may interface with each of these external devices in accordance with a different protocol. For example, integrated circuit 12 follows a protocol associated with the camera module to initiate communication with the camera module to capture a picture. When the camera module captures a picture, the integrated circuit 12 sends a request to the system memory to read the captured image data and write the image data to the system memory. Processor 14 processes the image data while the image data is in system memory. When processing is complete, the integrated circuit 12 reads data from the system memory according to the system memory protocol and transfers the image to the display screen. When the user requests to save the image, the integrated circuit 12 transfers the image to the disk drive. Again, integrated circuit 12 communicates with each of the external interfaces of the MSM chip, such as a camera interface, system memory interface, display interface, flash card / disk drive interface, according to a different protocol. For this reason, the integrated circuit 12 verifies post-manufacture functionality by testing communication through each external interface.

The core logic circuit 16 provides one or more interfaces, ie manages communication between the processor 14 and at least one external device. In particular, the core logic circuit 16 and the processor 14 may communicate with each other according to a single protocol. However, the core logic circuit 16 may communicate with each of the external interfaces according to respective protocols different from the protocol used to communicate with the processor 14. In other words, the core logic circuit 16 communicates with the processor 14 according to the first protocol, for example to receive a transaction request for writing data to the system memory, and executes a transaction for writing data to the system memory. It may be in communication with the processor 14 in accordance with the second protocol for transmission to the memory. Thus, the core logic circuit 16 is responsible for generating transactions in accordance with the appropriate protocol.

In other embodiments of the present disclosure, at least one of the external interfaces is a high frequency external interface. The high frequency external interface may operate at frequencies above about 200 MHz, within the range of about 200 MHz to about 400 MHz, or at frequencies above about 400 MHz. PCI, AHB, and AXI buses are exemplary high frequency external interfaces. In the case of the personal computer and wireless communication device described above, the memory bus, PCI bus, AGP bus, ATA bus, and USB buses may be high frequency interfaces. Other high frequency external interfaces include EISA buses, AHB buses, AXI buses, AXA buses, Ethernet buses, SCSI buses, and SATA buses.

The test logic circuit 18 is embedded on the semiconductor substrate of the integrated circuit 12 and is configured to verify the functionality of the high frequency external interfaces of the integrated circuit 12. Verifying the functionality of the high frequency external interfaces means verifying transactions sent over the high frequency interfaces. In one example aspect, test logic circuitry 18 may verify the transactions based on data associated with the transactions. In another aspect, the test logic circuit 18 may verify the transactions based on whether the transactions match the protocol associated with the transactions. When verifying transactions based on whether the transactions match the protocol, test logic circuitry 18 may also verify the transactions based on data associated with the transactions.

To verify the transactions, the test logic circuit 18 first snoops the communication channel or bus over which the transaction is sent. As described in more detail below, the test logic circuit 18 is a communication channel or bus between the processor 14 and the core logic circuit 16 or a communication channel or bus between the core logic circuit 16 and the pin interface 20. You can snoop. In either case, when test logic circuit 18 obtains a transaction, test logic circuit 18 examines the transaction to determine whether the transaction is valid. A transaction can be used, for example, by comparing the data associated with the transaction to reference data or by determining whether the transaction conforms to the associated protocol. In one embodiment, determining whether a transaction matches a related protocol may include checking control signals defined by the protocol. In other embodiments, determining whether the transaction matches the related protocol does not require checking the control signals. In either case, the test logic circuit 18 outputs a status signal indicating whether the transaction is valid, that is, whether the validity test passed or failed. This signal is for example output via the designated pin of the pin interface 20. At this point, the user is able to view status signals on the display monitor of the host computer that is interfacing with the test equipment 22 to determine whether the integrated circuit 12 is functioning.

Verifying the functionality of the high frequency external interfaces of the integrated circuit 12 does not require the test equipment 22 to provide high frequency signals to the integrated circuit 12, as described in the present disclosure. Rather, the test rig 22 is used to load the test program into the local memory of the processor 14. The processor 14 executes a test program that causes the integrated circuit 12 to simulate the operation of the transmit and receive modes. In other words, the test rig includes instructions that, when executable by the processor 14, cause the processor 14 and the core logic circuit 16 to generate write and read transactions sent over one or more external interfaces. The test logic circuit 18 snoops the communication channel of the integrated circuit 12 to obtain the transactions, and examines the transactions to determine the validity of the transactions. In this way, the test logic circuit 18 verifies that the processor 14 and the core logic circuit 16 follow the corresponding protocol when communicating over each of the external interfaces. As a result, the test is completed on-chip for the various operating conditions, otherwise the manual work that would otherwise be required to set up and / or initiate the test for each set of test conditions is not required. This reduces the time and cost required to verify the functionality and timing of external interfaces. In addition, test equipment 22 provides power, ground, and clock signals, such as non-test signals, such as system clock, system reset, and the like to integrated circuit 12 and provides a test program to integrated circuit 12. It can be a low cost device used to load. In this way, the test rig 22 does not need to be modified or updated to provide high frequency test signals.

Although the integrated circuit 12 is described in this disclosure as verifying the functionality of the high frequency interfaces, the test logic circuit 18 can be used to verify the functionality of the external interfaces operating at any frequency. This, in addition to purchasing new test equipment to verify the high cost of updating existing test equipment and the functionality of the high frequency external interfaces, ensures that each external interface has all possible operating conditions, eg supply voltage range, temperature range, and Because it is often tested for processing corners, verifying the functionality of external interfaces operating at any frequency can be complex and time-consuming task. In addition, manual changes are required to be made to the test program due to differences between integrated circuits.

However, since the test logic circuit 18 occupies an additional real estate on the semiconductor substrate, by providing test signals through the test equipment, an external interface operating at low frequencies, for example below 200 MHz. It is recognized that it may be desirable to verify these. This depends on the trade-off between the cost of the substrate space allocated to the test logic and the test cost without using the self test feature described in this disclosure. In other words, to supply the signals to verify the signals to verify the functionality of the external interfaces according to the cost of the physical area on the semiconductor substrate occupied by the test equipment 18 and techniques well known in the art at the time of the present disclosure. There is a trade-off between the costs associated with using test equipment. Thus, self test features for verifying the functionality of the external interfaces described in this disclosure can be used to verify the functionality of the external interfaces operating at any frequency, operating at high frequencies, for example 200 MHz or higher. It should be understood that this may be particularly useful for external interfaces.

2 is a block diagram illustrating the integrated circuit 12 in more detail. Specifically, integrated circuit 12 is shown in FIG. 2 as including external interface controllers 30A and 30B and test logic modules 32A and 32B. The external interface controllers 30A and 30B correspond to the core logic circuit 16 of FIG. That is, external interface controllers 30A and 30B represent individual blocks or modules of core logic circuit 16 associated with different external interfaces. For example, external interface controller 30A may manage communication over one type of high frequency external interface, such as a PCI bus, and external interface controller 30B may communicate over another type of high frequency external interface, such as an AGP bus. Can manage. External interface controllers 30A and 30B can manage communication with respective external devices according to different protocols. In FIG. 2, external interface controller 30A communicates with processor 14 via bus 31 and with a corresponding external device (not shown) via bus 33. The external interface controller 30B communicates with the processor 14 via the bus 35 and with the corresponding external device (not shown) via the bus 37. However, it should be understood that processor 14 and external interface controllers 30A and 30B may share some of one or more buses. That is, although communication channels are shown in FIG. 2 as being referred to as buses 31, 33, 35, and 37, these communication channels may represent single or multiple buses. As an example, the buses 31 and 35 may be a single bus, called a front-side bus, that provides a channel between the processor 14 and the core logic that may include multiple external interface controllers. have.

In a similar manner, test logic modules 32A and 32B represent individual blocks or modules of test logic circuit 18 associated with different external interfaces. Each of the test logic modules 32A and 32B verifies the functionality of the corresponding high frequency external interface. In Figure 2, test logic module 32A is associated with external interface controller 30A and test logic module 32B is associated with external interface controller 30B.

The test logic module 30A may snoop on the bus 31, the bus 35, or both. For example, the test logic module 32A may snoop the bus 31 to verify transactions generated by the processor 14 when operating in a transmit or receive mode. In another embodiment, the test logic module 32A may snoop the bus 31 to verify transactions generated by the external interface controller 30A and sent to the processor 14 in transmit or receive mode. When the external interface controller 30A is sent to the processor 14 in the receive mode, the test equipment 22 (not shown in FIG. 2) does not provide or check high frequency signals. Rather, the test rig module 32A transmits data and other signals as required by the protocol for the external interface controller 30A based on the seed value provided by the processor 14.

The external interface controller 30A generates corresponding write transactions and sends the write transactions to the processor 14 based on the data and other signals received from the test logic module 32A. In this manner, the test logic module 32A is conventional in that the test logic module 32A emulates the operation of the external device, i.e., provides the appropriate data and signals to the external interface controller 30A. It works in a similar way to test equipment. This is explained in more detail with reference to FIG. In a further embodiment, the test logic module 32A may snoop the bus 33 to verify transactions generated by the external interface controller 30A and sent to the pin interface 20 in transmit or receive mode. .

Test logic module 32B may operate in a similar manner to verify transactions sent over an external interface associated with external interface controller 30B. That is, the test logic module 32B may snoop the bus 35, the bus 37, or both to verify the transactions sent over the corresponding external interface in the transmit or receive mode.

In each of these embodiments, the test logic modules 32A and 32B may verify the transactions based on data associated with the transactions or based on whether the transactions match the associated protocol. Validating the transactions based on whether the transactions match the relevant protocol may include verifying that the transactions were created according to the rules defined by the protocol. Rules defined by the protocol may include rules that define data representation, signaling, authentication, error detection, and error handling. The test logic modules 32A and 32B may also verify the transactions based on the relevant data when verifying the transactions based on whether the transactions match the relevant protocol. The verification process used by the integrated circuit 12 is described in detail with reference to the block diagram shown in FIG. 3 and the flowcharts shown in FIGS. 4 and 5.

Although the integrated circuit 12 is shown in FIG. 2 as including two high frequency external interfaces, including test modules 32A and 32B and external interface controllers 30A and 30B, integrated circuit 12 is one. It may include the above external interfaces. Accordingly, FIG. 2 is to be understood as illustrative only and should not be intended to limit the present disclosure in any way. Rather, the purpose of FIG. 2 is to illustrate the relationship between the external interfaces of the integrated circuit and the test logic circuit embedded on the integrated circuit to verify the functionality of the external interfaces.

3 is a block diagram illustrating the components of the integrated circuit 12 in more detail. In particular, FIG. 3 shows processor 14, external interface controller 30A, and test logic module 32A in more detail. Processor 14 and external interface controller 30A provide external interfaces for performing read and write operations, for example, to write data to and read data from external devices (not shown). Works cooperatively. In particular, processor 14, external interface controller 30A, and corresponding external interface device communicate with each other according to respective protocols. That is, the processor 14 and the external interface controller 30A communicate with each other according to a specific protocol, and the external interface controller 30A and the external device communicate with each other according to different protocols. The test logic module 32A provides features for verifying the functionality of the external interface without requiring external test equipment such as test equipment 22 to supply and check high frequency signals. In one aspect, for example, test logic module 32A verifies transactions generated by one or both of processor 14 and external interface controller 30A based on data associated with the transactions. In another example aspect, the test logic module 32A verifies the transactions generated by one or both of the processor 14 and the external interface controller 30A based on whether the transactions match the associated protocol.

The processor 14 includes a memory 40, a processor 46, an input / output (I / O) module 48, and a transaction module 49. The memory 40 stores the test program 42 and state 44. The test program 42 is loaded into the memory 40 by the host computer via the test equipment 22 (not shown) and includes instructions for starting operation in a transmission mode or a reception mode when executed by the processor 46. do. When operating in a transmit mode or a receive mode, the processor 14 may, in some embodiments, perform operations for writing data to or reading data from a corresponding external device. In other embodiments, the processor 14 may perform operations when operating in a transmit or receive mode where there is no need to write data to or read data from the external device. In general, processor 46 processes data in accordance with instructions of test program 42 and controls the operation of transaction module 49 and I / O module 48.

When operating in transmit mode, for example, transaction module 49 generates write transactions under the control of processor 46. Exemplary write transactions include a request to write data to system memory, a request to the camera module to capture an image, and a request to a monitor to display the data. The write transaction for writing data to the external device may include data to be written to the external device and information identifying the external device.

Processor 46 may also control transaction module 49 to generate read transactions when operating in receive mode. Read transactions may request to retrieve data from memory, such as a hard disk or an erasable memory card, request to retrieve image data captured by a camera module of a handheld device, and retrieve data from a peripheral device. It may include a request to.

I / O module 48 transmits read and write transactions via bus 31 to external interface controller 30A. The bus 31 may be a front side bus through which the processor 14 communicates with an external interface controller 30A and additional external interface controllers. In the alternative, the bus 31 may be a dedicated bus for communication between the processor 14 and the external interface controller 30A.

The external interface controller 30A processes the write and read transactions received from the processor 14 and sends the corresponding write and read transactions to the corresponding external device in a real world environment. In the test environment, external interface controller 30A sends the corresponding transactions to the designated pin of interface 20. The following describes the operation of the external interface controller 30A with reference to the operation in the transmission mode. The operation of the external interface controller 30A in the receive mode will be described separately to avoid confusion.

In FIG. 3, external interface controller 30A includes transaction module 50 and I / O module 52. I / O module 52 manages I / O to external interface controller 30A. The I / O module directs write transactions received via the bus 31 to the transaction module 52 and applies the corresponding write transactions generated by the transaction module 50 to the bus 33. During the test, bus 33 is connected to a designated pin of pin interface 20 (not shown).

Transaction module 50 generates a write transaction corresponding to processing data contained in the received transactions and applying I / O module 52 to bus 33. Since external interface controller 30A communicates with processor 14 and corresponding external device in accordance with a different protocol, transaction module 50 generates transactions in accordance with the appropriate protocol. In this way, transaction module 50 can be seen as converting transactions from one protocol to another. Thus, the transaction module of each external interface controller can generate transactions in accordance with the protocol associated with the corresponding external interface. This is why core logic circuit 16 (shown in FIG. 1) can be seen to include a plurality of external interface controllers, such as controllers 30A and 30B in FIG. 2. Thus, transaction module 50 translates the write transaction received from processor 14 into a protocol associated with the corresponding external device.

As described above, the external interface controller 30A may, in the first embodiment, send a response message to the processor 14. In such embodiments, the transaction module 50 generates a response message and the I / O module 52 sends the response message over the bus 31 to the processor 14.

In the second embodiment, the external interface controller 30A may receive a response message from an external device corresponding to the case in which the external interface controller 30A operates in normal operation, that is, in a real environment. However, during the test, the external interface controller 30A receives a response message from the test logic module 32A. That is, the test logic module 32A provides signals other than the data as required for the external interface controller 30A, for example by protocol, such that the external interface generates a response message to which the controller 30A corresponds. To the processor 14. Referring to FIG. 3, I / O module 52 is directed to transaction module 50, which receives data and other signals from test logic module 32A via bus 33 and generates a corresponding response message thereof. direct). I / O module 52 sends a corresponding response message via bus 31 to processor 14.

In the third embodiment, the external interface controller 30A can send response messages according to the first and second embodiments. That is, the external interface controller 30A can send a first response message to the processor 14 in response to receiving a write transaction received from the processor 14 and sent to the external device by the external interface controller 30A. The second response message may be sent to the processor 14 in response to receiving the third response message corresponding to the write transaction.

In the fourth embodiment, the external interface controller 30A does not generate any response signals. The external interface controller 30A can operate in accordance with any of these embodiments. Thus, testing the external interface controller 30A may include verifying the operation of the external interface controller 30A in accordance with each of the embodiments.

The test logic module 32A verifies the functionality of the external interface provided by the processor 14 and the external interface controller 30A in transmit and receive modes. The test logic module 32A also provides data and other signals provided by the associated protocol to the external interface controller 30A to emulate the operation of the external device. By using the test logic module 32A instead of the external test equipment to supply data and signals, the external test equipment does not need to operate at high frequencies, and therefore, integrated circuit devices at progressively increasing operating frequencies If it needs to be tested, it may not need to be modified, upgraded or replaced.

In operation, processor 14 initiates or enables test logic module 32A. That is, the processor 46 generates a control signal according to the test program 42, and the I / O module 48 transmits the test program 42 to the test logic module 32A through the dedicated line connection 61. . Prior to receiving the control signal, the test logic module 32A may be disabled, i.e. deactivated. Thus, processor 14 may send a control signal to test logic module 32A before sending the write transaction to external interface controller 30A. However, in response to receiving the control signal, test logic module 32A can actively snoop buses 31 and 33. In this way, the test logic module 32A may obtain all transactions over the buses, and thus may determine whether too many or too few transactions have been sent in addition to verifying the transactions sent at the appropriate time.

In FIG. 3, the test logic module 32A includes a verification module 60, a pseudo random data generator 62, and an I / O module 64 and controlled from the processor 14 via a dedicated line connection 61. Receive the signal. I / O module 64 snoops buses 31 and 33 in transmit mode to intercept write transactions generated by processor 14 and external interface controller 30A, respectively. I / O module 64 may also snoop bus 31 to retrieve response messages or transactions sent by external interface controller 30A to processor 14.

The control signal includes a seed value used by the test logic module 32A to generate reference data. In particular, the pseudo random data generator 62 receives the seed value from the I / O module 64 and associates the data specified by the test program 42, that is, the data associated with the write transaction generated by the processor 14. Seed values are used to generate matching reference data. The pseudo random data generator 62 outputs the reference data to a module 60 that compares the reference data with data associated with the intercepted transaction, i.e., the write transaction intercepted on the bus 31. In embodiments in which test logic module 32A verifies transactions based on whether a transaction matches a protocol, verification module 60 may check data after checking the protocol.

An example protocol may define a signal that is used to indicate when data is being delivered. The signal may have a first state indicating that data transfer is in progress and a second state indicating that data transfer is not in progress. Thus, the verification module 60 will only check the data of the transaction provided by the I / O module 64 only if the control signal is in the first state. By verifying the data when the control signal is in the first state, the verification module 60 verifies that the transaction matches the data and protocol associated with the transaction. In this manner, the validation module 60 may determine when the transaction matches the protocol and the data is valid, when the transaction matches the protocol and the data is valid, and when the transaction does not match the protocol. However, if the verification module 60 only checks data associated with one transaction, the data may be valid but the transaction may not match the protocol. For this reason, verifying based on whether a transaction matches the protocol can provide a more accurate test to determine the functionality of the external interface. The above description is an example used to provide a simple illustrative description of validating transactions and should not be considered limiting of the disclosure in any way. Rather, the protocol may define multiple signals, and in such cases, may define multiple states checked to verify a transaction. In the case where multiple states are defined, verifying the transactions may include checking one or more states or checking a sequence of one or more states.

The verification module 60 generates a status signal indicating the status of the transaction. When the verification module 60 verifies a transaction based on the relevant data, the status signal may indicate whether the transaction has passed or failed. However, if the validation module 60 validates the transaction based on whether the transaction matches the protocol, the status signal indicates whether the transaction matches the protocol and the data is valid, and when the transaction matches the protocol and the data is valid. And when the transaction does not match the protocol.

In Fig. 3, the verification module 60 outputs a status signal via the dedicated line connection 61. Processor 14 updates state 44 based on the received signal. In particular, I / O module 48 directs status signals to processor 46 updating status 44 within memory 40. State 44 is a parameter that indicates the state of the external interface. For example, state 44 may store a "PASS" value if the transaction matches the protocol and the data is valid, or a "DATA ERROR" value if the transaction matches the protocol but the data is invalid. If the transaction does not match the protocol, store the "Protocol Error" value. In this case, the processor 14 is based on the value recorded in the state 44 read by the test equipment 22 (not shown in FIG. 3) and displayed to the user via a host computer connected to the test equipment 22. Will generate a signal. In an alternative aspect, the verification module 60 may send a status signal to the I / O module 64 that outputs the status signal directly to the designated pin of the pin interface 20.

The test logic module 32A uses a similar process to verify write transactions generated by the external interface controller 30A. That is, the I / O module 64 snoops the bus 33 to intercept the write transaction and the verify module 60 generates a reference to the data associated with the intercepted transaction by the pseudo random data generator 62. Compare to the data. The verification module 60 then outputs a status signal based on the comparison.

As described above, in some example aspects, the external interface controller 30A sends a response message to the processor 14 in response to receiving the response message from the external device. In these example aspects, the test logic module 32A and, in some example aspects, the external interface controller 30A, in response to receiving or verifying a write transaction generated by the external interface controller 30A. It provides the data and other signals required by the relevant protocol to the external interface controller 30A, which emulates a response message that would have been generated by the external device in normal operation. In this way, test logic module 32A typically provides the functionality provided by external test equipment and test equipment 22 (not shown in FIG. 3) can be implemented as low cost test equipment. Referring to Fig. 3, the verification module 60 may generate a response message, i.e., a signal different from the data required by the protocol, and the I / O module 64 may externally transmit the response message via the bus 33. Transfer to interface controller 30A.

The external interface controller 30A sends a corresponding response message to the processor 14 via the bus 31. The test logic module 32A snoops the bus 31 to intercept and verify the response message sent to the processor 14 using the techniques provided in the previous description.

The previous description relates to the operation of the integrated circuit 12 in the transmission mode. The following description relates to the operation of the integrated circuit 12 in the receive mode. In order to verify the functionality of the external interface when operating in the receive mode, based on the data associated with the transaction or based on whether the transaction conforms to the associated protocol, the integrated circuit 12 may select the processor 14 and the external interface controller in receive mode. Verify the transactions created by 30A. This means that read transactions generated by processor 14 sent to external interface controller 30A, read transactions generated by external interface controller 30A sent to pin interface 20, and processor 14 It is necessary to verify the response messages generated by the external interface controller 30A transmitted. As described above, the external interface controller 30A, in some example aspects, generates and transmits a response message corresponding to the read transaction received from the processor 14 to the processor 14 as well. In these example aspects, this response message is also verified.

When operating in the receive mode, the processor 14 transmits a read transaction to the external interface controller 30A which generates a read transaction in accordance with the test program 42 and sends the read transaction to a corresponding read transaction to an external device. . The test logic module 32A verifies the read transactions using techniques similar to those used to verify write transactions generated in the transmission mode. In case the external interface controller 30A sends a response message to the processor 14 after receiving the read transaction from the processor 14, the test logic module 32A also uses the same verification techniques to verify the response message. .

However, when operating in the receive mode, external interface controller 30A receives a response message from an external device in response to a read transaction sent to the same external device. Since the external test equipment 22 does not provide high frequency signals, during the test, the test logic module 32A provides the external interface controller 30A with data and other signals required by the protocol. Thus, the test logic module 32A is the test logic module 32A to the external interface controller 30A which causes the external interface controller 30A to generate or send a corresponding response message or transaction to the processor 14. The test logic module 32A operates in a manner similar to conventional test equipment in that it provides data and other signals required by this protocol.

Referring to Figure 3, the verification module 60 generates a response message that may include data and other signals required by the protocol and the I / O module 64 externally sends the response message via the bus 33. Transfer to interface controller 30A. I / O module 64 may wait for the appropriate protocol on bus 33 before sending a response message. The verification module 60 may generate a response message after generating a status signal associated with the corresponding read transaction received from the external interface controller 30A.

I / O module 52 receives the response message and sends it to transaction module 50. Transaction module 50 processes the response message and generates a corresponding response message that I / O module 52 sends to processor 14 via bus 31.

The test module 32A verifies the response message generated by the external interface controller 30A. In particular, I / O module 64 snoops bus 31 to retrieve the response message and validation module 60 verifies the retrieved response message based on whether the associated data or response message matches the associated protocol. do. The verification module 60 outputs a status signal indicating whether the response signal is valid to complete the verification process.

4 is a flow diagram illustrating an exemplary technique that may be executed by integrated circuit 12 to verify a transaction sent over a high frequency external interface based on data associated with the transaction. In general, the steps shown in FIG. 4 may be used to verify a transaction generated in a transmit mode and a receive mode and are described with respect to the components of the integrated circuit 12 shown in FIG. The flow chart begins when the integrated circuit 12 is mounted to the test equipment 22 via the pin interface 20 during the post-production test. Initially, the host computer loads the test program onto integrated circuit 12 (70). The test program can be developed on the host computer and loaded into the program memory 42 of the processor 14 via the test equipment.

Processor 14 and external interface controller 30A generate transactions 72 and transmit the transactions over the bus 74 according to test program instructions. For example, steps 72 and 74 may correspond to an external device via a processor or bus 33 that transmits a write transaction to interface controller 30A via bus 31 when operating in transmit mode. Reference may be made to the external interface controller sending the transaction. In the embodiment where the integrated circuit 12 operates in a receive mode, operations 72 and 74 correspond to a processor 14, an external device, which transmits a read transaction to the external interface controller 30A via the bus 31. Reference may be made to an external interface controller 30A sending a read transaction or an external interface controller 30A sending a response message to the processor 14. That is, operations 72 and 74 generally refer to a single transaction that is created during the process of performing a read or write operation. Thus, it will be clear that the operations of the flowchart shown in FIG. 4 may be repeated to verify the complete write or read operation.

Test logic module 32A snoops 76 on the appropriate bus, i.e., the bus on which the transaction is sent in operation 74 to retrieve or intercept the transaction. Thus, the test logic module 32A is configured to verify transactions generated by the processor 14 in the transmit mode or receive mode and transactions generated by the external interface controller 30A in the receive mode and for these transactions. The bus 33 can be snooped to verify the responses for transactions generated by the external interface controller 30A. Since write and read operations require the transfer of write and read transactions over buses 31 and 33, test logic module 32A uses buses 31 and 33 to verify the complete signal path of the external interface. Is usually snooped.

When retrieving a transaction, test logic module 32A verifies the transaction by generating reference data (78) and comparing the data associated with the transaction with the reference data (80). The test logic module 32A may generate reference data based on the seed value provided by the processor 14, more specifically based on the control signal received from the processor 14. The control signal, i.e. the seed value, may be transmitted over a dedicated line connection or a corresponding bus.

Based on the comparison, test logic module 32A generates 82 a status signal indicating whether the transaction is valid. The test logic module 32A may apply the state signal directly to the output of the pin interface 20. The output can be connected to a host computer having a display for viewing status signals. As a result, the user may examine the state to determine whether the transaction created in step 72 is valid (84). Alternatively, the status signal can be received by processor 14 and used to set the value of a memory parameter that can be read and displayed on a monitor.

5 is a flow diagram illustrating an example technique that may be performed by integrated circuit 12 to verify a transaction sent over a high frequency external interface based on whether a transaction conforms to an associated protocol. The steps shown in FIG. 5 may be used to verify a transaction generated in a transmission mode or a reception mode. Similar to the flowchart shown in FIG. 4, the steps of the flowchart shown in FIG. 5 are executed when the integrated circuit 12 is mounted to the test equipment 22 via the pin interface 20 during the post-production test.

Initially, the host computer loads the test program 42 into the integrated circuit 12 through the test equipment 22 (70). The test program 42 is developed for testing the functionality of the external interfaces when operating in the transmit mode and the receive mode. Thus, integrated circuit 12 generates a transaction in accordance with the test program instructions (102) and transmits the transaction over the bus (104). Similar to FIG. 4, operations 102 and 104 refer to a single read or write transaction generated by processor 14 or external interface controller 30A during a read or write operation. However, it should be understood that the operations of the flowchart of FIG. 5 may be repeated to verify multiple read and write transactions generated during read and write operations.

Snooping 106 the bus to retrieve or intercept the transaction may refer to test logic module 32A snooping the bus to which the transaction is sent in operation 102. The test logic module 32A may actively snoop on the appropriate bus when receiving control signals from the processor 14. The processor 14 may transmit a control signal to enable the test logic module 32A when the test program 42 is loaded into the memory.

When retrieving the transaction, the test logic module 32A verifies 108 the retrieved transaction based on whether the transaction matches the associated protocol. For example, test logic module 32A may verify the transaction by checking one or more signals defined by the protocol. This includes checking a sequence of states defined by one or more signals or one or more states defined by a signal. For example, if the protocol defines a signal indicating when data is being delivered, the test logic module 32A may check this signal to determine whether the data is being delivered at the time specified by the protocol. Can be. More generally, however, the test logic module 32A examines the transaction to determine whether the transaction satisfies the rules set by the protocol, that is, whether the transaction matches the protocol.

The test logic module 32A may then generate reference data 110 based on, for example, a seed value provided by the control signal received from the processor 14. The test logic module 32A verifies 112 the data associated with the transaction by comparing the data associated with the transaction with reference data. Accordingly, test logic module 32A may generate a status signal indicative of the status of the transaction (114). For example, the test logic module 32A may indicate whether a transaction matches the related data and the data is valid, a transaction matches the related protocol but the data is not valid, or the transaction does not match the protocol. You can generate a signal.

The user can then examine the status signal to determine whether the transaction is valid (116). As an example, the status signal may be output to a designated pin of the pin interface 20 or may be used to set the value of a stored parameter of the memory of the processor 14. In either case, the status signal can be read by the test equipment 22 to be displayed on the monitor of the host computer.

Various aspects and embodiments have been described. However, modifications may be made to the techniques or structure of the present disclosure without departing from the claims. For example, the integrated circuits described above include various IC process technologies such as complementary metal oxide semiconductor (CMOS), bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), and the like. It can be prepared with. These and other aspects of the disclosure are within the scope of the claims.

Claims (72)

As an integrated circuit,
A processor operative to execute instructions of a test program, the processor operative to generate a message comprising data;
Core logic circuitry operative to receive the message from the processor in accordance with the test program; And
Test logic circuitry operative to snoop the message sent from the processor to the core logic circuitry, evaluate the message, and provide a status signal to the processor indicating whether the message is valid. ,
Wherein the message is communicated in accordance with a protocol, and the test logic circuit generates reference data and determines whether the message is consistent with the protocol and the data associated with the message and the reference data. Evaluating the message based on at least one of the comparisons,
integrated circuit. The method of claim 1,
The core logic circuit is configured to operate at a frequency in the range of 200 MHz to 400 MHz,
integrated circuit. The method of claim 1,
The core logic circuit is configured to operate at a frequency greater than 400 MHz,
integrated circuit. delete delete The method of claim 1,
The core logic circuit includes a peripheral component interconnect (PCI) bus, an advanced high-performance bus (AHB), an advanced extensible interface (AXI) bus, and a small computer system interface. to external devices through one of the following: a small computer system interface (SCSI) bus, Ethernet bus, Universal Serial Bus (USB), Advance Graphics Processor (AGP) bus, and serial serial advanced technology attachment (SATA) bus. Operative to connect,
integrated circuit. The method of claim 1,
The message is a first message,
When operating in a transmit mode, the core logic circuit generates a second message based on the first message and transmits the second message to an external device,
The test logic circuit is operative to snoop the second message, the test logic circuit providing a second status signal to the processor that evaluates the second message and indicates whether the second message is valid;
integrated circuit. The method of claim 1,
The message is a first message,
When operating in a receive mode, the core logic circuit generates a second message based on the first message and sends the second message to an external device,
The test logic circuit is operative to snoop the second message, the test logic circuit provides a second status signal to the processor that evaluates the second message and indicates whether the second message is valid, and
The test logic circuit is further operative to generate a third message based on the second message and send the third message to the core logic circuit to emulate the external device,
integrated circuit. The method of claim 8,
The core logic circuit is operative to generate a fourth message based on the third message and send the fourth message to the processor,
The test logic circuitry provides a third status signal to the processor that evaluates the fourth message and indicates whether the fourth message is valid;
integrated circuit. delete delete delete The method of claim 1,
The core logic circuit generates a response message associated with the message and sends the response message to the processor,
The test logic circuitry provides a second status signal to evaluate the response message and indicate whether the response message is valid;
integrated circuit. The method of claim 1,
The integrated circuit is configured to operate in one of a personal computer, a laptop computer, a personal digital assistant (PDA), an ultra mobile personal computer (UMPC), a wireless communication device, a networking device, and an electronic computing device,
integrated circuit. The method of claim 1,
The integrated circuit is configured to operate as a mobile station modem (MSM) chip of a wireless communication device,
integrated circuit. As a method,
Executing instructions of a test program at a processor on an integrated circuit;
Generating a message comprising data at the processor to communicate with a core logic circuit of the integrated circuit in accordance with the test program;
Sending the message from the processor to the core logic circuit;
Snooping the message in a test logic circuit of the integrated circuit;
Evaluating the message in the test logic circuit to determine whether the message is valid, wherein the message is communicated according to a protocol, and evaluating the message comprises generating reference data and Evaluating the message based on at least one of a determination of whether the protocol matches the protocol and a comparison of the reference data with data associated with the message; And
Providing a status signal from the test logic circuit to the processor indicating whether the message is valid,
Way. 17. The method of claim 16,
The core logic circuit is configured to operate at a frequency in the range of 200 MHz to 400 MHz,
Way. 17. The method of claim 16,
The core logic circuit is configured to operate at a frequency higher than 400 MHz,
Way. delete delete 17. The method of claim 16,
The core logic circuit includes a peripheral component interconnect (PCI) bus, an enhanced high performance bus (AHB), an enhanced extensible interface (AXI) bus, a small computer system interface (SCSI) bus, an Ethernet bus, a universal serial bus (USB). Operative to connect with external devices through one of the following: AGP bus, and Serial ATA (SATA) bus,
Way. 17. The method of claim 16,
Executing the instructions includes executing instructions of the test program at the processor to initiate operation in a transmission mode, the method comprising:
Generating a second message in the core logic circuit based on the message;
Sending the second message to a pin interface of the integrated circuit to provide the message to an external device;
Snooping the second message in the test logic circuit;
Evaluating the second message in the test logic circuit to determine whether the second message is valid; And
Providing a second status signal from the test logic circuit to the processor indicating whether the second message is valid;
Way. 17. The method of claim 16,
Executing the instructions comprises executing instructions of the test program at the processor to initiate operation in a receive mode, the method comprising:
Generating a second message in the core logic circuit based on the message;
Sending the second message from the core logic circuit to a pin interface of the integrated circuit to provide the message to an external device;
Snooping the second message in the test logic circuit;
Generating a third message in the test logic circuit based on the second message; And
Sending the third message from the test logic circuit to the core logic circuit,
The test logic circuit emulates the external device,
Way. 24. The method of claim 23,
Generating a fourth message in the core logic circuit based on the third message;
Sending the fourth message from the core logic circuit to the processor;
Snooping the fourth message in the test logic circuit;
Evaluating the fourth message in the test logic circuit to determine whether the fourth message is valid; And
Providing a second status signal from the test logic circuit to the processor indicating whether the fourth message is valid;
Way. delete delete delete 17. The method of claim 16,
Generating a response message associated with the message in the core logic circuit, transmitting the response message to the processor, evaluating the response message in the test logic circuit, and indicating whether the response message is valid Generating at the test logic circuit a second state signal;
Way. 17. The method of claim 16,
The integrated circuit is configured to operate in one of a personal computer, a laptop computer, a personal digital assistant (PDA), an ultra mobile personal computer (UMPC), a mobile handset, a networking device, and an electronic computing device,
Way. As an integrated circuit,
Means for executing instructions of a test program on an integrated circuit to initiate operation in one of a transmit mode and a receive mode;
Means for generating a message comprising data at a processor to communicate with a core logic circuit of the integrated circuit in accordance with the test program;
Means for sending the message from the processor to the core logic circuit;
Means for snooping the message in a test logic circuit of the integrated circuit;
Means for evaluating the message in the test logic circuit to determine whether the message is valid, the message being communicated according to a protocol, and the means for evaluating the message comprising: means for generating reference data; Means for evaluating the message based on at least one of a determination of whether the message conforms to the protocol and a comparison of the reference data with data associated with the message; And
Means for providing a status signal from the test logic circuit to the processor indicating whether the message is valid;
integrated circuit. delete delete delete delete delete 31. The method of claim 30,
Means for executing the instructions includes means for executing instructions of the test program at the processor to initiate operation in the transmission mode, wherein the integrated circuit comprises:
Means for generating a second message in the core logic circuit based on the message;
Means for sending the second message to a pin interface of the integrated circuit to provide the message to an external device;
Means for snooping the second message in the test logic circuit;
Means for evaluating the second message in the test logic circuit to determine whether the second message is valid; And
Means for providing a second status signal from the test logic circuit to the processor indicating whether the second message is valid;
integrated circuit. 31. The method of claim 30,
Means for executing the instructions includes means for executing instructions of the test program at the processor to initiate operation in the receive mode, wherein the integrated circuit comprises:
Means for generating a second message in the core logic circuit based on the message;
Means for sending the second message from the core logic circuit to a pin interface to provide the second message to an external device;
Means for snooping the second message in the test logic circuit;
Means for generating a third message in the test logic circuit based on the second message; And
Means for sending the third message from the test logic circuit to the core logic circuit,
The test logic circuit emulates the external device,
integrated circuit. 39. The method of claim 37,
Means for sending a fourth message in the core logic circuit based on the third message;
Means for sending the fourth message from the core logic circuit to the processor;
Means for snooping the fourth message in the test logic circuit;
Means for evaluating the fourth message in the test logic circuit to determine whether the fourth message is valid;
Means for providing a second status signal from the test logic circuit to the processor indicating whether the fourth message is valid;
integrated circuit. delete delete delete 31. The method of claim 30,
Means for generating a response message associated with the message in the core logic circuit, means for sending the response message to the processor, means for evaluating the response message in the test logic circuit, and the response message is valid. Means for generating, in said test logic circuit, a second status signal indicating whether or not;
integrated circuit. delete A computer-readable medium for storing instructions executable by a computer, the instructions comprising:
Instructions executable by the computer to initiate operation in one of a transmission mode and a reception mode;
Instructions executable by the computer to generate a message comprising data of a processor for communicating with a core logic circuit of an integrated circuit in accordance with a test program;
Instructions executable by the computer to send the message from the processor to the core logic circuitry;
Instructions executable by the computer to snoop the message from a test logic circuit of the integrated circuit;
Instructions executable by the computer to evaluate the message in the test logic circuit to determine whether the message is valid—the message is communicated according to a protocol and executable by the computer to evaluate the message The instructions may be adapted to generate the reference data based on at least one of instructions executable by the computer to determine whether the message matches the protocol and comparison of the reference data with the data associated with the message. Instructions executable by the computer to evaluate; And
Instructions executable by the computer to provide a status signal from the test logic circuit to the processor indicating whether the message is valid,
Computer-readable media. delete delete delete delete delete 45. The method of claim 44,
Instructions executable by the computer to generate a second message in the core logic circuit based on the message;
Instructions executable by the computer to snoop the second message in a test logic circuit;
Instructions executable by the computer to evaluate the test logic circuit to determine whether the message is valid; And
Further instructions executable by the computer to provide a second status signal from the test logic circuit to the processor indicating whether the second message is valid;
Computer-readable media. 45. The method of claim 44,
Instructions executable by the computer to generate a second message in the core logic circuit based on the message;
Instructions executable by the computer to send the second message from the core logic circuit to a pin interface to provide the second message to an external device;
Instructions executable by the computer to snoop the second message in the test logic circuit;
Instructions executable by the computer to generate a third message in the test logic circuit based on the second message; And
Further instructions executable by the computer to send the third message from the test logic circuit to the core logic circuit,
The test logic circuit emulates the external device,
Computer-readable media. 52. The method of claim 51,
Instructions executable by the computer to generate a fourth message in the core logic circuit based on the third message;
Instructions executable by the computer to send the fourth message from the core logic circuit to the processor;
Instructions executable by the computer to snoop the fourth message from the test logic circuit;
Instructions executable by the computer to evaluate the fourth message in the test logic circuit to determine whether the fourth message is valid; And
Further instructions executable by the computer to provide a second status signal from the test logic circuit to the processor indicating whether the fourth message is valid;
Computer-readable media. delete delete delete 45. The method of claim 44,
Instructions executable by the computer to generate a response message in the core logic circuit associated with the message;
Instructions executable by the computer to send the response message to the processor;
Instructions executable by the computer to evaluate the response message in the test logic circuit; And
Further instructions executable by the computer to generate, in the test logic circuit, a second status signal indicating whether the response message is valid;
Computer-readable media. delete A system comprising an integrated circuit,
The integrated circuit is:
A processor operative to execute instructions of a test program, the processor operative to generate a message comprising data;
An interface controller coupled to the processor via a bus, the interface controller operative to receive the message over the bus from the processor in accordance with the test program; And
A test logic circuit external to the processor and the interface controller,
The test logic circuit is coupled to the bus, the test logic circuit operates to intercept the message sent over the bus, the test logic circuit evaluating the message and based on the evaluation Provides a status signal to the pin interface indicating whether is valid.
The message is communicated according to a protocol, and the test logic circuit generates at least one of: generating reference data and determining whether the message conforms to the protocol and comparing the reference data with data associated with the message. To evaluate the message based on
system. delete delete delete delete The method of claim 1,
The processor executes instructions of the test program in a receive mode, and the test logic circuitry is further configured to generate second data associated with the protocol based on a seed value in the test logic circuit provided by the processor. Sending a second message to the core logic circuit,
integrated circuit. 64. The method of claim 63,
The core logic circuit generates a third message based on the second data received from the test logic circuit;
integrated circuit. The method of claim 1,
The test logic circuit comprises a pseudo random data generator for receiving a seed value from the processor and generating second data, the second data matching the test data specified by the test program,
integrated circuit. 66. The method of claim 65,
The test logic circuit comprises a verify circuit, the verify circuit comparing the second data with data snooped from the message to determine whether the message is valid,
integrated circuit. 17. The method of claim 16,
The processor executes instructions of the test program in a receive mode, the method further comprising:
Sending a second message from the test logic circuit to the core logic circuit, the second message comprising second data required by a protocol, the second message being based on a seed value in the test logic circuit provided by the processor Further comprising:
Way. 68. The method of claim 67,
Generating a third message in the core logic circuit based on the second data received from the test logic circuit,
Way. 17. The method of claim 16,
Receiving a seed value at the pseudo random data generator of the test logic circuit from the processor; And
In the pseudo random data generator, generating second data corresponding to a second message, which matches the test data specified by the test program,
Way. 70. The method of claim 69,
In the verification module of the test logic circuit, further comprising comparing the second data with data snooped from the message to determine whether the message is valid,
Way. 59. The method of claim 58,
The interface controller generates a second message based on the message and sends the second message to an external device via a second bus,
The test logic circuit is coupled to the second bus, the test logic circuit is operative to intercept the second message via the second bus, the test logic circuit evaluates the second message and the second message Provide a second status signal to the pin interface indicating whether is valid;
The test logic circuit is further operative to generate a third message based on the second message and send the third message to the interface controller via the second bus to emulate the external device;
system. The method of claim 71 wherein
The interface controller is operative to generate a fourth message based on the third message and send the fourth message to the processor via the bus; and
The test logic circuitry evaluates the fourth message and provides a third status signal to the pin interface indicating whether the fourth message is valid;
system.

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