KR101258249B1 - Thin film transistor array substrate for liquid crystal display and manufacturing method thereof - Google Patents

Abstract

Provided are a thin film transistor array substrate and a method of manufacturing the same, which can prevent current movement due to channel formation when isopotential is formed between data lines respectively connected to an even / od shorting bar. A thin film transistor array substrate for a liquid crystal display includes: a thin film transistor arranged in a matrix form at each intersection area of a plurality of gate lines and data lines; An odd shorting bar commonly connected to odd data lines of the plurality of data lines; An even shorting bar connected to the even data lines among the plurality of data lines in common; And an equipotential that is directly connected to odd data lines branched from the odd shorting bar and even data lines branched from the even shorting bar to form an equipotential between the odd data lines and the even data line until source / drain formation of the thin film transistor. line; And a passivation layer for protecting the thin film transistor and a plurality of gate lines and data lines, wherein the isopotential line is disconnected at the passivation layer after channel formation according to source / drain formation, and the pattern for forming the equipotential line is equipotential The ratio W / L of the width W of the line to the width L of the channel is formed to have a small value.

Liquid crystal display, equipotential lines, channel formation, even shorting bar, odd shorting bar,

Description

Thin film transistor array substrate for liquid crystal display device and manufacturing method therefor {THIN FILM TRANSISTOR ARRAY SUBSTRATE FOR LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF}

1 is a view schematically showing a configuration of a general liquid crystal panel.

FIG. 2 is a diagram schematically illustrating an equipotential line formed on a general liquid crystal panel.

3 is a plan view illustrating a thin film transistor array substrate having an equipotential line according to the related art.

4A and 4B are detailed views illustrating portions in which the equipotential lines of FIG. 3 are formed, respectively.

5A and 5B are vertical sectional views of FIGS. 4A and 4B, respectively.

6 is a plan view illustrating a thin film transistor array substrate on which an equipotential line is formed according to an embodiment of the present invention.

7 is a view for explaining an equipotential line according to an embodiment of the present invention.

8 is a vertical cross-sectional view for explaining a method for forming an equipotential line according to an exemplary embodiment of the present invention.

9A to 9D are diagrams illustrating an equipotential line pattern according to an exemplary embodiment of the present invention, respectively.

DESCRIPTION OF THE REFERENCE NUMERALS

400: pixel area 600: data pad area

700: equipotential line forming area 800: aude / even shorting bar area

710, 750: first equipotential line 720, 760: second equipotential line

730, 770: disconnection area (open hole) 740, 780: gate metal layer

810: Aether Shorting Bar 820: Even Shorting Bar

830: odd data line 840: even data line

850: contact electrode 860: contact hole

The present invention relates to a liquid crystal display device, and more particularly, to a thin film transistor array substrate for a liquid crystal display device for forming an equipotential between an odd data line and an even data line when manufacturing a thin film transistor for a liquid crystal display device, and a method of manufacturing the same. will be.

In general, a liquid crystal display is an apparatus that expresses an image by using optical anisotropy and birefringence characteristics of liquid crystal molecules. In the liquid crystal display, two substrates on which the field generating electrodes are formed are disposed so that the surfaces on which the two electrodes are formed face each other, a liquid crystal material is injected between the two substrates, and then a voltage is applied to the two electrodes. By changing the arrangement of the liquid crystal molecules by the electric field, and by controlling the amount of light transmitted through the transparent insulating substrate through this, the desired image is expressed.

As the liquid crystal display, a thin film transistor liquid crystal display (TFT LCD) using a thin film transistor (TFT) as a switching element is mainly used.

1 is a view schematically showing a configuration of a general liquid crystal panel.

Referring to FIG. 1, a liquid crystal panel provided in a liquid crystal display includes a thin film transistor array substrate 10, a color filter substrate 20, and the thin film transistor array substrate 10 and the color filter substrate bonded to each other with a predetermined space. It consists of the liquid crystal layer 30 injected between the 20. In this case, the thin film transistor array substrate 10 is defined as a TFT region TFT, a pixel region Pixel, and a charging region C _ST which are switching regions.

In the thin film transistor array substrate 10, a plurality of gate lines 12 are arranged in one direction on a transparent glass substrate 11, and a plurality of gate lines 12 are arranged in a direction perpendicular to the gate line 12. By arranging the plurality of data lines 16, the pixel area Pixel is defined.

In addition, a pixel electrode 18 is formed in each pixel region Pixel, and a thin film transistor TFT is formed at a portion where each of the gate lines 12 and the data lines 16 intersect, and the thin film transistors are formed in the gate. The data signal of the data line 16 is applied to each pixel electrode 18 according to the scan signal applied through the line 12.

In the color filter substrate 20, a black matrix layer 22 is formed on the transparent glass substrate 21 to block light except for the pixel region Pixel. In the portion corresponding to each pixel region, R, G, and B color filter layers 23 are formed to express colors, and a common electrode 24 is formed on the color filter layers 23.

A charging capacitor C _ST connected in parallel with the pixel electrode 18 is configured on the gate line 12, and a portion of the gate line 12 is used as the first electrode of the charging capacitor C _ST . As the second electrode, an island-shaped metal pattern formed of the same material as the source and drain electrodes is used.

In the liquid crystal display, the liquid crystal layer 30 formed between the thin film transistor array substrate 10 and the color filter substrate 20 is aligned by an electric field between the pixel electrode 18 and the common electrode 24. The desired image can be expressed by adjusting the amount of light passing through the liquid crystal layer 30 according to the degree of alignment of the liquid crystal layer 30.

Meanwhile, the thin film transistor array substrate 10 undergoes a signal inspection process for detecting line defects such as short circuits and disconnections of the gate and data lines 12 and 16 and defects of the thin film transistor TFT after the fabrication process. . An odd shorting bar connected to the thin film transistor array substrate 10 by being divided into odd lines and even lines of each of the gate lines 12 and the data lines 16. (Shorting Bar) and Even Shorting Bar.

In detail, the inspection of the gate lines uses a gate odd shorting bar commonly connected to the odd gate lines and a gate even shorting bar commonly connected to the even gate lines. The inspection of the data lines detects a line failure by using a data odd shorting bar commonly connected to odd data lines and a data even shorting bar commonly connected to even data lines.

FIG. 2 is a diagram schematically illustrating an equipotential line formed on a general liquid crystal panel.

Referring to FIG. 2, the liquid crystal panel includes a pixel area 40, a gate pad part 50, a data pad part 60, an equipotential line forming area 70, and an even / odd shorting bar area. An equipotential line formation region 70 is formed between the data pad portion 60 and the even / od shorting bar 80 to form an equipotential between the data lines, and then the liquid crystal cell is manufactured. , Along the scribing line between the equipotential line forming region 70 and the data pad portion 60.

3 is a plan view illustrating a thin film transistor array substrate having an equipotential line according to the related art.

Referring to FIG. 3, a thin film transistor array substrate including a data shorting bar includes a thin film transistor TFT formed at each intersection of the gate line 41 and the data line 43; A pixel electrode Pixel connected to the thin film transistor TFT; A charging capacitor C _ST formed at an overlapping portion of the pixel electrode Pixel and the previous gate line 41; A gate pad portion (not shown) connected to the gate line 41; An array area including a data pad part 60 connected to the data line 43; An odd shorting bar 81 commonly connected to the odd data lines 83 via the data pad unit 60; A shorting bar region 80 including an even shorting bar 82 commonly connected to the even data lines 84; And an equipotential line 70 connected to the odd data line 83 and the even data line 84 to form an equipotential.

First, the odd shorting bar 81 of the data shorting bars is formed to be commonly connected to the odd data lines 83 and via the data pad unit 60, and the even shorting bar 82 is even data lines 84. And a common connection with the data pad unit 60.

The odd shorting bar 81 is formed of a source / drain metal layer together with the data lines 43. Alternatively, the even shorting bar 82 is formed of a gate metal layer to be insulated from the odd data lines 83 crossing therethrough. The even shorting bar 82 formed of the gate metal layer is connected to the even data lines 84 formed of the source / drain metal layer through the contact electrode 86 formed over the contact hole 85. When the thin film transistor array substrate is completed, defect inspection of the data lines 43 is performed by using the odd shorting bar 81 and the even shorting bar 82. Subsequently, the data shorting bar 80 is cut along the scribing line between the even shorting bar 82 and the data pad part 60.

However, even in the thin film transistor array substrate, the even data lines 84 may be relatively susceptible to static electricity during the manufacturing process. This is because each even data line 84 is independently separated from the source / drain metal layer patterning until the contact electrode 86 is formed. Alternatively, the odd data lines 83 are commonly connected by an odd shorting bar 81 formed of the same source / drain metal layer. Accordingly, when static electricity is introduced after the source / drain metal layer patterning, electrostatic components are diffused and weakened in the odd data lines 83 commonly connected by the odd shorting bar 81, thereby causing damage by static electricity. Will not. However, each of the even data lines 84 is independently separated until the contact electrode 86 is formed and commonly connected by the even shorting bar 82. Accordingly, when static electricity flows into the even data lines 84 before the contact electrode 86 is formed, the thin film transistors connected to the even data lines 84 by the static electricity are damaged or even data lines ( 84) and defects such as dielectric breakdown occur at the intersection of the gate line and the like.

That is, the data even / od connection line is formed of the gate and source / drain metal layers, respectively. At this time, it is necessary to form an equipotential pattern to form an equipotential between the data lines. It was.

By the way, when the equipotential lines according to the prior art have a straight structure, a phenomenon of locally disconnecting or connecting according to the equipotential pattern line width may occur, which may cause a problem of a TFT pad.

4A and 4B are detailed views of portions where the equipotential lines of FIG. 3 are formed, respectively, and FIGS. 5A and 5B show vertical cross-sectional views of FIGS. 4A and 4B, respectively.

Referring to FIG. 4A, a first equipotential branched from the odd data line 83 connected to the odd shorting bar 81 to form an equipotential between the odd data line 83 and the even data line 84. A second equipotential line 72 branching from the line 71 and the even data line 84 connected to the even shorting bar 82 is formed, and the first equipotential line 71 and the second equipotential line 72 are formed. ) Is connected until the source / drain formation, and then disconnection regions 73a and 73b are formed to disconnect the protective film. The disconnection regions 73a and 73b form open holes before the passivation layer forming process to disconnect the first equipotential line 71 and the second equipotential line 72.

4B is the same as FIG. 4A except that the gate metal layer 74 is formed below the disconnection region, and thus a detailed description thereof will be omitted. 5A and 5B are vertical cross-sectional views of FIGS. 4A and 4B, respectively, wherein the first equipotential line 71 and the second equipotential line 72 are source / drain, as indicated by reference numerals A and B. FIG. After disconnection until formation, it is each disconnected by an open hole before forming a protective film.

3, 5A, and 5B, an even shorting bar 82 formed of a gate metal layer is formed on the lower substrate 51, and a gate insulating layer 52 is formed thereon. The odd data lines 83, the even data lines 84, and the odd shorting bars 81 formed of the source / drain metal layers are formed on the gate insulating layer 52, and the passivation layer 55 is formed thereon. A contact hole 85 penetrating the gate insulating layer 52 and the passivation layer 55 is formed to expose the even data lines 84 and the even shorting bar 82 shown in FIG. 3, and the contact hole 85 is formed. The contact electrode 86 is formed over the cavities so that the even data lines 84 made of different metal layers and the even shorting bar 82 are connected to each other.

However, when the channel structure inside the equipotential pattern according to the related art is changed, that is, connected only until the source / drain progresses, and then manufactured to be disconnected after the passivation process through channel formation, the current shifts due to the channel formation. The phenomenon occurs, which causes a problem that the resistance between the data lines can be reduced.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to provide a thin film transistor array substrate for a liquid crystal display device and a method of manufacturing the same, which can prevent current movement due to channel formation when forming an equipotential line.

Another object of the present invention is to provide a thin film transistor array substrate for a liquid crystal display device and a method of manufacturing the same, which can reduce occurrence of defects in a TFT pad part by providing various pattern structures for forming an equipotential.

The objects of the present invention are not limited to the above-mentioned objects, and other objects not mentioned can be clearly understood by those skilled in the art from the following description.

In order to achieve the above object, according to the present invention, a thin film transistor arranged in a matrix form at each intersection region of a plurality of gate lines and data lines; An odd shorting bar connected to odd data lines among the plurality of data lines; An even shorting bar connected to the even data lines among the plurality of data lines in common; And directly connected to odd data lines branched from the odd shorting bar and even data lines branched from the even shorting bar, between the odd data lines and the even data line until source / drain formation of the thin film transistor is formed. An equipotential line forming an equipotential; And a passivation layer for protecting the thin film transistor and the plurality of gate lines and data lines, wherein the equipotential line is disconnected at the passivation layer after the channel formation according to the source / drain formation and disconnects the equipotential line. The pattern for forming is characterized in that the ratio (W / L) of the width (W) of the equipotential line and the width (L) of the channel has a small value.

Here, as the ratio (W / L) of the width (W) of the equipotential line and the width (L) of the channel has a smaller value, the resistance between the data lines is increased, thereby increasing the current movement according to the channel formation. It is characterized by preventing.

The equipotential line may include: a first equipotential line branched from the odd data line or the even data line; A second equipotential line branching from the even data line or the odd data line; And a disconnection region for opening the equipotential line by an open hole after the first and second equipotential lines are connected until the source / drain formation.

The open hole may be formed before the passivation layer forming process, and may open the equipotential lines between the odd data lines and the even data lines.

Herein, any one of the first equipotential line and the second equipotential line may be directly connected to the odd shorting bar.

Here, the equipotential line is formed on the gate metal layer that is formed to be the same when forming the gate of the thin film transistor.

The shorting bar of any one of the odd shorting bar and the even shorting bar, the data lines, and the equipotential line may be formed of a source / drain metal layer, and the shorting bar of the other shorting bar and the even shorting bar may be a gate. A metal layer is formed, and a gate insulating layer is formed between the source / drain metal layer and the gate metal layer. In addition, the shorting bar formed of the gate metal layer and the data lines formed of the source / drain metal layer may further include a contact electrode electrically connected through the contact hole.

In addition, the method of manufacturing a thin film transistor array substrate according to the present invention includes the steps of: a) forming a thin film transistor arranged in a matrix form in each of the intersection of the plurality of gate lines and data lines; b) forming an odd shorting bar commonly connected to odd data lines of the plurality of data lines and an even shorting bar commonly connected to even data lines of the plurality of data lines; c) an equipotential line forming an equipotential between odd data lines branching from the odd shorting bar and even data lines branching from the even shorting bar, wherein the equipotential line is formed after the channel formation according to source / drain formation. Disconnecting at formation, wherein the ratio (W / L) of the width (W) of the equipotential line and the width (L) of the channel is formed to have a small value; d) an open hole that opens the equipotential line between the odd and even lines with a plurality of contact holes that partially expose the desired portions of the data and gate lines, the thin film transistors and the shorting bars. Forming a; And e) forming a contact electrode formed over the contact holes together with the pixel electrode.

Here, as the ratio (W / L) of the width W of the equipotential line and the width L of the channel in step c) has a smaller value, the resistance between the data lines is increased, thereby increasing the channel formation. It is characterized by preventing the current from moving.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments make the disclosure of the present invention complete and the general knowledge in the technical field to which the present invention belongs. It is provided to fully convey the scope of the invention to those skilled in the art, the invention being defined only by the scope of the claims.

Hereinafter, a thin film transistor array substrate for a liquid crystal display according to an exemplary embodiment of the present invention and a method of manufacturing the same will be described in detail.

The embodiment of the present invention minimizes the occurrence of TFT pad defects due to the generation of different potentials in the even / od lines as the even / od lines are connected to the gate metal and the source / drain metal for the data line inspection in the TFT LCD structure. do.

Specifically, in the embodiment of the present invention, the equipotential is formed by tying the even / od data lines with the source / drain metal layer, and when the source / drain is formed, a current shift phenomenon may occur due to the channel formation. By changing the equipotential pattern structure in a direction in which the ratio W / L of the width W to the width L of the channel becomes small, the resistance between the data lines is increased. At this time, the equipotential lines are connected only until the source / drain progresses, and are disconnected after the passivation process through channel formation.

6 is a plan view illustrating a thin film transistor array substrate on which an equipotential line is formed according to an embodiment of the present invention.

Referring to FIG. 6, a thin film transistor array substrate having an equipotential line according to an embodiment of the present invention may include a pixel region 400, a data pad region 600, an equipotential line forming region 700, and an odd / even shorting bar region. 800.

In the pixel region 400, a thin film transistor TFT arranged in a matrix form is formed at each intersection area of the plurality of gate lines 410 and the data lines 430. In this case, the thin film transistor TFT is a gate. 420, a source 440, and a drain 450, and are connected to the pixel electrode Pixel by the contact hole 460. In addition, a charge capacitor Cst is formed in the pixel area 400 by overlapping the previous gate line 410.

The data pad 610, the contact hole 630, and the contact electrode 620 are formed in the data pad region 600 to connect the data line 430 to the odd / even shorting bars 810 and 820.

The odd / even shorting bar area 800 includes an odd shorting bar 810 and an even shorting bar 820, and the odd shorting bar 810 is an odd data line 830 among the plurality of data lines 430. ) And the even shorting bar 820 is commonly connected to the even data lines 840 of the plurality of data lines 430.

The equipotential line forming station 700 is directly connected to the odd data lines 830 branched from the odd shorting bar 810 and the even data lines 840 branched from the even shorting bar 820. An equipotential is formed between the odd data lines 830 and the even data lines 840 until the source / drain is formed.

In this case, the equipotential lines may include: first equipotential lines 710 and 750 branched from the odd data line 830 or the even data line 840; Second equipotential lines 720 and 760 branching from the even data line 840 or odd data line 830; And opening the equipotential lines 710, 720, 750, and 760 by an open hole after the first equipotential lines 710 and 750 and the second equipotential lines 720 and 760 are connected until the source / drain formation. The disconnection area 730 is included. Here, the open hole is formed before the passivation layer forming process and opens the equipotential line between the odd data lines 830 and the even data lines 840. In addition, the disconnection region 730 may be formed on the gate metal layer 740.

In this case, the equipotential lines 710 and 720 are disconnected when the passivation layer is formed after the channel formation according to the source / drain formation, and the pattern for forming the equipotential line is the width W of the equipotential line and the width of the channel. The ratio W / L of (L) is formed to have a small value. That is, as the ratio (W / L) of the width (W) of the equipotential line and the width (L) of the channel has a smaller value, the resistance between the data lines increases, and accordingly, the current movement according to the channel formation is increased. It can be prevented.

In addition, a passivation layer (not shown) is formed to protect the thin film transistor and the plurality of gate lines and data lines.

One of the first equipotential lines 710 and 750 and the second equipotential lines 720 and 760 may be directly connected to the odd shorting bar 810. In addition, the equipotential line may be a molybdenum (Mo) metal pattern connecting the even data line 840 and the odd data line 830.

In addition, the shorting bar, the data lines 430 and the equipotential lines 710, 720, 750, and 760 of any one of the odd shorting bar 810 and the even shorting bar 820 may be formed of a source / drain metal layer. The other shorting bar of the odd shorting bar 810 and the even shorting bar 820 is formed of a gate metal layer, and a gate insulating layer (not shown) is formed between the source / drain metal layer and the gate metal layer. .

In this case, the shorting bar 820 formed of the gate metal layer and the even data lines 840 formed of the source / drain metal layer may further include a contact electrode 850 electrically connected through the contact hole 860. do.

In addition, the odd shorting bar 810, the even shorting bar 820, and the equipotential lines 710, 720, 750, and 760 may be cut along the scribing line after the liquid crystal cell inspection.

In detail, the thin film transistor array substrate illustrated in FIG. 6 includes a thin film transistor TFT formed at each intersection of the gate line 410 and the data line 430, a pixel electrode Pixel connected to the thin film transistor TFT, A charge capacitor Cst formed at an overlapping portion of the pixel electrode Pixel and the previous gate line 410, and a gate pad portion (not shown) connected to the gate line 410; An array area including a data pad part 600 connected to the data line 430; The odd shorting bar 810 commonly connected to the odd data lines 830 via the data pad unit 600, and the even show commonly connected to the even data lines 840 via the data pad unit 600. Equipotential lines 710, 720, and 750 for common connection between the odd data lines 830 and the even data lines 840 before the patterning process of the data shorting bar region 800 formed of the setting bar 820 and the passivation patterning process. 760 having an equipotential line formation region 700, including 760.

The gate line 410 and the data line 430 intersect insulated with the gate insulating film interposed therebetween. The thin film transistor TFT formed at each intersection of the gate line 410 and the data line 430 includes a gate electrode 420 connected to the gate line 410, and a source electrode connected to the data line 430. An active layer (not shown) overlapping the 440, the drain electrode 450 connected to the pixel electrode Pixel, and the gate electrode 420, and forming a channel between the source electrode 440 and the drain electrode 450. ). In this case, the active layer typically extends along the data line 430. An ohmic contact layer is formed on the active layer except for the channel portion. The thin film transistor TFT keeps the pixel voltage signal supplied to the data line 430 charged in the pixel electrode Pixel in response to the scan signal supplied to the gate line 410.

The pixel electrode Pixel is connected to the drain electrode 450 of the thin film transistor TFT through the first contact hole 460 that passes through the passivation layer (not shown). The pixel electrode Pixel generates a potential difference from a common electrode formed on a color filter substrate, which is typically an upper substrate (not shown), by the charged pixel voltage. Due to this potential difference, the liquid crystal positioned between the thin film transistor array substrate and the color filter substrate is rotated by dielectric anisotropy, and transmits light incident through the pixel electrode Pixel from a light source (not shown) to the color filter substrate.

The charging capacitor Cst overlaps the previous gate line 410, the charging electrode 470 overlapping between the gate line 410 and the gate insulating film, and the charging electrode 470 and the passivation layer therebetween. The pixel electrode Pixel is connected via the second contact hole 480 formed in the passivation layer. The charging capacitor Cst allows the pixel voltage charged in the pixel electrode Pixel to be stably maintained until the next pixel voltage is charged.

The data line 430 is connected to a data driver (not shown) via the data pad part 600, and the gate line 410 is also connected to a gate driver (not shown) via the gate pad part.

The data pad unit 600 is a data pad 610 extending from the data line 430 via a data link, and a data pad connected to the data pad 610 through a third contact hole 630 penetrating through the passivation layer. A protective electrode 620 is formed.

The odd shorting bar 810 of the data shorting bar is commonly connected to the odd data lines 830 via the data pad part 600, and the even shorting bar 820 is even data via the data pad part 600. It is commonly connected with the lines 840.

The odd shorting bar 810 and the equipotential lines 710, 720, 750, and 760 are formed of a source / drain metal layer together with the odd and even data lines 830 and 840.

Alternatively, the even shorting bar 820 is formed of a gate metal layer to be insulated from the odd data lines 830 across it.

The even shorting bar 820 formed of the gate metal layer is connected to the even data lines 840 formed of the source / drain metal layer through the contact electrode 850 formed over the contact hole 860 as shown in FIG. 6. Equipotential lines 710, 720, 750, and 760 commonly connect the data lines 430 from the patterning process of the source / drain metal layer to the passivation patterning process to form an equipotential. Accordingly, when static electricity flows into the data lines 430 during the process, static electricity is diffused through the common connected data lines 430 to prevent static damage such as thin film transistor damage and dielectric breakdown caused by the static electricity. It becomes possible. The equipotential lines 710, 720, 750, and 760 are opened between the even and odd data lines 830 and 840 through open holes 730 by a patterning process of the passivation layer. When the thin film transistor array substrate is completed, defect inspection of the data lines 430 is performed using the odd shorting bar 810 and the even shorting bar 820. Subsequently, the data shorting bars 810 and 820 are cut along the scribing line between the equipotential lines 710, 720, 750, and 760 and the data pad part 600.

7 is a view for explaining an equipotential line according to an embodiment of the present invention.

Referring to FIG. 7, in the equipotential lines 710 and 720 according to an embodiment of the present invention, a pattern for forming the equipotential lines may include a ratio W of the width W of the equipotential line and the width L of the channel. / L) is formed to have a small value. In other words, the smaller the ratio (W / L) of the width (W) of the equipotential line and the width (L) of the channel is, the higher the resistance between the data lines increases, and accordingly, current movement according to the channel formation. Can be prevented. Subsequently, the equipotential lines 710 and 720 are disconnected when the passivation layer is formed after the channel formation according to the source / drain formation.

Thus, by reducing the width W of the equipotential line or increasing the width L of the channel, current cannot be moved.

In addition, the pattern for forming the equipotential lines may be formed into a plurality of fine patterns, as described above by reducing the width (W) of the equipotential line or by increasing the width (L) of the channel, As long as the ratio W / L of the width W of the line to the width L of the channel is made small, it is apparent to those skilled in the art that it is irrelevant to its shape. Various examples of the pattern for forming the equipotential lines will be described later with reference to FIGS. 9A to 9D.

FIG. 8 is a vertical cross-sectional view illustrating a method for forming an equipotential line according to an exemplary embodiment of the present invention. The thin film transistor array substrate according to the exemplary embodiment of the present invention may include a lower substrate 510, a gate insulating layer 520, and an active layer 530. ), An equipotential line 710 and 720 formed in correspondence with the source / drain layer of the ohmic contact layer 540, and an open hole are formed to disconnect the equipotential lines 710 and 720, and then a protective film formed thereon. 550 is formed. Here, although the gate metal layer 740 is illustrated as being formed on the lower substrate 510, the gate metal layer 740 may not be formed.

Here, the equipotential lines 710 and 720 formed corresponding to the source / drain layers are disconnected by the open holes 730, where the width L of the channel is formed as large as possible, and the equipotential lines 710 , The width W of 720 is formed to be small, so that the equipotential line pattern is formed in a direction in which the ratio W / L of the width W of the equipotential line and the width L of the channel decreases.

Meanwhile, in the method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention, a thin film transistor arranged in a matrix form is formed at each intersection of a plurality of gate lines and data lines, and then, the plurality of data lines. An odd shorting bar connected to odd data lines among the odd data lines and an even shorting bar commonly connected to even data lines among the plurality of data lines are formed.

Next, an equipotential line is formed between the odd data lines branched from the odd shorting bar and the even data lines branched from the even shorting bar, wherein the equipotential line is a channel according to source / drain formation. After formation, it is disconnected at the time of forming the protective film, and is formed such that the ratio (W / L) of the width (W) of the equipotential line and the width (L) of the channel has a small value. Here, as the ratio (W / L) of the width (W) of the equipotential line and the width (L) of the channel has a smaller value, the resistance between the data lines is increased, thereby increasing the current movement according to the channel formation. Will be prevented.

Next, an open to open the equipotential line between the odd and even lines together with a plurality of contact holes that partially expose the desired portions of the data and gate lines, the thin film transistors and the shorting bars. A hole is formed, and then, along with the pixel electrode, a contact electrode formed over the contact holes is formed.

6 and 8, a method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention will be described in detail as follows.

First, an even data shorting bar is formed on the lower substrate 510, and the even data shorting bar 820 is formed by depositing a gate metal material on the lower substrate 510 by a deposition method such as sputtering and then using an exposure process using a mask. It is formed by patterning with an etching process. The even data shorting bar 810 is formed with gate patterns including the gate line 410 and the gate electrode 440 in the array illustrated in FIG. 6. In this case, as the gate metal, chromium (Cr), molybdenum (Mo), an aluminum metal, or the like is used in a single layer or a double layer structure.

Next, a gate insulating film 520 is formed on the lower substrate 510 on which the even shorting bar 820 is formed, and the odd and even data lines 830 and 840, the odd shorting bar 810, and the equipotential are formed thereon. Lines 710, 720, 750, 760 are formed.

The gate insulating layer 520 is formed by depositing a gate insulating material on the entire surface by a deposition method such as plasma enhanced chemical vapor deposition (PECVD). As the gate insulating material, silicon oxide (SiOx) or silicon nitride (SiNx) is used. Subsequently, an amorphous silicon layer and an n + amorphous silicon layer are sequentially stacked on the gate insulating film 520, and then patterned by an exposure process and an etching process using a second mask to form an active layer 530 and an ohmic contact layer in the array illustrated in FIG. 6. 540 is formed. The odd and even data lines 830 and 840, the odd shorting bar 810, and the equipotential lines 710, 720, 750, and 760 are formed by depositing a source / drain metal material on the gate insulating layer 520 by sputtering. After the deposition, the pattern is formed by an exposure process using an third mask and an etching process. These odd and even data lines 830, 840, odd shorting bar 810, and equipotential lines 710, 720, 750, and 760 include data lines 430 and source electrodes 440 in the array shown in FIG. 6. ) And the source / drain patterns including the drain electrode 460, the charging electrode 470, the data pad 620, and the like.

The equipotential lines 710, 720, 750, and 760 form an equipotential by connecting the odd data lines 830 and the even data lines 840 in common. Accordingly, the static electricity flowing into the odd and even data lines 830 and 840 until the equipotential lines 710, 720, 750 and 760 are opened by the odd and even data lines 830 and 840 connected to each other. By spreading over a wide area, it is possible to prevent defects caused by static electricity. As the source / drain metal, a metal which can be dry etched, such as molybdenum (Mo), is used to open the equipotential lines 710, 720, 750, and 760 in the patterning process of the protective film.

Next, a passivation layer 550 including a contact hole 860 and an open hole 730 is subsequently formed.

In this case, the protective film 550 is formed by depositing an insulating material on the entire surface by a deposition method such as PECVD. As the insulating material of the passivation layer 550, an inorganic insulating material such as the gate insulating film 520 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB is used. The contact holes 860 of the even shorting bar 820 may be formed by patterning the passivation layer 550 and the gate insulating layer 520 in an exposure process using a mask and a dry etching process. 460, 480, and 630. At the same time, an open hole 36 for opening the equipotential lines 710, 720, 750, and 760 is also formed through the passivation layer 550 and the equipotential lines 710, 720, 750, and 760 by a dry etching process. A contact electrode 850 is further formed over the contact hole 860.

The contact electrode 850 is formed by depositing a transparent electrode material on the passivation layer 550 by a deposition method such as sputtering, and then patterning it by an exposure process and an etching process using a mask. The contact electrode 850 is formed together with the transparent electrode pattern including the pixel electrode Pixel, the data pad protection electrode 620, and the like in the array illustrated in FIG. 6. Indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide (IZO) is used as the transparent electrode material.

As described above, in the method of manufacturing a thin film transistor array substrate, the odd and even data lines are used from the source / drain metal layer patterning process to the patterning process of the passivation layer 550 using the equipotential lines 710, 720, 750, and 760. Equipotentials are formed by common connection between 830 and 840. Accordingly, the static electricity introduced into the odd and even data lines 830 and 840 during the process is diffused to the odd and even data lines 830 and 840 forming an equipotential.

9A to 9D are diagrams illustrating equipotential line patterns according to embodiments of the present invention, respectively.

FIG. 9A illustrates a case where the equipotential lines 710 and 720 are connected to the odd data line 830 and the even data line 840, respectively, and there is no gate metal layer 740 under the disconnection region 730. 9b illustrates a case where the gate metal layer 740 is formed below the disconnection region 730, and FIG. 9c illustrates a case where the equipotential lines 710 and 720 are linear on a plane. 9D illustrates a case in which the first equipotential line 710 is directly connected to the odd shorting bar 810 instead of the odd data line 830.

In the thin film transistor array substrate and the method of manufacturing the same according to the present invention, the equipotential lines are formed by common connection of data lines from the source / drain metal layer patterning process to the protective film patterning process using the equipotential lines, and the width (W) of the equipotential lines. By forming the equipotential pattern in which the ratio (W / L) of the width L of the channel is reduced, it is possible to prevent current movement due to channel formation at the time of forming the equipotential line.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. Therefore, the embodiments described above are to be understood in all respects as illustrative and not restrictive.

According to the present invention, by forming an equipotential pattern in which the ratio (W / L) of the width of the equipotential line and the width of the channel is reduced, it is possible to prevent current movement due to channel formation at the time of forming the equipotential line. In addition, it is possible to reduce the occurrence of defects in the TFT pad part by providing various pattern structures for forming the equipotential.

Claims (15)

A thin film transistor arranged in a matrix at each intersection of the plurality of gate lines and the data lines; An odd shorting bar connected to odd data lines among the plurality of data lines; An even shorting bar connected to the even data lines among the plurality of data lines in common; And Equipotential between the odd data lines and the even data line is directly connected to the odd data lines branched from the odd shorting bar and the even data lines branched from the even shorting bar until the source / drain formation of the thin film transistor is formed. An equipotential line forming a; And A passivation layer for protecting the thin film transistor and the plurality of gate lines and data lines / RTI > The equipotential lines are disconnected when the passivation layer is formed after the channel formation according to the source / drain formation, and the pattern for forming the equipotential lines is a ratio of the width W of the equipotential line and the width L of the channel. A thin film transistor array substrate, wherein (W / L) is formed to have a small value. The method of claim 1, As the ratio (W / L) of the width (W) of the equipotential line and the width (L) of the channel has a smaller value, the resistance between the data lines increases, thereby preventing current from moving due to the channel formation. Thin film transistor array substrate, characterized in that. The method of claim 1, wherein the equipotential line, A first equipotential line branched from the odd data line or the even data line; A second equipotential line branching from the even data line or the odd data line; And Disconnection region for opening the equipotential line by an open hole after the first and second equipotential lines are connected until the source / drain formation Thin film transistor array substrate comprising a. The method of claim 3, The open hole is formed before the passivation layer forming process, wherein the equipotential line is opened between the odd data lines and the even data lines. The method of claim 3, The thin film transistor array substrate of claim 1, wherein any one of the first and second equipotential lines is directly connected to the odd shorting bar. The method of claim 1, The equipotential line is a thin film transistor array substrate, characterized in that formed on the gate metal layer that is formed the same when forming the gate of the thin film transistor. The method of claim 1, The equipotential line is a thin film transistor array substrate, characterized in that the molybdenum (Mo) metal pattern connecting the even data line and the odd data line. The method of claim 1, The shorting bar, the data lines and the equipotential line of any one of the odd shorting bar and the even shorting bar are formed of a source / drain metal layer, The shorting bar of the other one of the odd shorting bar and the even shorting bar is formed of a gate metal layer, and a gate insulating film is formed between the source / drain metal layer and the gate metal layer. 9. The method of claim 8, And a contact electrode to which the shorting bar formed of the gate metal layer and the data lines formed of the source / drain metal layer are electrically connected via a contact hole. The method of claim 1, And the odd shorting bar, the even shorting bar, and the equipotential line are cut along the scribing line after inspecting the liquid crystal cell. a) forming a thin film transistor arranged in a matrix at each intersection of the plurality of gate lines and the data lines; b) forming an odd shorting bar commonly connected to odd data lines of the plurality of data lines and an even shorting bar commonly connected to even data lines of the plurality of data lines; c) an equipotential line forming an equipotential between odd data lines branching from the odd shorting bar and even data lines branching from the even shorting bar, wherein the equipotential line is formed after the channel formation according to source / drain formation. Disconnecting at formation, wherein the ratio (W / L) of the width (W) of the equipotential line and the width (L) of the channel is formed to have a small value; d) an open hole that opens the equipotential line between the odd and even lines with a plurality of contact holes that partially expose the desired portions of the data and gate lines, the thin film transistors and the shorting bars. Forming a; And e) forming a contact electrode formed over the contact holes together with a pixel electrode; Method of manufacturing a thin film transistor array substrate comprising a. 12. The method of claim 11, As the ratio (W / L) of the width (W) of the equipotential line of step (c) and the width (L) of the channel has a smaller value, the resistance between the data lines increases, and thus the current according to the channel formation. A method of manufacturing a thin film transistor array substrate, characterized in that the movement is prevented. 12. The method of claim 11, And the isopotential line of step c) is formed on the gate metal layer formed at the same time when the gate of the thin film transistor is formed. The method of claim 11, wherein b), Forming the shorting bar, the data lines, and the equipotential line of any one of the odd shorting bar and the even shorting bar as a source / drain metal layer; And The shorting bar of the other one of the odd shorting bar and the even shorting bar is formed of a gate metal layer, and forming a gate insulating layer between the source / drain metal layer and the gate metal layer. Method of manufacturing a thin film transistor array substrate comprising a. The method of claim 14, And forming a contact electrode in which the shorting bar formed of the gate metal layer and the data lines formed of the source / drain metal layer are electrically connected to each other via a contact hole.

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