KR101229832B1 - Method of fabricating semiconductor substarte and method of fabricating lighe emitting device - Google Patents

Abstract

Disclosed are a semiconductor substrate manufacturing method and a light emitting device manufacturing method. According to one embodiment of the present invention, in a method of manufacturing a semiconductor substrate, a first semiconductor layer is formed on a substrate, a metal material layer is formed in a pattern shape on the first semiconductor layer, and the first semiconductor layer is formed on the first semiconductor layer. And forming a second semiconductor layer on the metallic material layer, forming a cavity in the first semiconductor layer below the metallic material layer, and heating the substrate after forming the second semiconductor layer. Thereby growing the cavity in the first semiconductor layer. Accordingly, the growth substrate can be removed by the growth of the cavity, so that it is not necessary to separate the growth substrate using a laser, and thus the substrate manufacturing cost can be reduced.

Description

Method of manufacturing semiconductor substrate and method of manufacturing light emitting device {METHOD OF FABRICATING SEMICONDUCTOR SUBSTARTE AND METHOD OF FABRICATING LIGHE EMITTING DEVICE}

The present invention relates to a semiconductor substrate manufacturing method and a light emitting device manufacturing method, and more particularly, to a semiconductor substrate manufacturing method and a light emitting device manufacturing method using a novel peeling method of a growth substrate.

BACKGROUND OF THE INVENTION Light emitting diodes (hereinafter referred to as LEDs) using gallium nitride (GaN) -based semiconductors have been used in various devices such as signal signals and backlights of liquid crystal panels. It is known that the luminous efficiency of LED is influenced by dislocation density and defect of a crystal. Crystal growth of GaN-based semiconductors is performed on dissimilar substrates such as sapphire, but it is considered that lattice mismatch and mismatch of thermal expansion coefficients occur between the GaN layer and the substrate, leading to an increase in high potential density and defects.

Here, it is preferable to perform crystal growth of a GaN type semiconductor on the board | substrate of the same material, such as a GaN substrate. On the other hand, GaN is difficult to form a GaN melt due to the high dissociation rate of nitrogen, etc., making it difficult to manufacture a GaN substrate. In order to peel GaN bulk crystals grown for GaN substrates as GaN substrates, mechanical polishing and laser peeling are used, but it is very difficult to reproduce practically sized GaN substrates. In particular, peeling using a laser requires a large amount of time, causing a cost increase of the GaN substrate.

In addition, in the paper "Polycrystalline GaN for light emitter and field electron emitter applications" S. Hasegawa, S. Nishida, T. Yamashita, H. Asahi, Thin Solid Films 487 (2005) 260-267, W, Mo An example of crystal growth of GaN using plasma assisted molecular beam epitaxy on high melting point metal substrates of Ta, Ta, and Nb, and on Si substrates is shown.

However, as described above, the manufacture of GaN substrates is very difficult and expensive, so that light emitting devices such as LEDs and laser diodes are often manufactured by growing GaN layers on dissimilar substrates such as sapphire. However, the increase in the high potential density and defects described above hinders the improvement of the light emitting performance of the LED. In addition, the sapphire substrate has a lower thermal conductivity than the GaN substrate and lowers the heat radiation of the device. This causes the long life of the LED or laser diode to be prevented.

In order to solve the problem of sapphire, on the other hand, after growing the GaN layer using these dissimilar substrates as a growth substrate, a secondary substrate is attached, and using an excimer laser, GaN at the interface between the sapphire and the GaN layer, which is a growth substrate, is grown. Laser lift-off methods have been developed to locally decompose the layer to remove sapphire. This method is particularly used for manufacturing light emitting devices having vertical structures suitable for large area light emitting diodes (power chips) and the like.

However, as described above, peeling of the growth substrate using a laser requires a large amount of time, thereby increasing the manufacturing cost of the light emitting element. In addition, in order to irradiate a laser through sapphire, it is necessary to increase the laser transmittance of sapphire and polish the exposed surface of sapphire. For this reason, the thickness of sapphire becomes thin and it is unsuitable to use again.

The technical problem to be solved by the present invention is to provide a semiconductor substrate manufacturing method and a light emitting device manufacturing method that can remove the growth substrate without using a laser.

The technical problem to be solved by the present invention is to provide a semiconductor substrate manufacturing method and a light emitting device manufacturing method capable of reusing the growth substrate without the need to polish the growth substrate.

According to one Embodiment of this invention, the manufacturing method of a semiconductor substrate is provided. The method forms a first semiconductor layer on a substrate, forms a metallic material layer in a pattern shape on the first semiconductor layer, and forms a second semiconductor layer on the first semiconductor layer and on the metallic material layer. And forming a cavity in the first semiconductor layer below the metallic material layer, wherein the cavity is formed by the first semiconductor layer below the metallic material layer and the metallic material layer. Reacting to form the first semiconductor layer is etched, and after forming the second semiconductor layer, heating the substrate to grow the cavity in the first semiconductor layer.

The substrate can be easily peeled from the second semiconductor layer by the growth of the cavity.

The metallic material layer is formed on the first semiconductor layer in a stripe shape at regular intervals and widths, and the second semiconductor layer is formed to a thickness covering the metallic material layer.

It is preferable that a part of the metallic material layer is formed of an oxide film, and the oxide film forms a mask for the first semiconductor layer.

The metallic material layer may be formed to a thickness in which a plurality of holes are formed in the process of forming the second semiconductor layer.

The metallic material layer is formed by using a metallic material having a higher melting point than the heating temperature when the second semiconductor layer is formed.

In addition, a part of the metallic material layer is formed of an oxide film, and the oxide film forms a mask for the first semiconductor layer and forms a plurality of holes in the process of forming the second semiconductor layer. And forming the second semiconductor layer using an organometallic vapor phase growth method, reacting the first semiconductor layer below the portion where the metallic material layer is formed with the metallic material layer and nitrogen to form a plurality of the plurality of semiconductor layers. Evaporation from the pores can form the cavity.

The metallic material layer is tantalum, the film thickness is in the range of 5 nm to 100 nm, and the surface of the tantalum on the first semiconductor layer may include tantalum and tantalum oxide.

In addition, the substrate may be a sapphire substrate or a silicon-based substrate.

Meanwhile, the heating of the substrate may be performed so that the substrate temperature is 300 ° C. or higher, and preferably, the substrate temperature may be 900˜1100 ° C. FIG.

The metallic material layer may be formed of a metal selected from the group consisting of Ta, Ni, Cr, Pt, and Mo, or an alloy thereof.

According to one embodiment of the present invention, a light emitting device manufacturing method is provided. The method comprises forming a first semiconductor layer on a first substrate, forming a metallic material layer in a pattern shape on the first semiconductor layer, and forming a second semiconductor on the first semiconductor layer and the metallic material layer. While forming a layer, a cavity is formed in the first semiconductor layer below the metallic material layer, a first compound semiconductor layer is formed on the second semiconductor layer, and the first compound semiconductor is formed. Forming an active layer on the layer, forming a second compound semiconductor layer on the active layer, attaching a second substrate on the second compound semiconductor layer, and heating the first substrate to The cavity is grown, wherein the cavity is formed by reacting the metallic material layer with the first semiconductor layer below the metallic material layer to etch the first semiconductor layer. The. The substrate can be easily peeled from the second semiconductor layer by the growth of the cavity.

The metallic material layer is formed on the first semiconductor layer in a stripe shape at regular intervals and widths, and the second semiconductor layer is formed to a thickness covering the metallic material layer.

It is preferable that a part of the metallic material layer is formed of an oxide film, and the oxide film forms a mask for the first semiconductor layer.

The metallic material layer may be formed to a thickness in which a plurality of holes are formed in the process of forming the second semiconductor layer.

The metallic material layer is formed by using a metallic material having a higher melting point than the heating temperature when the second semiconductor layer is formed.

In addition, a part of the metallic material layer is formed of an oxide film, and the oxide film forms a mask for the first semiconductor layer, and forms a plurality of holes in the process of forming the second semiconductor layer. And forming the second semiconductor layer by an organometallic vapor phase growth method, reacting the first semiconductor layer below the portion where the metallic material layer is formed with the metallic material layer and nitrogen to form the plurality of holes. Can be evaporated from to form the cavity.

The metallic material layer is tantalum, the film thickness is in the range of 5 nm to 100 nm, and after formation on the first semiconductor layer, the surface of the tantalum on the first semiconductor layer may include tantalum and tantalum oxide. Can be.

In addition, the first substrate may be a sapphire substrate or a silicon-based substrate.

Meanwhile, the heating of the first substrate may be performed so that the temperature of the first substrate is 300 ° C. or more, and preferably, the substrate temperature may be 900˜1100 ° C. FIG.

The metallic material layer may be formed of Ta, Ni, Cr, Pt, or Mo, or an alloy thereof.

In addition, heating the first substrate may be performed while attaching the second substrate.

According to the present invention, the substrate can be easily removed by forming a cavity between the growth substrate and the semiconductor layer formed thereon and growing the cavity. Therefore, growth substrates such as sapphire can be removed without using a laser, and semiconductor substrates such as GaN substrates and light emitting devices can be manufactured at low cost. In addition, it is possible to grow the cavity by heating in a process such as secondary substrate bonding, it is possible to peel the growth substrate without additional process for removing the growth substrate can simplify the light emitting device manufacturing process.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in detail based on attached drawing. In addition, embodiment described below is only one form of this invention, respectively, and this invention is not limited to this embodiment.

(Embodiment 1)

FIG. 1: is a figure which shows the outline of the manufacturing method of the semiconductor substrate 100 which concerns on Embodiment 1. As shown in FIG. 1A is a cross-sectional view showing a step of forming a first GaN layer, (B) is a cross-sectional view showing a step of forming a Ta layer, and (C) shows a middle of the formation of a second GaN layer and a cavity. Sectional drawing (D) is sectional drawing of a completed semiconductor substrate.

In FIG. 1A, 101 is a sapphire (Al ₂ O ₃ ) substrate as a growth substrate. First, a first GaN layer 102 having a thickness of about 2 μm is formed on the sapphire substrate 101. The thickness of this first GaN layer is an example and is not limited.

Next, in FIG. 1B, a Ta layer (metallic material layer) 103 having a thickness of about 50 nm is formed into a stripe shape by using EB (Electron Beam) deposition and lift-off on the first GaN layer 102. It is formed at intervals of 5 m and 5 m. The shape, thickness, width, and spacing of this Ta layer 103 are examples and are not limited.

Next, in FIG. 1C, the second GaN layer 104 is formed on the first GaN layer 102 and the Ta layer 103 by using an organometallic gas phase growth method (hereinafter referred to as MOCVD method). To form. FIG. 1C shows a state in which the second GaN layer 104 is formed. In this case, N and Ta of the GaN layer combine to form TaN, which becomes a different material, and the N rises in a darker gas phase. TaN becomes unstable at 900 degreeC or more, vaporizes at 1000 degreeC or more, and a hole deepens with the vaporization, and the cavity 102a is formed. N of GaN becomes TaN, but Ga remains. Since Ga is the same as Ga deposited during gas phase growth, it is used as a raw material. However, there is an example in which GaN is grown on a Ta film. In the non-patent document 1, the surface of the Ta layer 103 is not only Ta but, as will be described later, it has been found that the surface of the Ta layer 103 may be Ta ₂ O ₅ by being treated in air.

On the other hand, the second GaN layer 104 may be formed at 1/2 times or more than the Ta layer 103, and may be formed to be less than 1000 μm for use as a substrate.

Next, in FIG. 1D, the formation of the second GaN layer 104 is completed to complete the semiconductor substrate 100. When the formation of the second GaN layer 104 is advanced by the MOCVD method, as shown in the figure, etching of the first GaN layer 102 under the Ta layer 103 proceeds and the cavity 102a is carried out. The formation region of is also enlarged almost on the sapphire substrate 101. In addition, since the growth of the first GaN layer 102 also proceeds with the growth of the second GaN layer 104, the substrate surface is planarized as shown in FIG. 1. For this reason, in the semiconductor substrate 100 of the first embodiment, it is possible to omit the step of planarizing the substrate surface.

Next, in FIG. 1E, the sapphire substrate 101 is peeled off. Subsequently, in FIG. 1F, the GaN substrate 100 can be obtained by polishing the peeled first GaN layer 102. In the drawing of this GaN substrate 100, a silicon-based substrate such as Si or SiC is attached to the surface side, and the bottom surface side may be flattened to form a semiconductor substrate for device manufacturing. In the case where the sapphire substrate 101 is peeled off, it is possible to use the cavity 102a formed in the first GaN layer 102. The sapphire substrate 101 is performed by heating the substrate 101 to grow the cavity 102a after the formation of the second GaN layer 104 is completed. Subsequent heating causes the cavity 102a to grow, thereby weakening the bond between the second GaN layer 104 and the sapphire substrate 101. Therefore, the sapphire substrate 101 may naturally be peeled from the second GaN layer 104 by the growth of the cavity 102a, or after the growth of the cavity 102a has progressed to some extent, the sapphire substrate 101 It can be peeled off by applying a physical force to it.

The sapphire substrate 101 may be heated to a temperature of 300 ℃ or more, for example, may be heated in the range of 900 ~ 1100 ℃. The sapphire substrate 101 may be heated while attaching a silicon-based substrate such as Si or SiC to the surface side of the GaN substrate 100.

As mentioned above, by forming the semiconductor substrate 100 which has a GaN layer using MOCVD method, it becomes easy to peel the 1st GaN layer 102 from the sapphire substrate 101 using the cavity 102a, The peeled GaN layer can be used as a GaN substrate. Therefore, it becomes possible to manufacture a GaN substrate at a lower cost than a conventional GaN substrate.

(Example 1)

Next, the specific example of the manufacturing method of the said semiconductor substrate 100 is demonstrated below. In the first embodiment, a process of forming the second GaN layer 104 using the MOCVD apparatus will be described. An example in which the growth temperature is set to 1045 ° C. and crystal growth is performed for 5 hours while flowing TMGa at a flow rate of 20 μmol / min using trimethyl gallium (hereinafter referred to as TMGa) as the source gas. In the first embodiment, a Ta layer 103 having a thickness of 50 nm is formed on the first GaN layer 102 in a stripe shape.

The semiconductor substrate 100 which completed formation of the 2nd GaN layer 104 by the said conditions is shown in FIG. 2 is a SEM cross-sectional photograph of a portion of the semiconductor substrate 100. As is apparent from this figure, a cavity 102a is formed in the first GaN layer 102 under the formation region of the Ta layer 103. FIG. 3 shows the results of analysis using an energy dispersive X-ray spectrometer (hereinafter referred to as EDX) for the enlarged region shown in the figure including the cavity 102a.

As shown in the spectral diagram by EDX in FIG. 3, GaN of the first GaN layer 102 and Al and O of the sapphire substrate 101 were observed, and Ta was hardly observed. 4 (B) to (D) As shown in the EDX diagram, Ga of the first GaN layer 102 and Al and O of the sapphire substrate 101 were observed, but Ta was not observed.

In Example 1, it was observed that the holes 103a were formed in the Ta layer 103 during the formation of the second GaN layer 104. The analysis result of the hole 103a formed in this Ta layer 103 is further demonstrated in FIG. 5 and FIG. In addition, the analysis result shown in FIG. 5 and FIG. 6 is the result of analyzing by EDX, stopping the formation process of the 2nd GaN layer 104 using the above-mentioned MOCVD apparatus in the middle.

In FIG. 5, (A) is a SEM cross-sectional photograph of the semiconductor substrate 100, (B) is a SEM surface photograph of the semiconductor substrate 100. In FIG. In FIG. 6, (A) is an EDX diagram of Ga obtained by EDX analysis from the surface of the semiconductor substrate 100 of FIG. 5B, and (B) is from the surface of the semiconductor substrate 100 of FIG. 5B. EDX The EDX of Ta analyzed.

In the SEM cross-sectional photograph of the semiconductor substrate 100 shown in FIG. 5A, it was observed that the first GaN layer 102 under the Ta layer 103 was etched to form a cavity 102a. In the SEM surface photograph of the semiconductor substrate 100 shown in FIG. (B), it was observed that the hole 103a was formed in the surface of the Ta layer 103. In addition, the result of having analyzed the surface of the Ta layer 103 containing this hole 103a about Ga and Ta by EDX method is shown to FIG. 6 (A) and (B). This EDX diagram proved that the Ta layer 103 remained and Ga and GaN were thinly grown on the Ta layer 103.

As described above, in the semiconductor substrate 100 according to the first embodiment, the conditions for forming the second GaN layer 104 are adjusted by using the MOCVD apparatus, and the Ta layer is used in the first GaN layer 102. It was possible to form the cavity 102a by etching. Therefore, when forming the second GaN layer 104 shown in Embodiment 1 described above, the cavity 102a by etching in the first GaN layer 102 with the growth of the first GaN layer 102. It became possible to form That is, it is possible to form the cavity 102a in the first GaN layer 102 by forming a metallic material layer on the first GaN layer 102 that generates the etching effect as described above. It turned out.

In addition, the setting conditions of the MOCVD apparatus shown in the said Example 1 are an example, What is necessary is just the conditions which can advance the growth of 1st GaN layer mentioned above, and formation of the cavity 102a simultaneously. However, in the growth process of the second GaN layer 104, the growth rate of the first GaN layer 102 is slow compared to the growth rate of the second GaN layer 104, so that in the first embodiment, The setting conditions of the MOCVD apparatus were adjusted in accordance with the growth rate of the first GaN layer 102.

In the first embodiment, although the hole 103a is formed in the Ta layer 103 during the growth process of the second GaN layer 104, for example, the Ta layer 103 is formed. In forming, the Ta layer 103 may be formed using a pattern mask having holes formed in advance. In addition, the shape of the Ta layer 103 is not limited to the above-mentioned stripe shape, and the shape may be changed according to the structure of the element formed on the semiconductor substrate 100, or the like. Examples of the device using the semiconductor substrate 100 will be described later.

In the semiconductor substrate 100 shown in the first embodiment, after the GaN substrate is peeled off, the GaN layer of the sapphire substrate 101 is flattened by RIE or the like to form a GaN layer having the above-mentioned cavity. It can be used again as the substrate 101. Therefore, it is possible to further reduce the manufacturing cost of the GaN substrate.

In addition, although the sapphire substrate was used as a growth substrate in the first embodiment, the substrate is not particularly limited as long as it is a substrate capable of growing a GaN layer such as a silicon-based substrate.

(Example 2)

In the second embodiment, a process of forming the second GaN layer 104 using the MOCVD apparatus will be described. An example of performing crystal growth for 5 hours by setting the heating temperature to 1045 ° C. while flowing TMGa at a flow rate of 20 μmol / min using TMGa as the source gas. In the second embodiment, a Ta layer 103 having a thickness of 30 nm is formed on the first GaN layer 102 in a stripe shape.

12 shows a semiconductor substrate 100 in which formation of the second GaN layer 104 is completed under the above conditions. 12 is a SEM cross-sectional photograph of a portion of the semiconductor substrate 100. As is apparent from this figure, a cavity 102a is formed in a part of the first GaN layer 102 below the formation region of the Ta layer 103. In Example 2, holes 103a were formed in the Ta layer 103 in the process of forming the second GaN layer 104.

In the semiconductor substrate 100 according to the second embodiment, the conditions for forming the second GaN layer 104 are adjusted using the MOCVD apparatus, and the etching is performed in the first GaN layer 102 using the Ta layer 103. It was made possible to form the cavity 102a by. Therefore, when forming the second GaN layer 104 shown in the above-described Embodiment 1, the cavity 102a by etching in the first GaN layer 102 together with the growth of the first GaN layer 102. ) Can be formed. That is, by forming a metallic material layer on the first GaN layer 102 that generates the etching effect as described above, the cavity 102a can be formed in the first GaN layer 102. It turned out.

In the cross-sectional view shown in FIG. 12, the cavity 102a is formed by etching in the first GaN layer 102 located below the left and right ends of each Ta layer 103, not directly below the Ta layer 103. Is formed. This indicates that etching in the first GaN layer 102 proceeds from both left and right ends of each Ta layer 103.

In addition, the setting conditions of the MOCVD apparatus shown in the said Example 2 are an example, What is necessary is just the conditions which can advance the growth of the above-mentioned 1st GaN layer, and formation of the cavity 102a simultaneously. However, in the growth process of the second GaN layer 104, the growth rate of the first GaN layer 102 is slow compared to the growth rate of the second GaN layer 104, so in the second embodiment, The setting conditions of the MOCVD apparatus were adjusted in accordance with the growth rate of the first GaN layer 102.

In Example 2, although the hole 103a is formed in the Ta layer 103 during the growth process of the second GaN layer 104, for example, the Ta layer 103 is formed. In forming, the Ta layer 103 may be formed using a pattern mask having holes formed in advance. In addition, the shape of the Ta layer 103 is not limited to the above-mentioned stripe shape, and the shape may be changed according to the structure of the element formed on the semiconductor substrate 100, or the like. Examples of the device using the semiconductor substrate 100 will be described later.

In the semiconductor substrate 100 shown in the first embodiment, after the GaN substrate is peeled off, the GaN layer having the above-mentioned cavity is formed when the surface on which the GaN is formed on the sapphire substrate 101 is made flat by RIE or the like. It can be used again as the board | substrate 101 to make. Therefore, it is possible to further reduce the manufacturing cost of the GaN substrate.

(Example 3)

In the third embodiment, a process of forming the second GaN layer 104 using the MOCVD apparatus will be described. An example of performing crystal growth for 5 hours by setting heating temperature to 1045 ° C. while flowing TMGa at a flow rate of 20 μmol / min using TMGa as the source gas is shown. On the first GaN layer 102, in Example 3, A Ta layer 103 having a thickness of 50 nm is formed in a stripe shape.

13 shows a semiconductor substrate 100 in which formation of the second GaN layer 104 is completed under the above conditions. 13 is a SEM cross-sectional photograph of a portion of the semiconductor substrate 100. As is apparent from this figure, a cavity 102a is formed in the first GaN layer 102 under the formation region of the Ta layer 103. In Example 3, holes 103a were formed in the Ta layer 103 during the formation of the second GaN layer 104.

In the semiconductor substrate 100 according to the third embodiment, the conditions for forming the second GaN layer 104 are adjusted using the MOCVD apparatus, and the etching is performed in the first GaN layer 102 using the Ta layer 103. It was made possible to form the cavity 102a by. Therefore, when forming the second GaN layer 104 shown in Embodiment 1 mentioned above, the cavity 102a by etching in the first GaN layer 102 is accompanied with the growth of the first GaN layer 102. It became possible to form That is, by forming a metallic material layer on the first GaN layer 102 that generates the etching effect as described above, the cavity 102a can be formed in the first GaN layer 102. It turned out.

In addition, the setting conditions of the MOCVD apparatus shown in the said Example 3 are an example, What is necessary is just the conditions which can advance the growth of the above-mentioned 1st GaN layer, and formation of the cavity 102a simultaneously. However, in the growth process of the second GaN layer 104, the growth rate of the first GaN layer 102 is slow compared to the growth rate of the second GaN layer 104, so in the third embodiment, The setting conditions of the MOCVD apparatus were adjusted in accordance with the growth rate of the first GaN layer 102.

In the third embodiment, although the hole 103a is formed in the Ta layer 103 during the growth of the second GaN layer 104, for example, the Ta layer 103 is formed. In forming, the Ta layer 103 may be formed using a pattern mask having holes formed in advance. In addition, the shape of the Ta layer 103 is not limited to the above-mentioned stripe shape, and the shape may be changed according to the structure of the element formed on the semiconductor substrate 100, or the like. Examples of the device using the semiconductor substrate 100 will be described later.

(Example 4)

In the fourth embodiment, a process of forming the second GaN layer 104 using the MOCVD apparatus will be described. An example of performing crystal growth for 5 hours by setting the heating temperature to 1045 ° C. while flowing TMGa at a flow rate of 20 μmol / min using TMGa as the source gas. In the fourth embodiment, a Ta layer 103 having a thickness of 100 nm is formed on the first GaN layer 102 in a stripe shape.

14 shows a semiconductor substrate 100 in which formation of the second GaN layer 104 is completed under the above conditions. 14 is a SEM cross-sectional photograph of a portion of the semiconductor substrate 100. As is apparent from this figure, a cavity 102a is formed in the first GaN layer 102 under the formation region of the Ta layer 103. In the fourth embodiment, it was observed that holes 103a were formed in the Ta layer 103 during the formation of the second GaN layer 104.

In the semiconductor substrate 100 according to the fourth embodiment, the conditions for forming the second GaN layer 104 are adjusted using the MOCVD apparatus, and the etching is performed in the first GaN layer 102 using the Ta layer 103. It was made possible to form the cavity 102a by. Therefore, when forming the second GaN layer 104 shown in Embodiment 1 described above, the cavity 102a by etching in the first GaN layer 102 with the growth of the first GaN layer 102. ) Can be formed. That is, by forming a metallic material layer on the first GaN layer 102 that generates the etching effect as described above, the cavity 102a can be formed in the first GaN layer 102. It turned out.

In addition, the setting conditions of the MOCVD apparatus shown in the said Example 4 are an example, What is necessary is just the conditions which can advance the growth of the above-mentioned 1st GaN layer, and formation of the cavity 102a simultaneously. However, in the growth process of the second GaN layer 104, the growth rate of the first GaN layer 102 is slower than the growth rate of the second GaN layer 104, so that in the fourth embodiment, The setting conditions of the MOCVD apparatus were adjusted in accordance with the growth rate of the first GaN layer 102.

In the fourth embodiment, the hole 103a is formed in the Ta layer 103 during the growth of the second GaN layer 104. However, for example, the Ta layer 103 is formed. In forming, the Ta layer 103 may be formed using a pattern mask having holes formed in advance. In addition, the shape of the Ta layer 103 is not limited to the above-mentioned stripe shape, and the shape may be changed according to the structure of the element formed on the semiconductor substrate 100, or the like. Examples of the device using the semiconductor substrate 100 will be described later.

(Comparative Example 1)

Next, the comparative example with respect to Example 1 mentioned above is demonstrated. In this comparative example, a specific example of forming the second GaN layer 104 of the semiconductor substrate 100 by changing the setting conditions of the MOCVD apparatus will be described.

In Comparative Example 1, the heating temperature was set to 1045 ° C. while TMGa was flowed at 87 μmol / min using TMGa as the source gas, and crystal growth was performed for 5 hours.

The semiconductor substrate 100 which completed formation of the 2nd GaN layer 104 by the said conditions is shown. 7 is shown. In FIG. 7, (A) is a SEM cross-sectional photograph of a part of the semiconductor substrate 100, (B) is a SEM surface photograph which partially enlarged the surface of (A). As is apparent from this figure, a granular material is deposited on the surface of the second GaN layer 104, and the cavity is formed in the first GaN layer 102 under the formation region of the Ta layer 103. 102a) is formed. The granular material was found to be Ga particles, N particles, and Ta particles by the following EDX analysis and CL analysis.

The result of EDX analysis of the surface of the said particulate matter is shown in FIG. In FIG. 8, (A) is the spectral diagram which EDX analyzed the granular material of FIG. 7 (B), (B) is the EDX diagram of Ga which EDX analyzed the granular material of FIG. 7 (B), (C) is It is EDX diagram of N which EDX analyzed the granular material of FIG. Ga and N and some Ta were observed as shown in the spectral diagram of FIG. 8 (A), and Pa and N were observed as shown in the EDX diagram of FIGS. 8 (B) and (C).

Moreover, the result of EDX analysis of the cross section of a granular material is shown to FIG. 9 and FIG. In FIG. 9, (A) is the SEM cross-sectional photograph which enlarged the void part as a granular material of FIG. In FIG. 10, (A) is the EDX figure of Ga which EDX analyzed the cross section of FIG. 9 (A), (B) is the EDX figure of N which EDX analyzed the cross section of FIG. 9 (A), (C) is It is EDX figure of Ta which EDX analyzed the cross section of FIG. 9 (A).

As shown in the spectral diagram of FIG. 9B, Ga and N of the second GaN layer 104 and the particulate matter, Ta of the Ta layer 103, and Al and O of the sapphire substrate 101 were observed. Moreover, as shown to FIG. 10 (A)-(C), Ga, N, Ta was observed in the void part.

From the above observation results, it was found that the granular material deposited on the surface of the second GaN layer 104 was Ga particles, N particles, and Ta particles. That is, in Comparative Example 1, it was found that Ga in the etched portion of the first GaN layer 103 was broken with N, GaO reaction and gasification were lost, and Ga particles, N particles, and Ta particles were precipitated. It became.

As described above, in the setting conditions of the MOCVD apparatus of Comparative Example 1, since the flow rate of TMGa was set to 87 μmol / min more than that of Example 1, it was found that the above-mentioned granular material precipitated on the substrate and was not usable as the substrate. It became. Therefore, it turned out that the preferable flow volume X of TMGa which a granular material does not precipitate on a board | substrate is the range of X <87 micromol / min.

(About Ta ₂ O ₅ formation of Ta layer)

In Examples 1 to 4, an example of changing the thickness of the Ta layer 103 to 30 nm, 50 nm, and 100 nm is shown. Thus, even if the thickness of the Ta layer 103 is changed, it can be confirmed that the cavity 102a is formed in the 1st GaN layer 104 by etching.

The Ta layer 103 schematically shows in FIG. 15 that a region where Ta ₂ O ₅ is generated varies with its thickness. 15 (A) shows an example in which the Ta layer 103 having a thickness of 5 nm is changed to Ta ₂ O ₅ , and FIG. 15 (B) shows that the surface of the Ta layer 103 having a thickness of 100 nm has Ta ₂ O. FIG. _The example which changed to ₅ is shown. After the Ta layer 103 is deposited on the surface of the first GaN layer 102 by the EB deposition apparatus, the Ta layer 103 is exposed to the atmosphere during the transfer to the MOCVD apparatus. In the meantime, it was found that Ta and oxygen reacted to change the Ta layer 103 into Ta ₂ O ₅ . For this reason, a thickness of 15 Ta layer 103 is Ta layer 103 as shown in, Figure 15, and the total change in Ta ₂ O ₅ (B), when a thickness of 5nm in that appears in (A) in 100nm If it was found that the surface is changed to Ta ₂ O _5. That is, Ta is in contact with air at room temperature, produces the Ta ₂ O _5. 15A schematically shows an example in which a Ta film having a thickness of 5 nm grows in the transverse direction on the GaN layer. 16 shows an example in which Ta ₂ O ₅ having a thickness of 10 nm is actually grown in the transverse direction on the substrate. In both cases, growth is progressing without etching the GaN layer under the Ta film. That is, when a substrate on which a Ta film having a thickness of 5 nm was formed was transferred to the MOCVD apparatus in air, 5 nm Ta ₂ O ₅ was formed in FIG. 15 (A). Ta ₂ O ₅ is a very good transverse growth mask. On the other hand, when Ta of 100 nm in thickness shown in Fig. 15B is formed, the circumstances are different. When Ta is formed by EB vapor deposition, since Ta of a raw material is mounted in air, a thin oxide film is deposited on Ta surface. Further deposition of this leads to Ta ₂ O ₅ at first, but this state gradually decreases to the deposition of Ta metal. Therefore, the thickness of the GaN layer of Ta ₂ O ₅ is 5nm or less Ta, and is partially contained in the Ta portion. The upper layer from this Ta ₂ O ₅ film is Ta. Then, the Ta ₂ O ₅ film is thinly formed on the surface of the Ta layer by transferring the substrate after Ta layer formation to the MOCVD apparatus in air. As a result, the surface of the Ta layer is thinly wrapped with a Ta ₂ O ₅ film. Among these Ta layers, the Ta ₂ O ₅ film on the GaN layer becomes a layer in which Ta is partially mixed. This state is shown typically in FIG.15 (B). N in the GaN layer and Ta in the Ta layer combine to form TaN. However, since Ga is the same as Ga deposited during gas phase growth, it is used as a raw material.

In the first to fourth embodiments, the Ta ₂ O ₅ region oxidized by the Ta layer 103 grows laterally with respect to the first GaN layer 104 to act as a very good etching mask. Therefore, the second embodiment, as in shown in Figure 12, GaN layer of a first to a thickness of the right and left end portions of the Ta layer 103 of 30nm are not forming a Ta ₂ O ₅ region, is located in the lower layer of the part ( It was found from 102 that the formation of the cavity 102a proceeded. Also in Embodiments 3 and 4 in which Ta layers 103 having thicknesses of 50 nm and 100 nm were formed, since Ta ₂ O ₅ regions were formed on the surface thereof, and acted as etching masks on the first GaN layer 104, Similarly, formation of the cavity 102a proceeds.

Therefore, the thickness of the Ta layer 103 is a region formed of Ta ₂ O ₅ acts as an etching mask, in Examples 1 to Embodiment 4 may be a 20nm ~ 100nm, as shown in. In addition, in FIG. 16 (A) which shows an example in which a Ta mask having a thickness of 5 nm is formed on the first GaN layer, no cavity is formed under the Ta mask. Further, in the Ta ₂ O 16 an illustrative example only and forming a mask ₅ (B), it was confirmed that the Ta ₂ O ₅ capable of forming a mask on the GaN layer, and InGaAlN. Therefore, since the Ta ₂ O ₅ mask is formed regardless of the thickness of the Ta layer 103, as shown in the above Examples 1 to 4, the first GaN layer (located under the Ta ₂ O ₅ mask) ( It is possible to advance the formation of the cavity 102a in the 102.

(Embodiment 2)

Next, the case where LED is formed as an example of the semiconductor element formed on the semiconductor substrate 100 shown in the said Embodiment 1 is demonstrated with reference to FIG.

11 is a partial cross-sectional view for illustrating the LED according to the second embodiment.

In FIG. 11, a plurality of LEDs 200 are separated from each other on the semiconductor substrate 100. Each LED 200 has a lower semiconductor layer 201 made of a first conductivity type compound semiconductor layer, and an active layer 202 and an upper semiconductor layer 203 made of a second conductivity type compound semiconductor layer. The active layer 202 may have a single or multiple quantum well structure having a layer and a barrier layer, and its material and composition are selected by the required emission wavelength. For example, the active layer 202 may be formed of a gallium nitride compound semiconductor. The lower and upper semiconductor layers 201 and 203 may be formed of a material having a larger band gap than the active layer 202, and may be formed of a gallium nitride compound semiconductor.

In this case, the lower semiconductor layer 201 formed on the semiconductor substrate 100 is formed on the second GaN layer 104. Therefore, the manufacturing cost can be reduced by manufacturing the LED 200 using the semiconductor substrate 100.

The upper semiconductor layer 203 is located above a portion of the lower semiconductor layer 201, and the active layer 202 is interposed between the upper semiconductor layer 203 and the lower semiconductor layer 201. In addition, the upper electrode layer 204 may be formed on the upper semiconductor layer 203. The upper electrode layer 204 may be formed of a transparent electrode layer, for example, an indium tin oxide film (ITO) or a material such as Ni / Au.

In addition, the upper electrode pad 205 is formed on the upper electrode layer 204, and the lower electrode 207 is formed in the region where the lower semiconductor layer 201 is exposed.

In this manner, after the plurality of LEDs 200 are formed on the single semiconductor substrate 100, the LEDs 200 can be separated into individual LEDs 200 by cutting at the cutting positions shown in the drawing. Like this LED 200, not only the upper electrode 205 and the lower electrode pad 207 are arrange | positioned horizontally, LED which arrange | positioned each electrode vertically can also be manufactured. That is, the sapphire substrate 101 is peeled off using the cavity 102a of the semiconductor substrate 100, and the lower electrode is formed by planarizing the peeling surface of the first GaN layer 102 by RIE or the like. It is possible to manufacture LEDs of vertical structure.

As described above, by manufacturing the plurality of LEDs 200 on the semiconductor substrate 100, the manufacturing cost of the LEDs can be reduced. In addition, when forming the LED 200 on the second GaN layer 104, by forming a compound semiconductor in which the refractive indexes of the second GaN layer 104 and the lower semiconductor layer 201 are different from each other, It is possible to improve the luminous efficiency and to configure a high brightness LED array. In addition, when the laser diode is formed using the semiconductor substrate 100, since it is formed on the GaN layer having better thermal conductivity than the sapphire substrate 101, the heat dissipation characteristics can be improved and the laser diode can be extended in life.

In the second embodiment, the LED 200 is formed on the second GaN layer of the semiconductor substrate 100, but the LED 200 is similarly used using the GaN substrate separated from the sapphire substrate 101. You may form.

Therefore, by forming semiconductor elements such as LEDs and laser diodes using the semiconductor substrate 100, it is possible to easily manufacture high-performance light emitting elements at low cost without using expensive GaN substrates.

(Embodiment 3)

Next, the light emitting element manufacturing method using growth substrate peeling is demonstrated with reference to FIG.

17 is a cross-sectional view illustrating a method of manufacturing a light emitting device according to the third embodiment.

In FIG. 17A, as described with reference to FIGS. 1A to 1D, the first GaN layer 102 is grown on the sapphire substrate 101 as a first substrate, and the first GaN layer is grown. Ta layer 103 is formed on 102 to form a pattern such as a stripe. Subsequently, a second GaN layer 104 is formed on the first GaN layer 102 and the Ta layer 103, and a cavity 102a is formed in the first GaN layer 102. The cavity 102a may be formed from the Ta layer 103 to the sapphire substrate 101, but is not limited thereto. The cavity 102a may be formed to be limited to a partial thickness of the first GaN layer 102 from the Ta layer 103. Can be. The size of the cavity 102a may be controlled by, for example, growth temperature, growth time, etc. of the first and second GaN layers 102 and 104. In addition, a hole 103a may be formed in the Ta layer 103 while the second GaN layer 104 is formed, and the hole 103a is previously formed through patterning before forming the second GaN layer 104. It may be formed.

In FIG. 17B, a first conductivity type compound semiconductor layer 301 is formed on the second GaN layer 104, and an active layer 302 is formed on the first conductivity type compound semiconductor layer. A second conductive compound semiconductor layer 303 is formed on the active layer.

The first conductive compound semiconductor layer, the active layer, and the second conductive compound semiconductor layer may be gallium nitride-based compound semiconductors, and may be formed using an organometallic vapor phase growth method. The active layer 302 may be formed in a single or multiple quantum well structure, and its material and composition are selected by the required emission wavelength. The first and second conductivity type compound semiconductor layers 301 and 303 are formed of a material having a larger band gap than the active layer 202.

While growing the first conductivity type compound semiconductor layer 301, the active layer 302, and the second conductivity type compound semiconductor layer 303, the size of the cavity 102a is also increased.

Thereafter, a second substrate 400 is attached onto the second conductive compound semiconductor layer 303. The second substrate 400 may be a metal having good thermal conductivity or a silicon-based substrate such as Si or SiC. The second substrate 400 may be attached onto the second conductive compound semiconductor layer in various ways, for example, by using a bonding metal.

In FIG. 17C, the sapphire substrate 101 is heated to further grow the cavity 102a. As a result, neighboring cavities 102a meet each other and the sapphire substrate 101 is peeled off from the second GaN layer 104. The sapphire substrate 101 may be heated to a temperature of 300 ℃ or more, for example, may be heated in the range of 900 ~ 1100 ℃.

The heating of the sapphire substrate 101 may be performed while attaching the second substrate 400 to the second conductive compound semiconductor layer 303. Therefore, the sapphire substrate 101 can be easily separated without a separate process for separating the sapphire substrate 101.

In addition, although the neighboring cavities 102a meet each other and the sapphire substrate 101 is described as being peeled off, the neighboring cavities 102a may not meet each other by the heating. In this case, since the cavities 102a are sufficiently large in size, they can be easily peeled off by applying a physical force to the sapphire substrate 101. However, it is preferable that the lower end portion of the cavity 102a is grown to be in contact with at least the sapphire substrate 101 by the heating.

In FIG. 17D, after the sapphire substrate 101 is peeled off, the peeling surface is planarized by RIE or polishing. In this case, the second GaN layer 104 may be removed by polishing to expose the first conductivity-type semiconductor layer 301. Alternatively, when the second GaN layer 104 is of the first conductivity type, the second GaN layer 104 may be left.

In FIG. 17E, the lower electrode pad 401 is formed on the second substrate 400, and the upper electrode pad 402 is formed on the peeling surface side. Thereafter, the light emitting device having the vertical structure shown in Fig. 17E is completed by separating the light emitting devices into individual light emitting devices.

The first conductive semiconductor layer may be a gallium nitride-based n-type compound semiconductor, and the second conductive semiconductor layer may be a gallium nitride-based p-type compound semiconductor. Accordingly, a roughened surface may be formed on the release surface, for example, the surface of the first conductivity type semiconductor layer 301 by using a photochemical etching technique.

In the third embodiment, a method of manufacturing a light emitting device having a vertical structure has been described. However, as described in the second embodiment, after the sapphire substrate 101 is peeled off, the light emitting device having a horizontal structure is formed on the second substrate 400. It may be prepared.

In the present embodiment, the cavity 102a is formed while the first GaN layer 102, the second GaN layer 104, and the gallium nitride based compound semiconductor layers 301, 302, and 303 are formed thereon. Although the size of is increased, the sapphire substrate 101 must be securely attached to the second GaN layer 104 through the first GaN layer 102 until the second substrate 400 is attached. Accordingly, the size of the cavity 102a is controlled by adjusting the thickness, width, and growth conditions of the respective layers of the Ta layer 103.

As described above, after growing the gallium nitride-based compound semiconductor layers on a growth substrate such as sapphire, the growth substrate can be easily peeled off without using a laser, thereby reducing the manufacturing cost of the LED. In addition, it is not necessary to perform the sapphire polishing necessary for the laser lift off process, so that it is possible to reuse the sapphire substrate.

In the above embodiments, the use of Ta as the metallic material layer has been described. However, the present invention is not limited to this, and Ta, Pt, Ni, Cr or Mo may be used, or an alloy of these metals or an alloy such as a metal and a semiconductor may be used. It may be used and may be a metallic material that exerts an etching effect on the first GaN layer described above.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the manufacturing method of the semiconductor substrate which concerns on Embodiment 1 of this invention, (A) is sectional drawing which shows the process of forming a 1st GaN layer, (B) shows the process of forming a Ta layer. Sectional drawing, (C) is sectional drawing which shows the formation process of a 2nd GaN layer and a cavity, (D) is sectional drawing which shows completion of formation of a 2nd GaN layer, (E) is sectional drawing which peeled a sapphire substrate, (F ) Is a cross-sectional view of the completed GaN substrate.

2 is a SEM cross-sectional photograph of a semiconductor substrate according to Example 1. FIG.

3 is a spectral diagram of EDX according to Example 1. FIG.

4 is a SEM cross-sectional photograph of the enlarged region of FIG. 2, (B) is an EDX of Ga, (C) is an EDX of Al, and (D) is an EDX diagram of O.

5 is a SEM cross-sectional photograph of a semiconductor substrate, and (B) is a SEM surface photograph of a semiconductor substrate according to Example 1. FIG.

6 is an EDX diagram of the semiconductor substrate according to Example 1, (A) is an EDX diagram of Ga, and (B) is an EDX diagram of Ta.

7 is a SEM photographic image of a semiconductor substrate, and (B) is a SEM surface photograph of a semiconductor substrate according to Comparative Example 1. FIG.

8 is a spectral diagram of EDX of FIG. 7B, (B) is EDX diagram of Ga of FIG. 7B, and (C) is N of FIG. 7B. EDX is also.

9 is a SEM cross-sectional photograph of a void according to Comparative Example 1, and (B) is an EDX spectrum diagram of (A).

Fig. 10 is a diagram showing ED ED of Ga of Fig. 9A, (B) according to Comparative Example 1, Fig. 9B shows ED ED of N of Fig. 9A, and Fig. 9C shows Ta of Fig. 9A. EDX is also.

11 is a cross-sectional view showing the configuration of an LED array according to Embodiment 2 of the present invention.

12 is a SEM cross-sectional photograph of a semiconductor substrate according to Example 2. FIG.

13 is a SEM cross-sectional photograph of a semiconductor substrate according to Example 3. FIG.

14 is a SEM cross-sectional photograph of a semiconductor substrate according to Example 4. FIG.

Fig. 15 is a diagram schematically showing an example in which a Ta layer having a thickness of 5 nm is changed to Ta ₂ O ₅ , and (B) is a diagram schematically illustrating an example in which the surface of a Ta layer having a thickness of 100 nm is changed to Ta ₂ O ₅ . It is a figure shown normally.

Fig. 16 (A) is a SEM surface photograph of a substrate on which a Ta mask having a thickness of 5 nm is formed, and (B) is a SEM cross-sectional photograph of a substrate on which a Ta ₂ O ₅ mask having a thickness of 10 nm is formed.

17 is a cross-sectional view illustrating a method of manufacturing a light emitting device according to Embodiment 3 of the present invention.

Claims (20)

Forming a first semiconductor layer on the substrate, Forming a metallic material layer in a pattern shape on the first semiconductor layer, A second semiconductor layer is formed on the first semiconductor layer and the metallic material layer, and a cavity is formed in the first semiconductor layer below the metallic material layer. The cavity is formed by reacting the metallic material layer with the first semiconductor layer below the metallic material layer to etch the first semiconductor layer, After forming the second semiconductor layer, heating the substrate to grow the cavity in the first semiconductor layer. The method according to claim 1, The metallic material layer is formed on the first semiconductor layer in a stripe shape at regular intervals and widths, The second semiconductor layer covers the metallic material layer. The method according to claim 1, A portion of the metallic material layer is formed of an oxide film, and the oxide film forms a mask for the first semiconductor layer. The method of claim 3, The metal material layer is a method of manufacturing a semiconductor substrate, characterized in that formed in the thickness of the plurality of holes are formed in the process of forming the second semiconductor layer. The method according to claim 1, The metallic material layer is formed by using a metallic material having a higher melting point than the heating temperature at the time of forming the second semiconductor layer. The method according to claim 1, The metal material layer is partially formed of an oxide film, and the oxide film forms a mask for the first semiconductor layer and forms a plurality of holes in the process of forming the second semiconductor layer. , When the second semiconductor layer is formed using the organometallic vapor phase growth method, the first semiconductor layer below the portion where the metallic material layer is formed is reacted with the metallic material layer and nitrogen to evaporate from the plurality of holes. To form the cavity to form a semiconductor substrate. The method according to claim 1, The metallic material layer is tantalum, the film thickness is in the range of 5 nm to 100 nm, and the surface of the tantalum on the first semiconductor layer contains tantalum and tantalum oxide. . The method according to claim 1, The substrate is a semiconductor substrate manufacturing method, characterized in that the sapphire substrate or silicon substrate. The method according to claim 1, Heating the substrate is performed so that the substrate temperature is in the temperature range of 900 ~ 1100 ℃. The method according to claim 1, And the metallic material layer is formed of a metal selected from the group consisting of Ta, Ni, Cr, Pt, and Mo, or an alloy thereof. Forming a first semiconductor layer on the first substrate, Forming a metallic material layer in a pattern shape on the first semiconductor layer, A second semiconductor layer is formed on the first semiconductor layer and the metallic material layer, and a cavity is formed in the first semiconductor layer below the metallic material layer. Forming a first compound semiconductor layer on the second semiconductor layer, An active layer is formed on the first compound semiconductor layer, Forming a second compound semiconductor layer on the active layer, Attaching a second substrate on the second compound semiconductor layer, The first substrate is heated to grow the cavity in the first semiconductor layer, And the cavity is formed by reacting the metallic material layer with the first semiconductor layer in a lower portion than the metallic material layer and etching the first semiconductor layer. The method of claim 11, The metallic material layer is formed on the first semiconductor layer in a stripe shape at regular intervals and widths, The second semiconductor layer covers the metallic material layer. The method of claim 11, A portion of the metallic material layer is formed of an oxide film, and the oxide film forms a mask for the first semiconductor layer. 14. The method of claim 13, The metal material layer is a method of manufacturing a light emitting element, characterized in that formed in the thickness of the plurality of holes formed in the process of forming the second semiconductor layer. The method of claim 11, The metallic material layer is formed by using a metallic material having a higher melting point than the heating temperature at the time of forming the second semiconductor layer. The method of claim 11, A part of the metallic material layer is formed of an oxide film, the oxide film forms a mask for the first semiconductor layer, and forms a plurality of holes in the process of forming the second semiconductor layer, When the second semiconductor layer is formed using the organometallic vapor phase growth method, the first semiconductor layer below the portion where the metallic material layer is formed is reacted with the metallic material layer and nitrogen to evaporate from the plurality of holes. To form the cavity to form a light emitting device. The method of claim 11, The metallic material layer is tantalum, the film thickness is in the range of 5 nm to 100 nm, and after formation on the first semiconductor layer, the surface of the tantalum on the first semiconductor layer includes tantalum and tantalum oxide; The manufacturing method of the light emitting element characterized by the above-mentioned. The method of claim 11, The said 1st board | substrate is a sapphire substrate or a silicon type substrate, The manufacturing method of the light emitting element characterized by the above-mentioned. The method of claim 11, Heating the first substrate is performed so that the temperature of the first substrate is in the temperature range of 900 ~ 1100 ℃. The method of claim 11, Heating the first substrate is performed while attaching the second substrate.

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