KR101213727B1 - Method for manufacturing semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and to improve cell characteristics by suppressing generation of cell leakage current by making the depth of the gate formed in the device isolation layer and the gate formed in the active region the same in the buried fin gate. .
A method of manufacturing a semiconductor device according to the present invention includes forming a device isolation layer defining an active region on a semiconductor substrate, forming a first recess by etching an active region, and etching the device isolation layer to etch the first recess. Forming a second recess of the same depth as the source, further etching the second recess of the portion connected with the first recess to form a third recess, the first recess, the second recess and And embedding a conductive material in the third recess to form a buried fin gate.

Description

Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method for manufacturing a semiconductor device including a buried fin gate.

In general, a semiconductor is one of a class of materials according to electrical conductivity, and is a material belonging to an intermediate region between conductors and non-conductors. In a pure state, a semiconductor is similar to non-conductor, but the electrical conductivity is increased by the addition of impurities or other operations. Such a semiconductor is used to create a semiconductor device such as a transistor by adding impurities and connecting conductors. A device having various functions made using the semiconductor device is called a semiconductor device. A representative example of such a semiconductor device is a semiconductor memory device.

A semiconductor memory device includes a plurality of unit cells each composed of a capacitor and a transistor. The capacitor is used for temporarily storing data, and the transistor is connected to a control signal (word line) using the property of a semiconductor whose electric conductivity changes according to the environment. And is used to transfer data between the bit line and the capacitor correspondingly. A transistor is composed of three regions: a gate, a source, and a drain. Charge occurs between a source and a drain in accordance with a control signal input to the gate. The transfer of charge between the source and drain occurs through the channel region, which uses the nature of the semiconductor.

When conventional transistors are made in a semiconductor substrate, a gate is formed on the semiconductor substrate and doped with impurities on both sides of the gate to form a source and a drain. As the data storage capacity of the semiconductor memory device increases and the degree of integration increases, the size of each unit cell is required to be made smaller and smaller. That is, the design rules of the capacitors and transistors included in the unit cell have been reduced. As a result, the channel length of the cell transistors has gradually decreased, and thus, short channel effects and drain induced barrier lower (DIBL) effects have been applied to conventional transistors. Occurred, and the reliability of the operation was deteriorated. Phenomena that occur as the channel length decreases can be overcome by maintaining the threshold voltage so that the cell transistor can perform normal operation. Typically, the shorter the channel of the transistor, the higher the doping concentration of impurities in the region where the channel is formed.

However, as the design rule decreases below 100 nm, increasing the doping concentration in the channel region further increases the electric field at the storage node (SN) junction, which deteriorates the refresh characteristics of the semiconductor memory device. Cause. To overcome this problem, a cell transistor having a three-dimensional channel structure having a long channel length in the vertical direction is used to maintain the channel length of the cell transistor even if the design rule is reduced. That is, even if the channel width in the horizontal direction is short, the doping concentration can be reduced by securing the channel length in the vertical direction, thereby preventing the refresh characteristics from deteriorating. Hereinafter, a gate process having a three-dimensional channel structure is introduced.

A gate process having a three-dimensional channel structure includes a recess gate process for recessing an active region of a region where a gate is to be formed and forming a gate thereon, and recessing an isolation layer to fin an active region. A fin gate process that protrudes in a fin form and forms a gate thereon, a saddle gate, a buried gate process, and a fin gate process, in which a recess gate process and a fin gate process are mixed Mixed buried fin gate processes are used.

The use of metal gates in double buried fin gates makes them vulnerable to trap sites due to differences in the work functions of silicon and metal. In addition, when the potential of the buried fin gate is high as Vpp, band bending occurs due to an electric field between the buried fin gate and the well. This increases the probability that electrons are trapped at the trap site, which eventually traps the electron at the trap site.

When the potential of the buried fin gate is lowered to Vbbw, the band bending phenomenon is alleviated, and the probability of the presence of electrons in the trap site is also reduced. This causes the trapped electrons to be released at the trap site and out to the silicon substrate.

As such, there is a problem in that a cell leakage current of the metal gate occurs when a specific word line is periodically activated and precharged. In addition, as the cell leakage current occurs, the characteristics of the cell are degraded.

SUMMARY OF THE INVENTION The present invention is to solve the above-mentioned problems, and to suppress the occurrence of cell leakage current by making the depth of the gate formed in the device isolation layer and the depth of the gate formed in the active region the same in the buried fin gate.

A method of manufacturing a semiconductor device according to the present invention includes forming a device isolation film defining an active region on a semiconductor substrate, forming a first recess by etching an active region, and etching the device isolation film to etch the first recess. Forming a second recess of the same depth as the source, further etching the second recess of the portion connected with the first recess to form a third recess, the first recess, the second recess and And embedding a conductive material in the third recess to form a buried fin gate.

The forming of the first recess may include forming a first mask pattern defining a gate predetermined region on the semiconductor substrate, and etching the active region using the first mask pattern as an etch mask. It features.

The forming of the second recess may include etching the device isolation layer using the first mask pattern as an etch mask, and removing the first mask pattern.

Further, forming the third recess includes further etching the second recess at the interface of the first recess and the second recess.

The forming of the third recess may further include exposing an active region between the first recess and the first recesses, and a portion of the second recess connected to the first recess and an active region between the first recesses. Forming a second mask pattern exposing a portion of the adjacent device isolation layer, and further etching the bottom of the second recess exposed by the second mask pattern. After etching, the method may further include removing the second mask pattern.

Furthermore, before forming the gate, the method may further include forming a barrier metal layer on the first recess, the second recess, and the third recess, wherein the barrier metal layer includes a titanium nitride film. do.

In addition, the conductive material is characterized in that it comprises tungsten.

The method of manufacturing a semiconductor device of the present invention prevents cell leakage current by making the depth of the gate formed in the device isolation layer and the depth of the gate formed in the active region the same in the buried fin gate. This improves cell properties, providing the effect of improving product quality and yield.

1 to 8 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

In the present invention, to form a buried fin gate having the same recess depth of the active region and the recess depth of the device isolation region. Hereinafter, an embodiment of a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

1 to 8 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention. 1A, 7A and 8A show a top view, FIGS. 1B, 7B and 8B are cross-sectional views taken along the cutting plane of X1-X1 'of FIGS. 2A, 7A and 8A, respectively, and FIGS. 7C and 8C respectively And sectional drawing along the cutting plane of X2-X2 'of 8a. 7D and 8D are sectional views taken along the cutting plane of X3-X3 'of FIGS. 7A and 8A, respectively, and FIGS. 7E and 8E are sectional views taken along the cutting plane of Y-Y' of Figs. 7A and 8A, respectively.

First, referring to FIGS. 1A and 1B, a pad oxide film (not shown) and a pad nitride film 213 are formed on the semiconductor substrate 200, and a photoresist film (not shown) is formed on the pad nitride film. The pad oxide film (not shown) is formed to suppress the stress of the pad nitride film itself from being transferred to the semiconductor substrate 200. Then, the photoresist film (not shown) is subjected to an exposure and development process to form a photoresist pattern (not shown) defining an active region. Subsequently, the pad nitride layer, the pad oxide layer (not shown), and the semiconductor substrate 200 are etched using the photoresist pattern (not shown) as a mask to form a device isolation trench, a pad nitride layer pattern 213, and a pad oxide layer pattern (not shown). do.

Subsequently, a sidewall oxide film 203 is formed on the inner wall of the device isolation trench through an oxidation process. The sidewall oxide layer 203 is formed to mitigate lattice defects on the exposed surface of the semiconductor substrate 200 after trench formation.

Thereafter, an insulating material for device isolation is formed on the entire semiconductor substrate 200 including the device isolation trench in which the sidewall oxide layer 203 is formed. The isolation material for device isolation is formed of an oxide film. For example, High Density Plasma (HDP) may be used. Subsequently, a chemical mechanical polishing (CMP) process is performed until the pad nitride layer pattern 213 is exposed to form the device isolation layer 205 defining the active region 210. In this case, as shown in FIG. 2A, the active region 210 is formed in a bar shape, and is provided along the long axis direction and the short axis direction of the active area 210. In addition, adjacent active areas 210 are arranged to be offset from each other along a short axis direction of the active area 210.

Next, a first hard mask layer 215 and a second hard mask layer 217 are formed on the semiconductor substrate 200 including the pad nitride film pattern 213. The first hard mask layer 215 includes a silicon oxynitride layer, and the second hard mask layer 217 includes amorphous carbon. In addition, a first mask pattern 220 defining a gate region to be formed is formed on the second hard mask layer 217. As shown in FIG. 2A, the first mask pattern 220 may be formed in a line shape, and the first mask pattern 220 may be formed to expose two gate predetermined regions on one active region 210.

Next, referring to FIG. 2, the second hard mask layer 217 and the first hard mask layer 215 are etched using the first mask pattern 220 as an etching mask to form the first hard mask layer pattern 215a and the first mask. 2 hard mask layer pattern 217a is formed. In this case, the pad nitride layer pattern 213 formed on the device isolation layer 205 and the active region 210 is exposed by the first hard mask layer pattern 215a and the second hard mask layer pattern 217a.

3, the pad nitride layer pattern 213 is etched using the first mask pattern 220, the first hard mask layer pattern 215a, and the second hard mask layer pattern 217a as an etch mask. 210). In this case, the device isolation layer 205 may be partially etched while the pad nitride layer pattern 213 is etched.

Next, referring to FIG. 4, the active region 210 is etched using the first mask pattern 220, the first hard mask layer pattern 215a, and the second hard mask layer pattern 217a as an etch mask to form 'D1'. The first recesses 225a having the same depth are formed. In this case, the first recess 225a may be formed by using an etching solution in which only silicon is etched so that the oxide layer, which is the device isolation layer 205, is not etched, and only the active region 210, which is silicon, is etched.

Next, referring to FIG. 5, the device isolation layer 205 is etched using the first mask pattern 220, the first hard mask layer pattern 215a, and the second hard mask layer pattern 217a as an etch mask to form a second layer. A recess 225b is formed. In this case, the second recess 225b is preferably formed by adjusting the etching target to have the same depth D2 as the depth D1 of the first recess 225a. Here, in contrast to FIG. 5, the oxide layer, which is the device isolation layer 205, is etched using the etching solution in which only the oxide layer is etched, and the active region 210, which is silicon, is not etched. Here, the method of etching the active region 210 and the device isolation layer 205 is not limited to the method of etching the active region 210 and the device isolation layer 205 as shown in FIGS. 4 and 5, respectively. Can also be. As such, when the active region 210 and the device isolation layer 205 are simultaneously etched, it is preferable to proceed with the etching target by adjusting the etching rate.

Next, referring to FIG. 6, the first mask pattern 220, the first hard mask layer pattern 215a, and the second hard mask layer pattern 217a are removed. At this time, the pad nitride film pattern 213 is also removed.

Then, referring to Figure 7a to 7e as follows. For reference, 7a illustrates a plan view, and FIG. 7B is a cross-sectional view taken along a cutting plane of X1-X1 'of FIG. 7A, and FIG. 7C is a cross-sectional view taken along a cutting plane of X2-X2' of FIG. 7A. 7D is a cross-sectional view taken along the cutting plane of X3-X3 'of FIG. 7A, and FIG. 7E is a cross-sectional view taken along the cutting plane of Y-Y' of FIG. 7A.

First, a second mask pattern 230 is formed on the semiconductor substrate 200 including the first recess 225a and the second recess 225b. In this case, the second mask pattern 230 is formed as shown in FIG. 7A. A second region exposing the active region 210 between the first recess 225a and the first recess 225a and adjacent to the first recess 225a in the Y-Y 'direction (the long axis direction of the gate); In some embodiments, the active region 210 between the recess 225b and the first recess 225a and the portion of the isolation layer 205 adjacent to each other in the Y-Y 'direction (the long axis direction of the gate) may be exposed. .

Next, the second recess 225b exposed by the second mask pattern 230 is further etched to have a depth deeper than the depths D1 and D2 of the first recess 225a and the second recess 225b. A third recess 225c having a D3 is formed. In this way, a portion of the second recess 225b adjacent to the first recess 225a formed in the active region 210 is further etched to form a third recess 225c. That is, the third recess 225c is formed at the interface between the first recess 225a and the second recess 225b so that the active region 205 becomes a fin.

FIG. 7E shows a cut along the longitudinal direction (Y-Y 'direction of FIG. 7A) of a recess comprising a first recess 225a, a second recess 225b and a third recess 225c. This represents the step formed in the bottom of the recess. The active region 210 is etched from the substrate surface by a depth of 'D1', and the center portion of the device isolation layer 205 is etched by the depth of 'D2' from the substrate surface. Here, it is preferable to adjust the etching target so that D1 and D2 are the same. In addition, the device isolation layer 205 adjacent to the active region 210 is etched from the substrate surface by the depth of 'D3'. At this time, it is preferable that D3 is larger than D1 or D2. As such, the active region 210 is etched to a depth of 'D1', and the device isolation layer 205 adjacent to the active region 210 is etched to a depth of 'D3' to form a fin like 'A'. In addition, the device isolation layer 205 which is not in direct contact with the active region 210 is etched to the same depth D2 as the depth D1 where the active region 210 is etched. That is, only the minimum region of the device isolation layer 205 for the formation of the fin-type recess is deeply etched, and the other portions are formed at the same depth as the active region 210, so that the buried fin gate has a deep structure. The cell leakage current generated is improved.

Next, the following process will be described with reference to FIGS. 8A to 8E. For reference, FIG. 8A illustrates a plan view, and FIG. 8B is a cross-sectional view taken along a cutting plane of X1-X1 'of FIG. 8A, and FIG. 8C is a cross-sectional view taken along a cutting plane of X2-X2' of FIG. 8A. 8D is a cross-sectional view taken along the cutting plane of X3-X3 'of FIG. 8A, and FIG. 8E is a cross-sectional view taken along the cutting plane of Y-Y' of FIG. 8A. First, the second mask pattern 230 is removed. Next, a barrier metal layer (not shown) is deposited on the first recess 225a, the second recess 225b, and the third recess 225c. The barrier metal layer (not shown) preferably includes a titanium nitride film. Next, a gate conductive material is buried in the semiconductor substrate 200 including the first recess 225a, the second recess 225b, and the third recess 225c on which a barrier metal layer (not shown) is formed. do. Thereafter, the planarization process is performed until the semiconductor substrate 200 is exposed to form the buried fin gate 235.

As described above, while the depth of the gate formed in the device isolation layer 205 is prevented from being formed deeper than the depth of the gate formed in the active region 210, a buried fin gate having a structure in which the gate completely surrounds the channel may be formed as in the conventional art. Can be.

 It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined by the appended claims. Of the present invention.

200 semiconductor substrate 203 sidewall oxide film
205 device isolation layer 210 active region
213: pad nitride film 215: first hard mask layer
215a: first hard mask pattern 217: second hard mask layer
217a: second hard mask pattern 220: first mask pattern
225a: first recess 225b: second recess
225c: third recess 230: second mask pattern
235 gate

Claims (9)

Forming an isolation layer defining an active region on the semiconductor substrate;
Etching the active region to form a first recess;
Etching the device isolation layer to form a second recess having the same depth as the first recess;
Further etching the second recess of the portion connected with the first recess to form a third recess; And
Embedding a conductive material in the first recess, the second recess, and the third recess to form a buried fin gate
And forming a second insulating film on the semiconductor substrate. Claim 2 has been abandoned due to the setting registration fee. The method according to claim 1,
Forming the first recess is
Forming a first mask pattern defining a gate predetermined area on the semiconductor substrate; And
Etching the active region using the first mask pattern as an etching mask
And forming a second insulating film on the semiconductor substrate. Claim 3 has been abandoned due to the setting registration fee. The method according to claim 2,
Forming the second recess is
Etching the device isolation layer using the first mask pattern as an etching mask; And
Removing the first mask pattern
And forming a second insulating film on the semiconductor substrate. Claim 4 has been abandoned due to the setting registration fee. The method according to claim 1,
Forming the third recess is
Further etching the second recesses at the interface between the first and second recesses
And forming a second insulating film on the semiconductor substrate. Claim 5 was abandoned upon payment of a set-up fee. The method according to claim 1,
Forming the third recess is
A second mask exposing an active region between the first recess and the first recesses and exposing a portion of the second isolation region connected to the first recess and a portion of the device isolation layer adjacent to the active region between the first recesses; Forming a pattern; And
Further etching the second recess bottom exposed by the second mask pattern
And forming a second insulating film on the semiconductor substrate. Claim 6 has been abandoned due to the setting registration fee. The method according to claim 5,
After further etching the bottom of the second recess,
Removing the second mask pattern
Method of manufacturing a semiconductor device further comprising. Claim 7 has been abandoned due to the setting registration fee. The method according to claim 1,
Prior to forming the gate,
And forming a barrier metal layer on surfaces of the first recess, the second recess, and the third recess. Claim 8 was abandoned when the registration fee was paid. The method of claim 7,
The barrier metal layer includes a titanium nitride film. Claim 9 has been abandoned due to the setting registration fee. The method according to claim 1,
The conductive material is a method of manufacturing a semiconductor device characterized in that it comprises tungsten.

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