KR101212269B1 - Switched capacitor type gain amplifier and analog memory circuit - Google Patents

Abstract

The present invention provides a switched capacitor type gain amplifier capable of eliminating an input offset. To this end, the present invention provides a first switching unit and a response to an operation of the first switching unit. A first capacitor for sampling and storing an input signal and an input offset in a sampling-mode, and sampling and storing the input offset in an amplification-mode, and the operation of the first switching unit. In response to sampling and storing the input offset in the sampling-mode, and sampling and storing the output signal and the input offset in the amplification-mode, the capacitance of the first capacitor in the amplification-mode, A switched capacitor including an amplifier configured to amplify the input signal and output the output signal by using a ratio between the capacitances of the second capacitor as a gain value; It provides the sheeter type gain amplifier.

Switched Capacitive Gain Amplifier, Analog Memory, Input Offset Cancellation, Input Loss Compensation

Description

SWITCHED CAPACITOR TYPE GAIN AMPLIFIER AND ANALOG MEMORY CIRCUIT

1 is a circuit diagram of a switched capacitor type gain amplifier according to the prior art.

2 is an operational waveform diagram of the switching unit illustrated in FIG. 1.

3 is a circuit diagram of another switched capacitor type gain amplifier of the prior art.

4 is an operation waveform diagram of the switching unit illustrated in FIG. 3.

5 is an analog-memory circuit diagram configured with the gain amplifier shown in FIG. 1 or FIG.

6 is an operation waveform diagram of the switching unit illustrated in FIG. 5.

7 is a circuit diagram of a switched capacitor type gain amplifier according to Embodiment 1 of the present invention.

8 is an equivalent circuit diagram according to an operating state of the switching unit of FIG. 7.

9 is a circuit diagram of a switched capacitor type gain amplifier according to Embodiment 2 of the present invention.

10 is an operation waveform diagram of the switching unit illustrated in FIG. 9;

FIG. 11 is an analog-memory circuit diagram comprised of the gain amplifier shown in FIG. 7 or FIG.

<Explanation of symbols for the main parts of the drawings>

10, 20, 110, 120: operational amplifier

30, 40: gain amplifier

TECHNICAL FIELD The present invention relates to semiconductor design techniques, and more particularly to switched-capacitor type gain amplifiers and analog-memory circuits.

In general, an analog-memory circuit converts an analog signal into a digital signal and stores it in a storage medium such as static random access memory (SRAM), and then converts the digital signal stored in the storage medium into an analog signal when necessary. It is a structure to convert. However, this structure has a problem that the circuit is complicated and the area is increased.

Another analog-memory circuit structure is typically a structure in which an analog signal is sampled and stored in a capacitor, and this structure increases the leakage current of the capacitor over time. There is a problem with the reliability.

Recently, an analog-memory circuit using a loop form of a switched capacitor type gain amplifier has been proposed. This circuit uses a loop type of a switched capacitor type gain amplifier to store the signal stored in the sampling capacitor of the previous stage before the discharge of the signal stored in the sampling capacitor of the previous stage.

The analog-memory circuit using the loop form of the switched capacitor type gain amplifier operates in an iterative loop form as described above, so that the analog signal can be preserved while a clock is supplied. In this case, as the open loop gain increases, the amplifier performs an ideal amplification operation, and the feedback nodes have the same value between input nodes. However, finite open-loop gain and device mismatching due to process variations cause input offsets, resulting in signal loss when delivering signals to the later capacitors.

1 is a circuit diagram showing a switched capacitor type gain amplifier according to the prior art.

Referring to FIG. 1, a switched capacitor type gain amplifier according to the related art includes an operational amplifier 10, two capacitors C1 and C2, and three switching units SW1 to SW3.

The operating characteristics of the switched capacitor type gain amplifier of FIG. 1 will be described with reference to FIG. 2 as follows.

As shown in FIG. 2, when the switching units SW1 and SW3 are turned ON (closed state) and the switching unit SW2 is turned OFF (open state), the input voltage Vin becomes a capacitor ( Sampled in C1). In this state, when the switching units SW1 and SW3 are turned off and the switching unit SW2 is turned on, the input signal Vin is represented as an output signal Vout by the ratio c1 / c2 by the operational amplifier 10. As a result, it operates in the amplification mode that drives the next stage load. Here, 'c1' is the capacitance of the capacitor C1, and 'c2' is the capacitance of the capacitor C2.

3 is a circuit diagram showing another switched capacitor type gain amplifier according to the prior art.

Referring to FIG. 3, the switched capacitor type gain amplifier according to the related art includes an operational amplifier 10, two capacitors C1 and C2, and four switching units SW1 to SW4.

The operating characteristics of the switched capacitor type gain amplifier of FIG. 3 will be described with reference to FIG. 4 as follows.

As shown in FIG. 4, when the switching units SW1 and SW4 are turned on and the switching units SW2 and SW3 are turned off, the input voltage Vin is sampled by the capacitor C1. In this state, when the switching units SW1 and SW4 are turned off and the switching units SW2 and SW3 are turned on, the input signal Vin is represented as an output signal Vout by the ratio c1 / c2 by the operational amplifier 20. . As a result, it operates in the amplification mode that drives the next stage load. Here, 'c1' is the capacitance of the capacitor C1, and 'c2' is the capacitance of the capacitor C2.

FIG. 5 is a block diagram showing an analog-memory circuit using the gain amplifier for the switched capacitor shown in FIG. 1 or 3. Here, '30' and '40' are gain amplifiers for switched capacitors.

Operation characteristics of the analog-memory circuit of FIG. 5 will be described with reference to FIG. 6 as follows.

5 and 6, first, the switching unit SWI is turned on, and the switching unit SWT is turned off so that the output of the gain amplifier 40 of the B stage does not affect the gain amplifier 30 of the A stage. The external input signal Vin is stored in the sampling capacitor of the A stage operating in the sampling mode. Then, the switching unit SWI is turned off, the switching unit SWT is turned on, and before the leakage current occurs, the gain amplifier 30 of the A stage is operated in the amplification-mode so that the gain amplifier 30 of the A stage is operated. The analog signal stored in the sampling capacitor is stored in the sampling capacitor of the gain amplifier 40 of the B stage. The gain amplifier 40 of stage B also operates in amplification mode before leakage current occurs, so that the value stored in the sampling capacitor of the gain amplifier 40 of stage B is converted to the sampling capacitor of the gain amplifier 30 of stage A. Store in This series of loop processes can continue while the clock is being supplied to preserve the analog signal. On the other hand, the switching unit SWO is turned on when the stored analog signal is externally requested and outputs the stored signal to the outside.

However, in the analog-memory circuit according to the prior art, finite open-loop gain and device mismatch due to process variations occur, which causes an input offset in the actual amplifier, which causes signal loss when transferring a signal to a later capacitor. Will bring.

Accordingly, an object of the present invention is to provide a switched capacitor type gain amplifier capable of eliminating an input offset, which has been proposed to solve the problems of the prior art.

Another object of the present invention is to provide a switched capacitor type gain amplifier capable of eliminating an input offset and correcting an input loss.

Another object of the present invention is to provide an analog-memory circuit using the switched capacitor type gain amplifier.

According to an aspect of the present invention, a first switching unit and an input signal and an input offset are sampled and stored in a sampling mode in response to an operation of the first switching unit. A first capacitor for sampling and storing an input offset, and sampling and storing the input offset in the sampling-mode in response to an operation of the first switching unit, and sampling and storing the output signal and the input offset in the amplification-mode And a second capacitor and an amplifier configured to amplify the input signal and output the output signal using a ratio between the capacitance of the first capacitor and the capacitance of the second capacitor as a gain value in the amplification-mode. Capacitive gain amplifiers are provided.

In addition, the present invention according to another aspect to achieve the above object, the first switching unit, in response to the operation of the first switching unit in the sampling-mode sampling and storing the input signal and the input offset, the amplification-mode A first capacitor for sampling and storing the input offset at the time of sampling and storing the input offset in the sampling-mode in response to an operation of the first switching unit, and sampling the output signal and the input offset in the amplification-mode. An amplifying unit for amplifying the input signal and outputting the output signal by using a ratio between the second capacitor to be stored and the capacitance of the first capacitor and the capacitance of the second capacitor in the amplification-mode as a gain value; And a third capacitor configured to sample and store a difference value between the output signal and the input signal in a compensation mode in response to an operation of the first switching unit. It provides a switched-capacitor type amplifier gain.

In addition, the present invention according to another aspect for achieving the above object has a configuration of the second switching unit and the switched capacitor-type gain amplifier, and connected to each other in a loop form in response to the operation of the second switching unit. An analog-memory circuit is provided that includes first and second gain amplifiers.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, parts denoted by the same reference numerals throughout the specification represent the same elements performing the same function.

Example 1

FIG. 7 is a circuit diagram illustrating the configuration of a switched capacitor type gain amplifier according to Embodiment 1 of the present invention.

Referring to FIG. 7, the switched capacitor type gain amplifier according to the first embodiment of the present invention includes a capacitor C2 for removing the offset of the operational amplifier 110 in order to transfer the input signal to the output terminal without loss. Connect between negative input terminal and output terminal.
In more detail, the switched capacitor type gain amplifier according to Embodiment 1 of the present invention includes a plurality of first switching elements SW1 disposed between an input terminal provided with an input signal Vin and a ground voltage terminal. A switching unit including switching elements SW1 to SW4, and a first capacitor C1 sampling and storing an input signal and an input offset in a sampling-mode in response to an operation of the switching unit, and sampling and storing the input offset in an amplification-mode. ), In response to the operation of the switching unit, a second capacitor C2 sampling and storing the input offset in the sampling-mode, sampling and storing the output signal Vout and the input offset in the amplification-mode, and a first in the amplification-mode. And an amplifier for amplifying the input signal by outputting a ratio between the capacitance of the capacitor C1 and the capacitance of the second capacitor C2 as a gain value. In this case, the amplifier may represent, for example, the operational amplifier 110.
Here, one end of the first switching element SW1, that is, one terminal is commonly connected to the input terminal and one end of the first capacitor C1, and the other end, that is, the other terminal is connected to the ground voltage terminal, and the first switching element SW1 is connected. ) Is simultaneously turned on at the same time as one of the plurality of switching elements SW1 to SW4 connected to the other end of the second capacitor C2 and the output end of the amplifier part, for example, the third switching element SW3. And an OFF operation.
Both ends of the first capacitor C1 are connected to the input terminal through which the input signal is input and the negative input terminal of the amplifying unit, respectively, and both ends of the second capacitor C2 are connected to the negative input terminal and the output signal Vout of the amplifier unit. Are electrically connected to the output terminals.
In addition, the switching unit includes a first switching element SW1 connected at both ends to an input terminal and a ground voltage terminal, a second switching element SW2 connected at both ends to an output terminal and a second capacitor C2 at each end of the second capacitor C2. And a third switching element SW3 connected at both ends to the other end and the output end of C2), and a fourth switching element SW4 connected at both ends to the other end and the ground voltage terminal of the second capacitor C2, respectively.
According to the above configuration, in the sampling mode, the second and fourth switching elements SW2 and SW4 are kept in an ON state, and the first and third switching elements SW1 and SW3 are in an OFF state. maintain.
In contrast, in the amplification mode, the first and third switching devices SW1 and SW3 are kept in an on state, and the second and fourth switching devices SW2 and SW4 are in an off state.
The amplifier includes a negative input terminal connected to the first capacitor C1 and a positive input terminal formed of an operational amplifier 110 connected to a ground voltage terminal.

An operation characteristic of the switched capacitor gain amplifier according to the first embodiment of the present invention having such a configuration to remove an input offset will be described with reference to FIG. 8 as follows.

FIG. 8A is an equivalent circuit diagram of FIG. 7 in a sampling-mode, and FIG. 8B is an equivalent circuit diagram of FIG. 7 in an amplification-mode. In addition, for convenience of description, the input offset Voff is modeled on the positive input terminal of the amplifier 110.

First, as shown in FIG. 8A, in the sampling mode, the switching units SW1 and SW3 are turned off, and the switching units SW2 and SW4 are turned on so that the input signal Vin is applied to the capacitor C1. Sampled. At this time, as much as "c1 x (Vin-Voff)" charges are stored in the capacitor C1, and as much as "c2 x (-Voff)" charges are stored in the capacitor C2. Here, 'c1' is the capacitance of the capacitor C1, and 'c2' is the capacitance of the capacitor C2.

Then, as shown in Fig. 8B, in the amplification mode, the switching units SW1 and SW3 are turned on, and the switching units SW2 and SW4 are turned off so that the capacitor C1 has " c1 x (−). Voff) " is stored, and the capacitor C2 stores the charge of " c2 x (Vout-Voff) ".

In accordance with the law of charge conservation, the sum of the charges stored in the capacitors C1 and C2 in the sampling mode and the amplification mode is the same. This is shown in Equation 1 below.

c1 × (Vin-Voff) + c2 × (-Voff) = c1 × (-Voff) + c2 × (Vout-Voff)

In summary, the output signal Vout is as shown in Equation 2 below.

Vout = c1 / c2 × Vin

As shown in Equation 2, it can be seen that the output signal Vout has been removed from the input offset Voff.

Example 2

FIG. 9 is a circuit diagram for explaining the configuration of a switched capacitor type gain amplifier according to Embodiment 2 of the present invention.

9, the switched capacitor type gain amplifier according to the second embodiment of the present invention has an input loss correction function to compensate for the input loss shown in the gain amplifier of the first embodiment.

In the gain amplifier according to the first embodiment, the output signal Vout is represented by Equation 2 above. Here, 'c1 / c2' is a gain value, and the output is expressed in the form of "gain x input". For example, even if the gain amplifier according to Embodiment 1 is used as a capacitor having capacitors C1 and C2 with the same capacitance to use as an analog-memory circuit, a gain error occurs and the output is equal to the input. It does not appear, but it is multiplied by the gain value including gain loss.

Therefore, the switched capacitor type gain amplifier according to Embodiment 2 of the present invention includes a gain compensation capacitor C3 for compensating for gain loss while eliminating an input offset.
In more detail, the switched capacitor type gain amplifier according to the second embodiment of the present invention includes a switching unit including a plurality of switching elements SW1 to SW8 and an input signal and an input offset in the sampling mode in response to the operation of the switching unit. First capacitor C1 for sampling and storing the input offset in the amplification-mode, and sampling and storing the input offset in the sampling-mode in response to the operation of the switching unit, and outputting the output signal and the input offset in the amplification-mode. Amplifies the input signal by a ratio between the second capacitor C2 for sampling and storing, and the capacitance of the first capacitor C1 and the capacitance of the second capacitor C2 in the amplification-mode as a gain value, and outputs an output signal. And a third capacitor C3 for sampling and storing a difference value between the output signal and the input signal in the compensation mode in response to an operation of the switching unit, wherein the plurality of switching elements SW1 are included. One of the switching elements, ie, one of the second switching elements SW2, is connected to the input terminal and one end of the first capacitor C1 in common, and the other end is connected to the ground voltage terminal. To simultaneously turn on and off the other switching element, for example, the fourth switching element SW4, from among a plurality of switching elements respectively connected to the other end of the second capacitor C2 and the output end of the amplifier. do.
Here, both ends of the first capacitor C1 are connected to the input terminal to which the input signal is input and to the negative input terminal of the amplifier, respectively, and both ends of the second capacitor C2 are connected to the negative input terminal and the output signal of the amplifier. It is electrically connected to the output terminal which is output, respectively.
The switching unit may include a first switching element SW1 connected at both ends to an input terminal and an output terminal, a second switching element SW2 connected at both ends between an input terminal and a ground voltage terminal, and a negative input terminal and a negative input terminal of the amplifying unit. The other end of the third switching element SW3, the second capacitor C2, which is connected at both ends to the first output terminal, and the other end of the fourth switching element SW4, and the second capacitor C2, which are connected at both ends to the first output terminal, respectively. A fifth switching element SW5 having both ends connected to the terminal and the ground voltage terminal, a sixth switching element SW6 having both ends connected to the other end of the first output terminal and the third capacitor C3, and a sixth switching element SW6 respectively; ) And the seventh switching element (SW7) and the fifth switching element (SW5), the third capacitor (C3) and the first output terminal are connected to both ends of the connection point and the ground voltage terminal connected to the third capacitor (C3) And an eighth switching element SW8 having both ends connected to the interconnection point and the second output end, respectively.
According to the above configuration, in the sampling-mode, the second and fourth switching elements SW2 and SW4 are kept in an ON state, and the first, third, fifth and eighth switching elements SW1, SW3 and SW5. SW8 is maintained in the OFF state, while in the amplification mode, the first and third switching elements SW1 and SW3 are kept in the ON state, and the second, fourth, fifth to eighth switching elements (SW2, SW4, SW5 to SW8) are kept off. In addition, in the compensation mode, the seventh and eighth switching elements SW7 and SW8 are turned on while the first, third, fifth and sixth switching elements SW1, SW3, SW5 and SW6 are kept on. The values stored in the second and third capacitors C2 and C3 are output to the second output terminal.
On the other hand, the amplifying unit includes a negative (−) input terminal is connected to the first capacitor (C1), the positive input terminal is an operational amplifier 120 is connected to the ground voltage terminal.

In the gain amplifier according to the second embodiment of the present invention shown in FIG. 9, the gain amplifier, the sampling-mode, and the amplification-mode according to the first embodiment shown in FIG. The above description will be made, and hereinafter, an operation characteristic in which the gain amplifier according to Embodiment 2 corrects an input loss will be described.

The compensation-mode for compensating for the input loss is performed after performing both the sampling mode and the amplification mode in the first embodiment. This will be described with reference to FIG. 10.

9 and 10, while amplification is completed during an amplification-mode (Tamp) period, the output of the amplifier 120 is a product of an input signal and a gain Vin × A (where 'A' is a gain value). Appears. In this case, when the gain A becomes '1', it operates as a memory. However, when gain loss occurs and A has a value smaller than 1, the switching units SW1, SW2, SW4, and SW6 are kept on so that the difference between the output value of the amplifier 120 and the input signal Vin × ( 1-A)) is stored in the capacitor C3. In this state, the switching units SW7 and SW8 are turned on to transfer the values stored in the capacitors C2 and C3 to the output terminal Vout. As a result, the input signal Vin, which adds two charges to the capacitor of the gain amplifier (in the case of an analog-memory circuit) in the next stage, is transmitted without loss of input voltage, thereby correcting gain loss (1-A). .

Example 3

FIG. 11 is a diagram for explaining an analog-memory circuit according to Embodiment 3 of the present invention.

Referring to FIG. 11, the analog-memory circuit according to Embodiment 3 of the present invention is constructed using the switched capacitor type gain amplifier shown in FIG. That is, two switched capacitor type gain amplifiers A and B are connected to each other in a loop to store analog signals. Detailed description thereof will be replaced with the above description.
However, the analog-memory circuit according to the third embodiment of the present invention may include a switching unit (or a first switching unit), wherein the first switching unit provides an input signal to an input terminal of the first gain amplifier A. An input switching element SWI, a transfer switching element SWT connected at both ends to an input end of the first gain amplifier A, and an output end of the second gain amplifier B, and an output end of the first gain amplifier A. One end is connected to the output switching element (SWO) for outputting a signal.
Here, the input switching element SWI is kept on in the sampling-mode of the first gain amplifier A, and the transfer switching element SWT is kept in the off state, so that the input signal is controlled by the first gain amplifier A. It is sampled and stored by one capacitor C1.
The input switching element SWI is kept off in the amplification-mode of the first gain amplifier A, and the transfer switching element SWT is kept in the on state so that the first capacitor C1 of the first gain amplifier A is closed. The value sampled and stored at) is sampled and stored in the first capacitor C1 of the second gain amplifier B.
The input switching element SWI is kept off in the amplification-mode of the second gain amplifier B, and the transfer switching element SWT is kept in the on-state so that the first capacitor of the second gain amplifier B is The value sampled and stored in C1) is sampled and stored in the first capacitor C1 of the first gain amplifier A.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, in a structure requiring a logic standard process analog-memory circuit, a complex circuit and a large area of an analog digital converter (ADC) -SRAM-DAC (Digital Analog Converter) form Instead of using an analog-memory circuit, the circuit is simple and compensates for the input signal loss caused by the mismatching of the gain amplifier and the loss of the input signal caused by the gain loss. Economical and efficient

Claims (26)

A switching unit including a first switching element disposed between an input terminal provided with an input signal and a ground voltage terminal, the switching unit including a plurality of switching elements other than the first switching element; A first capacitor sampling and storing an input signal and an input offset in a sampling-mode in response to an operation of the switching unit, and sampling and storing the input offset in an amplification-mode; A second capacitor configured to sample and store the input offset in the sampling-mode in response to an operation of the switching unit, and to sample and store the output signal and the input offset in the amplification-mode; And An amplifying unit configured to amplify the input signal and output the output signal by using a ratio between the capacitance of the first capacitor and the capacitance of the second capacitor as a gain value in the amplification mode; One end of the first switching element is commonly connected to an input terminal and one end of the first capacitor, and the other end is connected to a ground voltage terminal. The first switching device is ON and OFF in the same state as one switching device that is connected to both ends of the second capacitor and the output terminal of the amplifier of the plurality of switching devices, respectively. Switched capacitor type gain amplifier. The method of claim 1, A switched capacitor gain amplifier connected to both ends of the first capacitor and an input terminal to which the input signal is input and a negative input terminal of the amplifier. The method of claim 2, Both ends of the second capacitor is a switched capacitor type gain amplifier electrically connected to the negative (-) input terminal and the output terminal of the output signal is output. The method of claim 3, wherein The switching unit includes: A first switching element connected at both ends to the input terminal and the ground voltage terminal; A second switching element having both ends connected to one end of the second capacitor and the output end, respectively; A third switching element having both ends connected to the other end and the output end of the second capacitor, respectively; And A fourth switching element having both ends connected to the other end of the second capacitor and the ground voltage terminal, respectively. Switched capacitor-type gain amplifier comprising a. 5. The method of claim 4, And the second and fourth switching elements are kept in an ON state and the first and third switching elements are in an OFF state in the sampling-mode. 6. The method of claim 5, And said first and third switching elements remain on and said second and fourth switching elements remain off in said amplification-mode. The method of claim 6, The amplifying unit is a switched capacitor type gain amplifier comprising a negative (-) input terminal is connected to the first capacitor, the positive input terminal is an operational amplifier connected to the ground voltage terminal. A switching unit including a plurality of switching elements; A first capacitor sampling and storing an input signal and an input offset in a sampling-mode in response to an operation of the switching unit, and sampling and storing the input offset in an amplification-mode; A second capacitor configured to sample and store the input offset in the sampling-mode in response to an operation of the switching unit, and to sample and store the output signal and the input offset in the amplification-mode; And An amplifier for amplifying the input signal and outputting the output signal by using a ratio between the capacitance of the first capacitor and the capacitance of the second capacitor in a gain mode; And And a third capacitor configured to sample and store a difference value between the output signal and the input signal in a compensation mode in response to an operation of the switching unit. One end of one of the plurality of switching elements is commonly connected to an input terminal and one end of the first capacitor, the other end is connected to the ground voltage terminal, The one switching element is ON and OFF in the same state as the other switching element of the plurality of switching elements connected to the other end of the second capacitor and the output terminal of the amplifying unit, respectively. Switched capacitor type gain amplifier. 9. The method of claim 8, A switched capacitor gain amplifier connected to both ends of the first capacitor and an input terminal to which the input signal is input and a negative input terminal of the amplifier. The method of claim 9, Both ends of the second capacitor are switched capacitor type gain amplifier electrically connected to the negative (-) input terminal and the output terminal of the output signal is output. 11. The method of claim 10, The switching unit includes: First switching elements connected at both ends of the input terminal and the output terminal, respectively; A second switching element connected at both ends between the input terminal and the ground voltage terminal; A third switching element connected at both ends to the negative input terminal and the first output terminal of the amplifier; A fourth switching element having both ends connected to the other end of the second capacitor and the first output end, respectively; A fifth switching element having both ends connected to the other end of the second capacitor and the ground voltage terminal, respectively; A sixth switching element having both ends connected to the other ends of the first output terminal and the third capacitor, respectively; A seventh switching element connected at both ends to a connection point to which the sixth switching element and the third capacitor are connected and to the ground voltage terminal; And An eighth switching element having both ends connected to a connection point at which the fifth switching element, the third capacitor, and the first output end are interconnected, and a second output end, respectively; Switched capacitor-type gain amplifier comprising a. The method of claim 11, In the sampling-mode, the second and fourth switching elements are kept in an ON state, and the first, third, fifth to eighth switching elements are in an OFF state. Gain amplifier. 13. The method of claim 12, And the second, fourth, fifth to eighth switching elements remain in an off state during the amplification-mode, and the second, fourth, fifth to eighth switching elements remain in an off state. The method of claim 13, In the compensation-mode, the seventh and eighth switching elements are turned on while the first, third, fifth, and sixth switching elements are kept in an on state to store the values stored in the second and third capacitors. A switched capacitor type gain amplifier for outputting to a second output stage. 15. The method of claim 14, The amplifying unit is a switched capacitor type gain amplifier comprising a negative (-) input terminal is connected to the first capacitor, the positive input terminal is an operational amplifier connected to the ground voltage terminal. A first switching unit; And A first gain amplifier and a second gain amplifier connected to each other in a loop form in response to an operation of the first switching unit, At least one gain amplifier of the first and second gain amplifiers, A second switching unit including a first switching element disposed between an input terminal provided with an input signal and a ground voltage terminal, the second switching unit including a plurality of switching elements other than the first switching element; A first capacitor sampling and storing an input signal and an input offset in a sampling mode in response to an operation of the second switching unit, and sampling and storing the input offset in an amplification mode; A second capacitor sampling and storing the input offset in the sampling-mode in response to an operation of the second switching unit, and sampling and storing the output signal and the input offset in the amplification-mode; And And an amplifier for amplifying the input signal and outputting the output signal by using a ratio between the capacitance of the first capacitor and the capacitance of the second capacitor as a gain value in the amplification mode. One end of the first switching element is commonly connected to an input terminal and one end of the first capacitor, and the other end is connected to a ground voltage terminal. And the first switching element operates in the same state as one switching element which is connected to the other end of the second capacitor and the output end of the amplifying unit, respectively, among the plurality of switching elements. 17. The method of claim 16, The first switching unit, An input switching element providing an input signal to an input terminal of the first gain amplifier; A transfer switching element connected at both ends to an input terminal of the first gain amplifier and an output terminal of the second gain amplifier; And An output switching element having one end connected to an output terminal of the first gain amplifier and outputting a signal Analog-memory circuit comprising a. The method of claim 17, The input switching element is kept in an on state in the sampling-mode of the first gain amplifier, and the transfer switching element is kept in an off state so that the input signal is sampled and stored in the first capacitor of the first gain amplifier. Analog-memory circuit. The method of claim 18, The input switching element remains off in the amplification-mode of the first gain amplifier, and the transfer switching element remains on so that the value sampled and stored in the first capacitor of the first gain amplifier is stored in the second state. And an analog-memory circuit which is sampled and stored in said first capacitor of a gain amplifier. 20. The method of claim 19, The input switching element remains off in the amplification-mode of the second gain amplifier, and the transfer switching element remains on-state so that the value sampled and stored in the first capacitor of the second gain amplifier is stored in the first gain amplifier. And an analog-memory circuit which is sampled and stored in said first capacitor of a gain amplifier. A first switching unit; And A first gain amplifier and a second gain amplifier connected to each other in a loop form in response to an operation of the first switching unit, At least one gain amplifier of the first and second gain amplifiers, A second switching unit including a plurality of switching elements; A first capacitor sampling and storing an input signal and an input offset in a sampling mode in response to an operation of the second switching unit, and sampling and storing the input offset in an amplification mode; A second capacitor sampling and storing the input offset in the sampling-mode in response to an operation of the second switching unit, and sampling and storing the output signal and the input offset in the amplification-mode; And An amplifier for amplifying the input signal and outputting the output signal by using a ratio between the capacitance of the first capacitor and the capacitance of the second capacitor in a gain mode; And A third capacitor configured to sample and store a difference value between the output signal and the input signal in a compensation mode in response to an operation of the second switching unit, One end of one of the plurality of switching elements is commonly connected to an input terminal and one end of the first capacitor, the other end is connected to the ground voltage terminal, The one switching element is ON and OFF in the same state as the other switching element of the plurality of switching elements connected to the other end of the second capacitor and the output terminal of the amplifying unit, respectively. Characterized by an analog-memory circuit. 22. The method of claim 21, The first switching unit, An input switching element providing an input signal to an input terminal of the first gain amplifier; A transfer switching element connected at both ends to an input terminal of the first gain amplifier and an output terminal of the second gain amplifier; And An output switching element having one end connected to an output terminal of the first gain amplifier and outputting a signal Analog-memory circuit comprising a. 23. The method of claim 22, The input switching element is kept in an on state in the sampling-mode of the first gain amplifier, and the transfer switching element is kept in an off state so that the input signal is sampled and stored in the first capacitor of the first gain amplifier. Analog-memory circuit. 24. The method of claim 23, The input switching element remains off in the amplification-mode of the first gain amplifier, and the transfer switching element remains on so that the value sampled and stored in the first capacitor of the first gain amplifier is stored in the second state. And an analog-memory circuit which is sampled and stored in said first capacitor of a gain amplifier. 25. The method of claim 24, The input switching element remains off in the amplification-mode of the second gain amplifier, and the transfer switching element remains on-state so that the value sampled and stored in the first capacitor of the second gain amplifier is stored in the first gain amplifier. And an analog-memory circuit which is sampled and stored in said first capacitor of a gain amplifier. A first switching unit; And A first gain amplifier and a second gain amplifier connected to each other in a loop form in response to an operation of the first switching unit, At least one gain amplifier of the first and second gain amplifiers, A second switching unit including a plurality of switching elements including a first switching element disposed between an input terminal provided with an input signal and a ground voltage terminal; A first capacitor sampling and storing an input signal and an input offset in a sampling mode in response to an operation of the second switching unit, and sampling and storing the input offset in an amplification mode; A second capacitor sampling and storing the input offset in the sampling-mode in response to an operation of the second switching unit, and sampling and storing the output signal and the input offset in the amplification-mode; And An amplifier for amplifying the input signal and outputting the output signal by using a ratio between the capacitance of the first capacitor and the capacitance of the second capacitor in a gain mode; And A third capacitor configured to sample and store a difference value between the output signal and the input signal in a compensation mode in response to an operation of the second switching unit, One end of the first switching element is commonly connected to the input end and one end of the first capacitor, and the other end is commonly connected to one end of the third capacitor and the output end of the amplifier.

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