CN109474241B

CN109474241B - Amplifier and reset method thereof

Info

Publication number: CN109474241B
Application number: CN201710807552.7A
Authority: CN
Inventors: 吴健铭; 雷良焕; 黄诗雄; 陈志龙
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2017-09-08
Filing date: 2017-09-08
Publication date: 2022-09-27
Anticipated expiration: 2037-09-08
Also published as: CN109474241A

Abstract

The amplifier comprises an output stage circuit and a compensation circuit. The output stage circuit comprises a first input end, a second input end, a first output end and a second output end. The compensation circuit comprises a first capacitor, a second capacitor, a third capacitor and a fourth capacitor. The first capacitor is coupled between the first input end and the second output end and is used for operating as a first Miller capacitor. The second capacitor is coupled between the second input terminal and the first output terminal and is used for operating as a second miller capacitor. The third capacitor and the fourth capacitor are used for alternately operating as a first Miller capacitor and a second Miller capacitor according to at least one clock signal.

Description

Amplifier and reset method thereof

Technical Field

The present invention relates to an amplifier, and more particularly, to an amplifier applied to an analog-to-digital converter and a reset method thereof.

Background

Amplifiers are commonly used in various electronic devices, for example, amplifiers may be used in sample-and-hold circuits of analog-to-digital converters, and the like. Since the amplifier often needs to be configured with a miller capacitor coupled to the output terminal to set the bandwidth and stability. However, the miller capacitance may retain the charge left by the amplifier in the previous operation, which may cause inaccuracy of the output signal or cause the output signal to have non-linear characteristics. To avoid this problem, the amplifier is reset before each amplification. However, as the operating speed of the circuit increases, the existing reset mechanism is not sufficient to completely eliminate the residual charge in the amplifier.

Disclosure of Invention

In order to solve the above problems, an aspect of the present invention is to provide an amplifier. The amplifier comprises an output stage circuit and a compensation circuit. The output stage circuit comprises a first input end, a second input end, a first output end and a second output end. The compensation circuit comprises a first capacitor, a second capacitor, a third capacitor and a fourth capacitor. The first capacitor is coupled between the first input end and the second output end and is used for operating as a first Miller capacitor. The second capacitor is coupled between the second input terminal and the first output terminal and is used for operating as a second miller capacitor. The third capacitor and the fourth capacitor are used for alternately operating as a first Miller capacitor and a second Miller capacitor according to at least one clock signal.

One aspect of the present invention is to provide an amplifier. The amplifier comprises an output stage circuit and a compensation circuit. The output stage circuit comprises a plurality of input ends and a plurality of output ends. The compensation circuit is coupled between the input ends and the output ends and is used for operating as a first Miller capacitor and a second Miller capacitor according to a first clock signal and a second clock signal. The compensation circuit comprises a first capacitor, a second capacitor, a third capacitor and a fourth capacitor. During the enabling period of the first clock pulse signal, the first capacitor and the second capacitor operate as a first miller capacitor, the third capacitor and the fourth capacitor operate as a second miller capacitor, and during the enabling period of the second clock pulse signal, the first capacitor and the third capacitor operate as the first miller capacitor, and the fourth capacitor and the second capacitor operate as the second miller capacitor.

In one aspect, the present invention provides a reset method, which includes the following operations: operating as a first miller capacitor corresponding to a first output terminal of the amplifier according to the first clock signal through the first capacitor and the second capacitor; operating as a second miller capacitor corresponding to a second output terminal of the amplifier according to the first clock signal through a third capacitor and a fourth capacitor; operating a first miller capacitor corresponding to the first output end through the first capacitor and the fourth capacitor according to the second clock pulse signal; and a second miller capacitor corresponding to the second output terminal is operated by the third capacitor and the second capacitor according to the second clock pulse signal.

In summary, the amplifier and the reset method thereof provided by the present invention can alternately switch the coupling relationship between the miller capacitance and the output terminal of the amplifier, thereby eliminating the residual charge in the previous operation.

Drawings

The drawings of the invention are illustrated as follows:

FIG. 1 is a schematic diagram of an amplifier according to some embodiments of the present invention;

FIG. 2 is a schematic diagram of a switched capacitor circuit according to some embodiments of the present invention;

FIG. 3A is a schematic circuit diagram of the amplifier of FIG. 3A according to some embodiments of the invention;

FIG. 3B is a circuit diagram of the compensation circuit of FIG. 1 or FIG. 2 according to some embodiments of the present invention;

FIG. 3C is a waveform diagram illustrating waveforms of the clock signals of FIGS. 2 and 3B according to some embodiments of the present invention;

FIG. 3D is a schematic diagram illustrating the operation of the amplifier of FIG. 3A when a clock signal in FIG. 3C is high, according to some embodiments of the present invention;

FIG. 3E is a schematic diagram illustrating the operation of the amplifier of FIG. 3A when the other clock signal of FIG. 3C is high, according to some embodiments of the present invention; and

fig. 4 is a flow chart of a reset method according to some embodiments of the invention.

Description of the reference numerals:

100: the amplifier 110: input stage circuit

120: output stage circuit 130: compensation circuit

I11, I12: inputs O11, O12: output terminal

VI1, VI 2: input signals VO11, VO 12: output signal

I21, I22: input terminals O21, O22: output terminal

VO21, VO 22: output signals Pd1, Nd 1: node point

Φ 1r, Φ 2 r: clock signals Φ 1, Φ 2: clock signal

200: switched capacitor circuits SW 1-SW 6: sampling switch

CH1, CH 2: sampling capacitors M1-M9: transistor with a high breakdown voltage

VDD: voltage GND: ground (floor)

131. 132: capacitive circuits VB1, VB2, Vcmfb: bias voltage

S1-S8: switches CN1, CN2, CP1, CP 2: capacitor with a capacitor element

+ Δ V, - Δ V: signal amplitudes T1, T2: during the enabling period

S410 to S440: operation 400: reset method

Detailed Description

Referring to fig. 1, fig. 1 is a schematic diagram of an amplifier 100 according to some embodiments of the invention. Amplifier 100 includes an input stage circuit 110, an output stage circuit 120, and a compensation circuit 130.

The input stage circuit 110 includes a plurality of inputs I11 and I12 and a plurality of outputs O11 and O12. The input terminals I11 and I12 receive input signals VI1 and VI2, respectively. In some embodiments, the input signals VI1 and VI2 may be differential input signals. The input stage circuit 110 is used for providing a first-stage gain to amplify the input signals VI1 and VI2, so as to output a plurality of output signals VO11 and VO12 from a plurality of output terminals O11 and O12, respectively.

The output stage 120 includes a plurality of inputs I21 and I22 and a plurality of outputs O21 and O22. The input terminal I21 and the output terminal O11 of the input stage circuit 110 are coupled to the node Nd1 for receiving the output signal VO 11. The input terminal I22 and the output terminal O12 of the input stage circuit 110 are coupled to the node Pd1 for receiving the output signal VO 12. The output stage circuit 120 is configured to provide a second stage gain to amplify the output signals VO11 and VO12, and output the output signals VO21 and VO22 from the output terminals O21 and O22, respectively.

The compensation circuit 130 is coupled between the input terminals I21 and I22 and the output terminals O21 and O22. The compensation circuit 130 is used to compensate the frequency response of the amplifier 100, so as to set the stability and bandwidth of the amplifier 100. For example, in some embodiments, the compensation circuit 130 includes a plurality of miller capacitors (e.g., capacitors CN1, CN2, CP1, and CP2 of fig. 3B), wherein the miller capacitors are coupled between the output terminals O22, O21 and the input terminals I21, I22.

In some embodiments, a single miller capacitance may be implemented with multiple capacitors connected in parallel. In some embodiments, the compensation circuit 130 is further configured to couple the capacitors to each other within a certain period according to the clock signal Φ 1r and the clock signal Φ 2 r. With this arrangement, the capacitors can be recycled as Miller capacitors after each operation. In this way, the voltage levels of the output terminals O21 and O22 can be reset to a predetermined level (e.g., a common mode voltage) in each operation, so as to improve the linearity and/or accuracy of the output signals VO21 and VO 22. The contents of this will be described in the following paragraphs with reference to fig. 3A to 3E.

Referring to fig. 2, fig. 2 is a schematic diagram of a switched capacitor circuit 200 according to some embodiments of the invention. For ease of understanding, similar elements of fig. 2 to fig. 1 will be designated with the same reference numerals. In some embodiments, the switched capacitor circuit 200 may be applied to an analog-to-digital converter. For example, the switched capacitor circuit 200 may operate as a sample-and-hold circuit or as a Multiplying digital-to-analog converter (multiplexing DAC). The above applications are only examples, and the present invention is not limited thereto.

As shown in fig. 2, the switched capacitor circuit 200 includes the amplifier 100 of fig. 1, a plurality of sampling switches SW 1-SW 6, and a plurality of sampling capacitors CH1 and CH 2. The sampling switches SW 1-SW 4 are turned on according to the clock signal Φ 1, and the sampling switches SW 5-SW 6 are turned on according to the clock signal Φ 2, so as to set the operation mode of the switched capacitor circuit 200. For example, as shown in fig. 3C, in some embodiments, the clock signals Φ 1 and Φ 2 are non-overlapping clock signals. In other words, the enabled period T1 of the clock signal Φ 1 does not overlap the enabled period T2 of the clock signal Φ 2. In some embodiments, the enabling period is a period in which the clock signal turns on the switch. For example, in this document, the enabling period is a period in which the clock signal is at a high level, but the invention is not limited thereto.

During the enabling period T1, the sampling switches SW1 SW4 are turned on and the sampling switches SW5 SW6 are turned off. Under this condition, the switched capacitor circuit 200 is set to the sampling mode. In the sampling mode, the input signals VI1 and VI2 are sampled to the sampling capacitors CH1 and CH2, respectively. For example, the input signals VI1 and VI2 are differential inputs, and the sampled signal values of the sampling capacitors CH1 and CH2 are denoted as VCM- Δ V and VCM + Δ V, where VCM is the common mode voltage of the differential inputs and Δ V is the signal amplitude of the differential inputs.

Then, during the enabling period T2, the sampling switches SW1 SW4 are turned off and the sampling switches SW5 SW6 are turned on. Under this condition, the switched capacitor circuit 200 is set to the hold mode (or called the amplification mode). In the hold mode, the amplifier 100 amplifies the previous sampled signal values VCM- Δ V and VCM + Δ V to generate a plurality of output signals VO21 and VO 22.

Ideally, the output signals VO21 and VO22 generated at a time in the hold mode should be independent from the output signals VO21 and VO22 generated during the previous sampling mode. However, since a plurality of miller capacitors (not shown) in the amplifier 100 are coupled to the output terminals O21 and O22, at the end of the enabling period T1, the miller capacitors may have output signals VO21 and VO22 generated at the time. For example, the miller capacitors are coupled to the output terminal O21 and the output terminal O22, and respectively hold charges corresponding to the previous sampled signal values VCM- Δ V and VCM + Δ V. In this way, the output signals VO21 and VO22 generated by the amplifier 100 in the subsequent hold mode have non-linear characteristics or are affected by noise. In some cases, these phenomena are referred to as Inter Symbol Interference (ISI) or memory effects. In some embodiments, the compensation circuit 130 of fig. 1 can be used to eliminate these phenomena.

Referring to fig. 3A, fig. 3A is a circuit schematic diagram of the amplifier 100 of fig. 3A according to some embodiments of the invention. For ease of understanding, similar elements in fig. 1 and 3A will be designated with the same reference numerals.

As shown in FIG. 3A, the input stage circuit 110 includes a plurality of transistors M1-M5. The first terminal of the transistor M1 is coupled to the first terminal of the transistor M2, the second terminal of the transistor M1 is set as the output terminal O11 and coupled to the node Nd1, and the control terminal of the transistor M1 is set as the input terminal I11. The second terminal of the transistor M2 is set as the output terminal O12 and coupled to the node Pd1, and the control terminal of the transistor M2 is set as the input terminal I22. The first terminal of the transistor M3 is coupled to the node Nd1, the second terminal of the transistor M3 is coupled to the ground GND, and the control terminal of the transistor M3 is for receiving the bias voltage VB 2. The first terminal of the transistor M4 is coupled to the node Pd1, the second terminal of the transistor M4 is coupled to ground GND, and the control terminal of the transistor M4 is for receiving the bias voltage VB 2. The first terminal of the transistor M5 is for receiving the voltage VDD, the second terminal of the transistor M5 is coupled to the first terminals of the transistors M1-M2, and the control terminal of the transistor M5 is for receiving the bias voltage Vcmfb.

In some embodiments, the amplifier 100 further comprises a common mode feedback circuit (not shown) for generating a bias voltage Vcmfb according to the output signals VO21 and VO22 to maintain a predetermined bias condition of the amplifier 100.

With continued reference to fig. 3A, in this example, the compensation circuit 130 includes a capacitive circuit 131 and a capacitive circuit 132. In some embodiments, the capacitive circuit 131 is coupled to the node Nd1 and the output terminal O22 to serve as a miller capacitance of the amplifier 100, and the capacitive circuit 132 is coupled between the node Pd1 and the output terminal O21 to serve as another miller capacitance of the amplifier 100.

The output stage circuit 120 includes a plurality of transistors M6-M9. The first terminal of the transistor M6 is set as the output terminal O21 and is coupled to the second terminal of the transistor M7 and one terminal of the capacitive circuit 132, the second terminal of the transistor M6 is coupled to the ground GND, and the control terminal of the transistor M6 is set as the input terminal I22 coupled to the node Pd1 and the other terminal of the capacitive circuit 132. The first terminal of the transistor M7 is for receiving the voltage VDD, and the control terminal of the transistor M7 is for receiving the bias voltage VB 1. The first terminal of the transistor M8 is set as the output terminal O22 and is coupled to the second terminal of the transistor M9 and one terminal of the capacitive circuit 131, the second terminal of the transistor M8 is coupled to the ground GND, and the control terminal of the transistor M8 is set as the input terminal I21 coupled to the node Nd1 and the other terminal of the capacitive circuit 131. The first terminal of the transistor M9 is for receiving the voltage VDD, and the control terminal of the transistor M9 is for receiving the bias voltage VB 1.

The arrangement shown in fig. 3A described above is merely an example. Various other arrangements for implementing the amplifier 100 are also within the scope of the present invention.

Referring to fig. 3B to 3E, fig. 3B is a circuit diagram illustrating the compensation circuit 130 of fig. 1 or fig. 2 according to some embodiments of the invention, fig. 3C is a waveform diagram illustrating the clock signals of fig. 2 and fig. 3B according to some embodiments of the invention, fig. 3D is an operation diagram illustrating the amplifier 100 of fig. 3A when the clock signal Φ 2r of fig. 3C is at a high level according to some embodiments of the invention, and fig. 3E is an operation diagram illustrating the amplifier 100 of fig. 3A when the clock signal Φ 1r of fig. 3C is at a high level according to some embodiments of the invention.

As shown in fig. 3B, the compensation circuit 130 includes a plurality of capacitors CN1, CN2, CP1, CP2, and a plurality of switches S1 to S8. The capacitor CN1 is coupled between the node Nd1 and the output terminal O22. The capacitor CN2 is coupled between one end of the switches S1 and S2 and one end of the switches S3 and S4. The other terminal of the switch S1 is coupled to the output terminal O22, and the other terminal of the switch S2 is coupled to the output terminal O21. The other terminal of the switch S3 is coupled to the node Nd1, and the other terminal of the switch S4 is coupled to the node Pd 1. The switches S1 and S3 are turned on according to the clock signal Φ 2r, and the switches S2 and S4 are turned on according to the clock signal Φ 1 r.

The capacitor CP1 is coupled between the output terminal O21 and the node Pd 1. The capacitor CP2 is coupled between one end of the switches S5 and S6 and one end of the switches S7 and S8. The other terminal of the switch S5 is coupled to the node Pd1, and the other terminal of the switch S6 is coupled to the node Nd 1. The other terminal of the switch S7 is coupled to the output terminal O21, and the other terminal of the switch S8 is coupled to the output terminal O22. The switches S5 and S7 are turned on according to the clock signal Φ 2r, and the switches S6 and S8 are turned on according to the clock signal Φ 1 r.

In some embodiments, the plurality of capacitors CN1, CN2, CP1 and CP2 are configured to have the same capacitance value. As shown in fig. 3C, in normal operation, during the enabled period (e.g. high level period) of the clock signal Φ 2r, the switches S1, S3, S5 and S7 are turned on. Under this condition, as shown in fig. 3D, the capacitor CN1 and the capacitor CN2 operate as the capacitive circuit 131, and the capacitor CP1 and the capacitor CP2 operate as the capacitive circuit 132. Alternatively, as shown in fig. 3C, during the enabled period (e.g., high level period) of the clock signal Φ 1r, the switches S2, S4, S6, and S8 are turned on. Under this condition, as shown in fig. 3E, the capacitor CN1 and the capacitor CP2 operate as the capacitive circuit 131, and the capacitor CP1 and the capacitor CN2 operate as the capacitive circuit 132.

As described above, at the end of the enabling period T1 in fig. 3C, the clock signal Φ 1r remains high, and as shown in fig. 3E, the

capacitive circuits

131 and 132 coupled to the output terminals O21 and O22 of the amplifier 100 may have the output signals VO21 and VO22 generated at the time. For example, as described earlier, the output terminal O22 has the charge amount corresponding to VCM + Δ V remaining thereon, and the output terminal O21 has the charge amount corresponding to VCM- Δ V remaining thereon. In other words, the capacitive circuit 131 (i.e., the capacitors CN1 and CP2) has an amount of charge corresponding to + Δ V at the end coupled to the output terminal O22, and the capacitive circuit 132 (i.e., the capacitors CP1 and CN2) has an amount of charge corresponding to- Δ V at the end coupled to the output terminal O21.

Next, referring to fig. 3D, during the enabling period of the clock signal Φ 2r, the end of the capacitor CP2 that was previously coupled to the output terminal O22 is coupled to the output terminal O21. Thus, the capacitor CP2 supplies the output terminal O22 with the amount of charge corresponding to + Δ V. Equivalently, the amount of charge on capacitor CP1 corresponding to- Δ V and the amount of charge on capacitor CP2 corresponding to + Δ V will cancel each other out.

Similarly, during the enabled period of the clock signal Φ 2r, the terminal of the capacitor CN2, which is previously coupled to the output terminal O21, is coupled to the output terminal O22. Thus, the capacitor CN2 supplies the output terminal O21 with the amount of charge corresponding to- Δ V. Equivalently, the amount of charge on capacitor CN1 corresponding to + Δ V and the amount of charge on capacitor CN2 corresponding to- Δ V cancel each other out. In this way, the output terminals O21 and O22 of the amplifier 100 can be reset to the common mode voltage VCM.

In some embodiments, the period during which the clock signal Φ 1r or the clock signal Φ 2r is at the high level is longer than the period T1 and/or the period T2. In some embodiments, the clock signal Φ 1r or the clock signal Φ 2r may be non-overlapping clock signals. The setting manner of the clock signals is only an example, and the invention is not limited thereto.

Referring to fig. 4, fig. 4 is a flow chart of a reset method 400 according to some embodiments of the invention. For ease of explanation, reference is also made to fig. 3A-3E for a description of the relevant operation of amplifier 100. In some embodiments, the reset method 400 includes a plurality of operations S410, S420, S430, and S440.

In operation S410, the capacitors CN1 and CN2 operate as miller capacitors corresponding to the output terminal O22 according to the clock signal Φ 2 r. In operation S420, the capacitors CP1 and CP2 operate as miller capacitors corresponding to the output terminal O21 according to the clock signal Φ 2 r.

For example, as shown in fig. 3A to 3C, during the enabled period of the clock signal Φ 2r, the switches S1 and S3 are turned on, and the switches S5 and S7 are turned on. As shown in fig. 3D, the capacitive circuit 131 formed by the capacitor CN1 and the capacitor CN2 is coupled in parallel between the output terminal O22 and the node Nd1 to operate as a miller capacitor corresponding to the output terminal O22. Meanwhile, the capacitive circuit 132 formed by the capacitor CP1 and the capacitor CP2 is coupled in parallel between the output terminal O21 and the node Pd1 to operate as a miller capacitor corresponding to the output terminal O21.

With reference to fig. 4, in operation S430, the capacitors CN1 and CP2 operate as miller capacitors corresponding to the output terminal O22 according to the clock signal Φ 1 r. In operation S440, the capacitors CP1 and CN2 operate as miller capacitors corresponding to the output terminal O21 according to the clock signal Φ 1 r.

For example, as shown in fig. 3B, 3C and 3E, during the enabled period of the clock signal Φ 1r, the switches S2 and S4 are turned on, and the switches S6 and S8 are turned on. As a result, the capacitive circuit 131 formed by the capacitor CN1 and the capacitor CP2 is coupled in parallel between the output terminal O22 and the node Nd1 to operate as a miller capacitor corresponding to the output terminal O22. Meanwhile, the capacitive circuit 132 formed by the capacitor CP1 and the capacitor CN2 is coupled in parallel between the output terminal O21 and the node Pd1 to operate as a miller capacitor corresponding to the output terminal O21. In addition, as described above, under this condition, the output O21 and the output O22 of the amplifier 100 can be reset.

The steps of the reset method 400 are only exemplary and need not be performed in the order shown in this example. Various operations under the reset method 400 may be added, substituted, omitted, or performed in a different order, as appropriate, without departing from the manner of operation and scope of various embodiments of the disclosure.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A reset method for resetting an amplifier, the reset method comprising:

operating as a first miller capacitor corresponding to a first output terminal of the amplifier according to a first clock signal through a first capacitor and a second capacitor;

operating as a second miller capacitor corresponding to a second output terminal of the amplifier according to the first clock signal through a third capacitor and a fourth capacitor;

operating the first miller capacitor corresponding to the first output end according to a second clock signal through the first capacitor and the fourth capacitor; and

the third capacitor and the second capacitor are operated as the second miller capacitor corresponding to the second output end according to the second clock pulse signal.

2. An amplifier that is reset using the reset method according to claim 1, the amplifier comprising:

an output stage circuit including a first input terminal, a second input terminal, a first output terminal and a second output terminal; and

a compensation circuit, comprising:

a first capacitor coupled between the first input terminal and the second output terminal and configured to operate as a first miller capacitor;

a second capacitor coupled between the second input terminal and the first output terminal and configured to operate as a second miller capacitor;

a third capacitor; and

a fourth capacitor, wherein the third capacitor and the fourth capacitor are alternately operated as the first miller capacitor and the second miller capacitor according to at least one clock signal.

3. The amplifier of claim 2, wherein the compensation circuit further comprises:

a first set of switches, which is turned on according to a first clock signal of the at least one clock signal to couple the third capacitor between the first input terminal and the second output terminal, so as to operate as the first miller capacitor in cooperation with the first capacitor; and

and a second set of switches, which is turned on according to the first clock signal to couple the fourth capacitor between the second input terminal and the first output terminal, so as to operate as the second miller capacitor in cooperation with the second capacitor.

4. The amplifier of claim 3, wherein the first set of switches comprises a first switch and a second switch, the second set of switches comprises a third switch and a fourth switch, the first switch is coupled between the third capacitor and the second output terminal and turned on according to the first clock signal, the second switch is coupled between the third capacitor and the first input terminal and turned on according to the first clock signal, the third switch is coupled between the fourth capacitor and the second input terminal and turned on according to the first clock signal, and the fourth switch is coupled between the fourth capacitor and the first output terminal and turned on according to the first clock signal.

5. The amplifier of claim 3, wherein the compensation circuit further comprises:

a third set of switches, which is conducted according to a second clock signal of the at least one clock signal to couple the third capacitor between the second input terminal and the first output terminal, so as to operate as the second miller capacitor in cooperation with the third capacitor; and

and a fourth set of switches, which is turned on according to the second clock signal to couple the fourth capacitor between the first input terminal and the second output terminal, so as to operate as the first miller capacitor in cooperation with the first capacitor.

6. The amplifier of claim 5, wherein the third set of switches comprises a first switch and a second switch, the fourth set of switches comprises a third switch and a fourth switch, the first switch is coupled between the third capacitor and the first output terminal and is turned on according to the second clock signal, the second switch is coupled between the third capacitor and the second input terminal and is turned on according to the second clock signal, the third switch is coupled between the fourth capacitor and the first input terminal and is turned on according to the second clock signal, and the fourth switch is coupled between the fourth capacitor and the second output terminal and is turned on according to the second clock signal.

7. The amplifier of claim 3, further comprising:

an input stage circuit, which includes a third input terminal, a fourth input terminal, a third output terminal and a fourth output terminal,

the third input terminal is used for receiving a first input signal, the fourth input terminal is used for receiving a second input signal, the third output terminal is coupled to the first input terminal, and the fourth output terminal is coupled to the second input terminal.

8. The amplifier of claim 7, further comprising:

a plurality of sampling switches; and

a plurality of sampling capacitors coupled to the third input terminal, the fourth input terminal, the first output terminal and the second output terminal,

the sampling switches are conducted according to a third clock signal and a fourth clock signal to operate in a first mode or a second mode with the sampling capacitors, when operating in the first mode, the sampling capacitors are used for respectively sampling the first input signal and the second input signal, and when operating in the second mode, the input stage circuit and the output stage circuit are used for amplifying the sampled first input signal and the sampled second input signal.

9. The amplifier of claim 8, wherein an enable period of the first clock signal or the second clock signal is greater than an enable period of the third clock signal or the fourth clock signal.

10. An amplifier reset using the reset method of claim 1, the amplifier comprising:

an output stage circuit including a plurality of input terminals and a plurality of output terminals; and

a compensation circuit coupled between the input terminals and the output terminals for operating as a first miller capacitor and a second miller capacitor according to a first clock signal and a second clock signal,

the compensation circuit comprises a first capacitor, a second capacitor, a third capacitor and a fourth capacitor, wherein the first capacitor and the second capacitor operate as the first miller capacitor and the third capacitor and the fourth capacitor operate as the second miller capacitor during an enabling period of the first clock signal, the first capacitor and the third capacitor operate as the first miller capacitor and the fourth capacitor and the second capacitor operate as the second miller capacitor during an enabling period of the second clock signal.