JP6155918B2 - Sample and hold circuit, analog-digital conversion circuit, and digital control circuit - Google Patents

Description

  The present invention relates to a sample-and-hold circuit that samples and holds an analog input signal, and more particularly to a bottom-plate sampling type sample-and-hold circuit.

  Most high-speed, high-precision analog-to-digital converters (AD converters) sample and hold an analog input signal, and among them, the bottom plate sampling method has been proposed as a particularly high-precision sample-and-hold circuit ( For example, refer nonpatent literature 1).

Akira Matsuzawa, “Analog RFCMOS Integrated Circuit Design”, Baifukan Co., Ltd., January 15, 2010, p. 258-260

  However, in the prior art, in order to obtain a differential signal, a CMFB (common-mode feedback) circuit is used or two stages of amplifiers are connected in series to generate outputs that are added to and subtracted from the intermediate potential, respectively. However, there are problems such as the input / output dynamic range being limited and the occurrence of an output phase difference.

  The object of the present invention is to solve the above-mentioned problems of the prior art in view of the above-mentioned problems, to set a wide dynamic range, to prevent occurrence of a phase difference, and to obtain a high-speed and high-accuracy differential signal. To provide a sample and hold circuit.

  The sample-and-hold circuit of the present invention is a sample-and-hold circuit that samples and holds an analog input signal and outputs a differential signal. The sample-and-hold circuit samples and holds a first reference voltage. A superimposed circuit based on the hold circuit and the second sample and hold circuit, the analog input signal and the second reference voltage is generated, and the generated superimposed voltage is used as the first sample and hold circuit and the second sample. A voltage superimposing circuit that superimposes the first reference voltage held in the hold circuit, and the first sample and hold circuit is generated from the held first reference voltage by the voltage superimposing circuit. The output voltage on the low potential side in which the superimposed voltage is reduced is output, and the second sample and hold circuit And outputting the high potential side of the output voltage with the increased superposed voltage generated by the voltage superimposing circuit from the first reference voltage.

  According to the present invention, the superimposed voltage based on the analog input signal and the second reference voltage is added to or subtracted from the first reference voltage held by the first sample and hold circuit and the second sample and hold circuit. Therefore, a wide dynamic range can be set by setting the first reference voltage, the occurrence of a phase difference can be prevented, and a high-speed and highly accurate differential signal can be obtained.

It is a circuit block diagram which shows the circuit structure of embodiment of the sample hold circuit based on this invention. 2 is a timing chart showing switch switching timings in the sample and hold circuit shown in FIG. 1. FIG. 2 is a circuit configuration diagram showing a specific circuit configuration of the sample and hold circuit shown in FIG. 1. FIG. 2 is a circuit configuration diagram illustrating a configuration example of a switch SW3 illustrated in FIG. FIG. 2 is a schematic diagram illustrating a configuration example of an AD converter using the sample and hold circuit illustrated in FIG. 1. It is the schematic which shows the structural example of the digital control circuit using the AD converter shown in FIG. 5 which controls the output voltage of a switching power supply circuit. It is a circuit block diagram which shows the modification of capacitor | condenser C2_1 shown in FIG. It is a circuit block diagram which shows the modification of capacitor | condenser C1_1 and C2_1 shown in FIG.

  In the sample and hold circuit 1 of the present embodiment, referring to FIG. 1, two single-ended sample and hold circuits, bottom plate sampling circuits L1 and L2, are connected by a switched capacitor circuit L3.

  The bottom plate sampling circuit L1 includes an operational amplifier I1, a capacitor C1_1, and switches SW2_1, SW4_1, and SW5_1. A switch SW2_1 and a capacitor C1_1 are connected in series between the first reference voltage Vref1 and the inverting input terminal of the operational amplifier I1. A switch SW4_1 is connected between the output terminal of the operational amplifier I1 from which the output voltage OUT_L on the low potential side is output, the inverting input terminal of the operational amplifier I1, the capacitor C1_1, and the connection point X_1. A switch SW5_1 is connected between the output terminal and a connection point Y_1 between the switch SW2_1 and the capacitor C1_1.

  The bottom plate sampling circuit L2 has the same configuration as the bottom plate sampling circuit L1, and includes an operational amplifier I2, a capacitor C1_2, and switches SW2_2, SW4_2, and SW5_2. A switch SW2_2 and a capacitor C1_2 are connected in series between the first reference voltage Vref1 and the inverting input terminal of the operational amplifier I2. A switch SW4_2 is connected between the output terminal of the operational amplifier I2 from which the output voltage OUT_H on the high potential side is output, the inverting input terminal of the operational amplifier I2, the capacitor C1_2, and the connection point X_2. A switch SW5_2 is connected between the output terminal and a connection point Y_2 between the switch SW2_2 and the capacitor C1_2.

  Note that the non-inverting input terminal of the operational amplifier I1 and the non-inverting input terminal of the operational amplifier I2 are respectively connected to the reference voltage VPLUS1 and the reference voltage VPLUS2 as shown in FIG. The reference voltage VPLUS1 and the reference voltage VPLUS2 only need to apply a reference voltage that operates stably to the operational amplifier I1 and the operational amplifier I2, respectively, and an arbitrary bias may be applied. However, for simplification, VPLUS1 = By setting VPLUS2 = Vref1, stable circuit operation can be obtained.

  The switched capacitor circuit L3 includes capacitors C2_1 and C2_2 and switches SW1_1, SW1_2 and SW3. A capacitor C2_1, a switch SW3, and a capacitor C2_2 are connected between a connection point Y_1 between the switch SW2_1 and the capacitor C1_1 in the bottom plate sampling circuit L1, and a connection point Y_2 between the switch SW2_2 and the capacitor C1_2 in the bottom plate sampling circuit L2. Connected in series. A connection point Z_1 between the capacitor C2_1 and the switch SW3 is connected to an input voltage VIN, which is an analog input signal to the sample and hold circuit 1, via the switch SW1_1. A connection point Z_2 between the switch SW3 and the capacitor C2_2 is The second reference voltage Vref2 is connected via the switch SW1_2.

Next, the operation of the sample and hold circuit 1 of the present embodiment will be described in detail with reference to FIG.
Referring to FIG. 2, first, the switches SW1_1 and SW1_2, the switches SW2_1 and SW2_2, and the switches SW4_1 and SW4_2 are turned on at the time T1 when the sampling of the analog input signal is started. This corresponds to the initial charge charge timing of the input voltage VIN and the second reference voltage Vref2 in bottom plate sampling. At this time, the switch SW3 and the switches SW5_1 and SW5_2 are off. By turning on the switches SW4_1 and SW4_2, the non-inverting input terminal of the operational amplifier I1 and the non-inverting input terminal of the operational amplifier I2 operate as virtual ground points. Accordingly, the first reference voltage Vref1 is applied to the capacitors C1_1 and C1_2, and the first reference voltage Vref1 is sampled by the bottom plate sampling circuits L1 and L2. Further, a voltage difference between the input voltage VIN and the first reference voltage Vref1 is applied to the capacitor C2_1, and a voltage difference between the first reference voltage Vref1 and the second reference voltage Vref2 is applied to the capacitor C2_2. It will be in the state.

  Next, the switches SW1_1 and SW1_2 are turned off at a time T2 after a lapse of a predetermined time from the time T1, and the switches SW2_1 and SW2_2 are turned off at a time T3 after the lapse of a predetermined time from the time T2. The reason why the switches SW1_1 and SW1_2 are turned off first is to prevent the loss of charge during the transition of the switches. As a result, the first reference voltage Vref1 is held by the bottom plate sampling circuits L1 and L2, and the input voltage Vin and the second reference voltage Vref2 are held at both ends of the switch SW3.

  Next, when the switch SW3 is turned on at time T4 after a predetermined time has elapsed from time T3, a superimposed voltage based on the input voltage Vin and the second reference voltage Vref2 is generated, and the generated superimposed voltage is converted into a bottom plate sampling circuit. Superposed on the first reference voltage Vref1 held by L1 and L2. That is, when capacitor C1_1 = capacitor C1_2, capacitor C2_1 = capacitor C2_2, and C1_1≈C2_1 (value obtained by correcting the parasitic capacitance), the voltage across switch SW3 is (Vin−Vref2) / 2 due to capacitance distribution. Become. In the present embodiment, the second reference voltage Vref2 is assumed to be 0 V based on the ground level, and the voltage across the switch SW3 is assumed to be Vin / 2. In this case, ½ of the voltage across the switch SW3 is the superimposed voltage. The voltage at the connection point Y_1 between the capacitor C1_1 and the capacitor C2_1 and the voltage at the connection point Y_2 between the capacitor C1_2 and the capacitor C2_2, that is, the first reference voltage Vref1 held by the bottom plate sampling circuits L1 and L2 is: The superimposed voltage (Vin / 4) is superimposed by voltage division, and Vin / 4 is added or subtracted with reference to the first reference voltage Vref1. That is, the voltage at the connection point Y_1 between the capacitor C1_1 and the capacitor C2_1 is Vref1-Vin / 4, and the voltage at the connection point Y_2 between the capacitor C1_2 and the capacitor C2_2 is Vref1 + Vin / 4. As a result, a differential voltage based on the first reference voltage Vref1 is obtained.

  Next, after the switches SW4_1 and SW4_2 are turned off at time T5, the switches SW5_1 and SW5_2 are turned on at time T6. As a result, the capacitor C1_1 is connected between the output terminal and the non-inverting input terminal of the operational amplifier I1, and the capacitor C1_2 is connected between the output terminal and the non-inverting input terminal of the operational amplifier I2, and stored in the capacitor C1_1 and the capacitor C1_2. The charge is held. Therefore, Vref1−Vin / 4 is output as the low potential side output voltage OUT_L from the output terminal of the operational amplifier I1, and Vref1 + Vin / 4 is output as the high potential side output voltage OUT_H from the output terminal of the operational amplifier I2. . Note that the switch SW3 and the switches SW5_1 and SW5_2 are turned off immediately before the time T1 when the next analog input signal sampling is started.

  As described above, the capacitors C1_1 to C2_2 described above are capacitances used in bottom plate sampling, and the divided voltage at the connection points Y_1 to Z_2 is determined by the capacitance ratio of the capacitors C1_1 to C2_2. Further, the switches SW1_1 to SW5_2 function as switches for generating bottom plate sampling and voltage division by the capacitors C1_1 to C2_2, and by controlling the on / off of the switches SW1_1 to SW5_2 at the above timing, A differential signal that is not affected by the parasitic capacitance present in the operational amplifiers I1 and I2 can be easily generated.

  The differential signals output from the operational amplifiers I1 and I2 generate a low voltage (output voltage OUT_L) and a high voltage (output voltage OUT_H) with reference to the first reference voltage Vref1. Therefore, the dynamic range can be easily set by setting the first reference voltage Vref1. Further, setting the first reference voltage Vref1 to ½ of the power supply voltage Vdd is preferable because the dynamic range of the output can be maximized.

  The second reference voltage Vref2 may be higher, lower, or equal to the first reference voltage Vref1, but may be the lowest potential of the circuit (0V in the case of ground level reference) or the highest potential as described above. It is desirable that the voltage is lower or higher than the input voltage Vin, such as (power supply voltage Vdd). That is, when the input voltage Vin changes between the second reference voltage Vref2 and the output voltage OUT_L and the output voltage OUT_H are reversed, a complicated circuit configuration is required in the subsequent stage. Therefore, the second reference voltage Vref2 is set to a voltage at which the output voltage OUT_L and the output voltage OUT_H do not reverse, that is, a voltage lower than the lowest potential that the input voltage Vin can take, or the highest potential that the input voltage Vin can take. Should be set to a higher voltage.

  Note that in this embodiment, the operation is described as capacitor C1_1 = capacitor C1_2, capacitor C2_1 = capacitor C2_2, and C1_1≈C2_1. However, the capacitance ratio of the capacitor C1_1, the capacitor C2_1, the capacitor C2_2, and the capacitor C1_2 The dynamic range can be easily changed by the combination.

  FIG. 3 shows a specific circuit configuration of the sample and hold circuit 1 using CMOS operational amplifiers as the operational amplifiers I1 and I2. In FIG. 3, MP1 to MP5 are current mirror circuits based on MP1, and supply current to operational amplifiers I1 and I2. Further, as the switch SW3, in order to reduce the influence of clock feedthrough during switching, it is preferable to employ the switch SW3a shown in FIG. 4A or the switch SW3b shown in FIG. 4B. The clock feedthrough is a phenomenon in which the parasitic capacitance of each switch is superimposed on the capacitors C1_1 to C2_2 and affects the output.

  As shown in FIG. 4A, the switch SW3a has a p-channel MOSFET (hereinafter referred to as a PMOS switch) functioning as a switch element and an n-channel MOSFET (hereinafter referred to as an NMOS switch) connected in parallel. CMOS switch. On both sides of the PMOS switch, that is, the drain and the source, a p-channel MOSFET (hereinafter referred to as PMOS), which is driven by a clock CK complementary to the clock CKB that drives the gate of the PMOS switch and whose source and drain are short-circuited. (Referred to as a dummy switch). Note that the PMOS dummy switch has approximately half the size of the PMOS switch. Further, on both sides of the NMOS switch, that is, the drain and the source, an n-channel MOSFET (hereinafter referred to as NMOS) that is driven by a clock CKB that is complementary to the clock CK that drives the gate of the NMOS switch and whose source and drain are short-circuited. (Referred to as a dummy switch). The NMOS dummy switch has half the size of the NMOS switch.

  With this configuration, when the PMOS switch is turned off, the charge stored in the parasitic capacitance is released, but the PMOS dummy switch connected to the drain and source of the PMOS switch is turned on and the charge discharged from the PMOS switch. Is absorbed by the PMOS dummy switch. Similarly, when the NMOS switch is turned off, the charge stored in the parasitic capacitance is released, but the NMOS dummy switch connected to the drain and source of the NMOS switch is turned on, and the charge discharged from the NMOS switch is changed. Absorbed by NMOS dummy switch. Therefore, the influence of clock feedthrough during switching can be reduced.

  As shown in FIG. 4 (b), the switch SW3b is connected in series with the switch SW3a shown in FIG. 4 (a). With this configuration, when the PMOS switch and the NMOS switch are off, the connection point A between the switch SW3a and the switch SW3a is in a floating state. Therefore, the junction capacitance Cj of the PMOS switch and the NMOS switch has a temperature characteristic and changes depending on the temperature, but when the PMOS switch and the NMOS switch are turned off, the error amount of the junction capacitance Cj is accumulated at the connection point A where the junction is floating. I can leave. The error of the junction capacitance Cj stored at the connection point A is released from the connection point A when the PMOS switch and the NMOS switch are turned on, and the change in the junction capacitance Cj due to temperature can be canceled.

  FIG. 5 shows an example of an AD converter 10 using the sample and hold circuit 1 of the present embodiment. The AD converter 10 shown in FIG. 5 is a differential type successive approximation type. A low-pass filter (LPF) L10, the sample-and-hold circuit 1 of the present embodiment, a capacitor ladder circuit L11, a comparator (Comp) L12, and a control logic circuit L13 are provided. Yes.

  The analog input signal input from Vin is input to the sample and hold circuit 1 of the present embodiment through the low-pass filter L10. Then, the differential signals (OUT_L, OUT_H) output from the sample and hold circuit 1 are input to the capacitor ladder circuit L11, and the capacitor ladder circuit L11 and the comparator L12 are controlled by the control logic circuit L13. The successive comparison of the voltage value of Vin sampled by the hold circuit 1 is performed, and the AD signal is output from the control logic circuit L13.

  The capacitor ladder circuit L11 is bit-controlled by a CMOS switch. However, the single-ended configuration is easily affected by parasitic capacitance of the CMOS switch and cannot cope with high-precision AD conversion. In contrast, by adopting a configuration that uses differential signals (OUT_L, OUT_H) output from the sample-and-hold circuit 1, it is possible to reduce the influence of the parasitic capacitance of the CMOS switch and so on, thus enabling highly accurate AD conversion. It becomes.

  The AD converter 10 as shown in FIG. 5 using the sample and hold circuit 1 of the present embodiment can be used in a digital control circuit for controlling the output voltage of the switching power supply circuit L20 as shown in FIG. That is, in recent years, the feedback control of the analog output voltage Vo has been digitized. The analog output voltage Vo is converted into a digital signal by the AD converter 10, an error signal is generated by a digital error amplifier (digital error-amp) L21 based on the converted digital signal, and a digital PWM (digital PWM) is generated based on the generated error signal. PWM) circuit L22 controls the switching operation of switching power supply circuit L20. According to the AD converter 10 using the sample and hold circuit 1 of the present embodiment, AD conversion with high accuracy is possible, and therefore the analog output voltage Vo can be controlled with high accuracy.

  FIG. 7 shows an example in which a variable capacitor C2_1 ′ whose capacity can be changed is connected instead of the capacitor C2_1 shown in FIG. 1 connected between the connection point Y_1 and the connection point Z_1 of the sample and hold circuit 1. It is shown. The variable capacitor C2_1 ′ includes a capacitor C2_1_1 to a capacitor C2_1_4, and a switch SW6_1_2 to a switch SW6_1_4. A series circuit composed of a capacitor C2_1_3 and a switch SW6_1_3 and a series circuit composed of a capacitor C2_1_4 and a switch SW6_1_4 are connected in parallel. With this configuration, the capacitance between the connection point Y_1 and the connection point Z_1 is changed by switching the on / off state of the switches SW6_1_2 to SW6_1_4. Therefore, the on / off control of the switches SW6_1_2 to SW6_1_4 can change the combination of the capacitance ratios of the capacitor C1_1, the variable capacitor C2_1 ′, the variable capacitor C2_2, and the capacitor C1_2, and easily change the dynamic range. be able to. A variable capacitor C2_2 ′ having the same configuration as that of the variable capacitor C2_1 ′ is connected between the connection point Y_2 and the connection point Z_2 of the sample and hold circuit 1 so that variable capacitor C2_1 ′ = variable capacitor C2_2 ′ is controlled. This is preferable because the differential signals (OUT_L, OUT_H) have the same gain across the first reference voltage Vref1.

  Thus, since the dynamic range can be easily changed, the gain can be switched according to the magnitude of the fluctuation of the input voltage VIN. That is, when the fluctuation of the input voltage VIN is large, the gain is reduced by widening the dynamic range, and when the fluctuation of the input voltage VIN is small, the gain is increased by narrowing the dynamic range. Thus, the AD conversion accuracy can be easily switched. For example, when the AD converter 10 is used as a digital control circuit for controlling the output voltage of the switching power supply circuit L20 as shown in FIG. 6, the dynamic range is wide during the period when the analog output voltage Vo is not stable when the power is turned on. By reducing the gain, the analog output voltage Vo is quickly stabilized, and after the analog output voltage Vo is stabilized, the dynamic range is narrowed to increase the gain, and the analog output voltage Vo can be increased with high accuracy. Can be controlled. Even when the gain of AD conversion is fixed, the variable capacitor C2_1 'is provided, and the switch SW6_1_2 to the switch SW6_1_4 can be turned on and off to be used for trimming such as variations in the manufacturing process. Further, a switch that is turned on / off in synchronization with the switch SW6_1_2 to the switch SW6_1_4 may be connected between each of the capacitor C2_1_2 to the capacitor C2_1_4 and the connection point Z_1. If comprised in this way, a highly accurate differential signal can be obtained.

  In FIG. 8, in the sample and hold circuit 1, a capacitor C <b> 1 </ b> _ <b> 1 that cancels the influence of the parasitic capacitance from the periphery is used instead of the capacitor C <b> 1 </ b> _ 1 shown in FIG. 1 connected between the connection point X_1 and the connection point Y_ <b> 1. An example in which a capacitor C2_1 '' that cancels the influence of parasitic capacitance from the periphery is connected instead of the capacitor C2_1 shown in FIG. 1 connected between the connection point Y_1 and the connection point Z_1. It is shown. The capacitor C1_1 'and the capacitor C2_1 "are configured to correct the influence of the parasitic capacitance from the periphery by a plurality of capacitors having different connection directions. That is, the capacitor is formed between different substrates on the IC or using the capacitance of the wiring metal, but the capacitor is also formed in a direction to cancel the parasitic. A capacitor C1_1 ′ and a capacitor C2_1 ″ illustrated in FIG. 8 are formed by connecting two capacitors formed between the A-layer substrate and the B-layer substrate in different directions between the connection point X_1 and the connection point Y_1. Is connected. Thereby, the influence of the parasitic capacitance from the periphery can be reduced. Note that the connection direction to be corrected is not limited to the reverse direction, and if there are a plurality of different vectors (for example, capacitances between the substrates and the wirings Metal), it is preferable to connect the capacitors in the canceling direction corresponding to the number.

As described above, according to the present embodiment, the sample-and-hold circuit 1 that samples and holds the input voltage VIN and outputs a differential signal, the sample-and-hold circuit that samples and holds the first reference voltage Vref1. The bottom reference plate sampling circuits L1 and L2, the superimposed voltage based on the input voltage VIN and the second reference voltage Vref2 are generated, and the generated reference voltage is held in the bottom plate sampling circuits L1 and L2. The bottom plate sampling circuit L1 includes a switched capacitor circuit L3 superimposed on the voltage Vref1, and the bottom plate sampling circuit L1 outputs a low-potential-side output voltage obtained by reducing the superimposed voltage generated by the switched capacitor circuit L3 from the held first reference voltage Vref1. OUT_L is output, bottom plate sampling times L2 is configured to output a hold to said first high-potential side of the output voltage OUT_H from the reference voltage Vref1 increased the superimposed voltage generated by the switched capacitor circuit L3.
With this configuration, the superimposed voltage based on the input voltage VIN and the second reference voltage Vref2 is added to and subtracted from the first reference voltage Vref1 held by the bottom plate sampling circuit L1 and the bottom plate sampling circuit L2, and then output. Since the dynamic range can be easily set by setting the first reference voltage Vref1, a wide dynamic range can be set and the occurrence of a phase difference can be prevented, and a high-speed and highly accurate differential signal can be obtained. Can do. In addition, since a sample-and-hold differential output can be obtained without using a CMFB circuit, the circuit configuration can be simplified. Further, although two single-ended circuit configurations are used, there is no phase shift and the design can be made independently, so that the circuit design is easy and the power consumption can be reduced.

Further, according to the present embodiment, the bottom plate sampling circuit L1 is a single-ended bottom plate that holds the first reference voltage Vref1 by the capacitor C1_1 (first capacitor) connected to the inverting input terminal of the operational amplifier I1. The bottom plate sampling circuit L2 is a single-ended bottom plate sampling circuit that holds the first reference voltage Vref1 by a capacitor C1_2 (second capacitor) connected to the inverting input terminal of the operational amplifier I2. The switched capacitor circuit L3 includes a capacitor C2_1 (third capacitor) in which the input voltage VIN is sampled and held, a capacitor C2_2 (fourth capacitor) in which the second reference voltage Vref2 is sampled and held, and a capacitor A switch SW3 connected between a connection point Z_1 connected to the input voltage VIN when sampling C2_1 and a connection point Z-2 connected to the second reference voltage Vref2 when sampling the capacitor C2_2; A series circuit composed of C2_1, switch SW3, and capacitor C2_2 is connected to a connection point Y_1 that is connected to the first reference voltage Vref1 when the capacitor C1_1 is sampled in the bottom plate sampling circuit L1, and a circuit in the bottom plate sampling circuit L2. It is connected between the connection point Y_2 that at the time of sampling of the capacitor C1_2 is connected to first reference voltage Vref1.
With this configuration, the gain can be easily changed depending on the capacitance ratio of the capacitors C1_1 to C2_2.

Furthermore, according to the present embodiment, both or either of the capacitor C2_1 and the capacitor C2_2 are configured by a variable capacitor (variable capacitor C2_1 ′) whose capacity can be changed.
With this configuration, the gain can be easily changed by changing the capacitance of the variable capacitor (variable capacitor C2_1 ′).

Furthermore, according to the present embodiment, the capacitors C1_1 to C2_2 are composed of a plurality of capacitors (capacitor C1_1 ′ and capacitor C2_1 ″) connected in a direction to cancel the influence of the parasitic capacitance from the periphery. .
With this configuration, the influence of parasitic capacitance from the periphery can be reduced.

Further, according to the present embodiment, the switch SW3a of the switched capacitor circuit L3 is a CMOS switch in which a PMOS switch and an NMOS switch are connected in parallel, and the gate of the PMOS switch is driven on both sides of the PMOS switch. A PMOS dummy switch whose source and drain are short-circuited is connected with a clock complementary to the clock to be connected, and is driven with a clock complementary to the clock for driving the gate of the NMOS switch on both sides of the NMOS switch. The NMOS dummy switch whose source and drain are short-circuited is connected.
With this configuration, the influence of clock feedthrough during switching can be reduced.

Furthermore, according to the present embodiment, the switch SW3b of the switched capacitor circuit L3 is connected in series with the switch SW3a shown in FIG.
With this configuration, it is possible to cancel the change due to the temperature of the junction capacitance Cj due to the temperature.

Furthermore, according to the present embodiment, the first reference voltage Vref1 is set to ½ of the power supply voltage Vdd.
This configuration is suitable because it can be used by bottom-plate sampling in Rail-to-Rail, and the dynamic range of output can be maximized.

Furthermore, according to the present embodiment, the second reference voltage Vref2 is set to a voltage that is lower or higher than the input voltage VIN. Preferably, the second reference voltage Vref2 is set to the lowest potential or the highest potential.
With this configuration, since the inversion of the output voltage OUT_L and the output voltage OUT_H does not occur, the circuit configuration of the subsequent stage can be simplified.

  As mentioned above, although this invention was demonstrated by specific embodiment, the said embodiment is an example and it cannot be overemphasized that it can change and implement in the range which does not deviate from the meaning of this invention.

1 Sample and Hold Circuit 10 AD Converter C1_1 to C2_2 Capacitor C2_1 'Variable Capacitor I1, I2 Op Amp L1, L2 Bottom Plate Sampling Circuit L3 Switched Capacitor Circuit L10 Low Pass Filter L11 Capacitor Ladder Circuit L12 Comparator L13 Control Logic Circuit L20 Switching Power Supply Circuit L21 Digital error amplifier L22 Digital PWM circuit SW1_1 to SW5_2 switch SW3a, SW3b switch SW6_2 to SW6_4 switch

Claims (11)

A sample and hold circuit that samples and holds an analog input signal and outputs a differential signal,
A single-ended first sample and hold circuit and a second sample and hold circuit that sample and hold a first reference voltage;
A superimposed voltage based on the analog input signal and a second reference voltage is generated, and the generated superimposed voltage is held in the first sample and hold circuit and the second sample and hold circuit. A voltage superimposing circuit for superimposing on the voltage,
The first sample-and-hold circuit outputs a low-potential-side output voltage obtained by reducing the superimposed voltage generated by the voltage superimposing circuit from the held first reference voltage, and the second sample-and-hold circuit outputs the low-potential-side output voltage. The hold circuit outputs a high-potential-side output voltage obtained by increasing the superimposed voltage generated by the voltage superimposing circuit from the held first reference voltage.   The first sample and hold circuit is a single-ended bottom plate sampling circuit that holds the first reference voltage by a first capacitor connected to an inverting input terminal of a first amplifier. 2. The sample-and-hold circuit is a single-ended bottom plate sampling circuit that holds the first reference voltage by a second capacitor connected to an inverting input terminal of a second amplifier. Sample-and-hold circuit. The voltage superimposing circuit includes a third capacitor in which the analog input signal is sampled and held;
A fourth capacitor in which the second reference voltage is sampled and held;
A switch connected between a connection point connected to the analog input signal when sampling the third capacitor and a connection point connected to the second reference voltage when sampling the fourth capacitor; And
A connection point in which a series circuit including the third capacitor, the switch, and the fourth capacitor is connected to the first reference voltage when the first capacitor is sampled in the first sample and hold circuit. 3. The sample according to claim 2, wherein the sample is connected to a connection point connected to the first reference voltage when the second capacitor is sampled in the second sample and hold circuit. -Hold circuit.   4. The sample-and-hold circuit according to claim 3, wherein both or one of the third capacitor and the fourth capacitor is a variable capacitor whose capacity can be changed.   At least one of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor is a plurality of capacitors connected in a direction to cancel the influence of parasitic capacitance from the periphery. 5. The sample and hold circuit according to claim 3, wherein each of the sample and hold circuits is configured.   The switch of the voltage superimposing circuit is a CMOS switch in which a PMOS switch and an NMOS switch are connected in parallel, and is driven on both sides of the PMOS switch by a clock complementary to a clock for driving the gate of the PMOS switch. A PMOS dummy switch whose source and drain are short-circuited is connected, and both sides of the NMOS switch are driven by a clock complementary to the clock driving the gate of the NMOS switch. The source and drain are short-circuited. 6. The sample and hold circuit according to claim 3, further comprising an NMOS dummy switch connected thereto.   7. The sample and hold circuit according to claim 5, wherein the switch of the voltage superimposing circuit includes two CMOS switches connected in series.   8. The sample and hold circuit according to claim 1, wherein the first reference voltage is set to ½ of a power supply voltage. 9. The second reference voltage is set to a voltage lower than a lowest potential of the analog input signal or a voltage higher than a highest potential of the analog input signal . The sample and hold circuit described in 1. Analog-to-digital conversion circuit and performing an analog-to-digital conversion on the basis of the differential signal output from the sample-and-hold circuit according to any one of claims 1 to 9. 11. A digital control circuit, wherein the output voltage of the switching power supply is digitized by the analog-to-digital conversion circuit according to claim 10 , and the operation of the switching power supply is controlled based on the digitized output voltage.

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