KR101203116B1 - Solar cell comprising an epitaxially grown semiconductor layer and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a solar cell and a manufacturing method thereof. The solar cell comprises i) a first electrode comprising a substrate and a plurality of conductive structures located on a plate surface of the substrate and spaced apart from each other, ii) a plurality of semiconductor layers stacked overlying and covering the plurality of conductive structures, iii) A second electrode covering the plurality of semiconductor layers, and iv) a resin pinned layer covering the second electrode. The plurality of semiconductor layers includes: i) a first semiconductor layer in contact with the first electrode, and ii) a second semiconductor layer located on the first semiconductor layer and in contact with the second electrode. The first semiconductor layer has a nonuniform thickness.

Description

Solar cell comprising epitaxially grown semiconductor layer and manufacturing method thereof {SOLAR CELL COMPRISING AN EPITAXIALLY GROWN SEMICONDUCTOR LAYER AND METHOD FOR MANUFACTURING THE SAME}

The present invention relates to a solar cell and a method of manufacturing the same. More particularly, the present invention relates to a solar cell including epitaxially grown semiconductor layers and a method of manufacturing the same.

Recently, due to resource depletion and rising resource prices, clean energy research and development has been actively conducted. Examples of clean energy include solar energy, wind energy and tidal energy. In particular, research and development of solar cells are being made continuously in order to use solar energy efficiently.

Solar cells are devices that convert the sun's light energy into electrical energy. When sunlight shines on a solar cell, electrons and holes are generated inside the solar cell. The generated electrons and holes move to the P pole and the N pole included in the solar cell, and the electric current flows because all positions occur between the P pole and the N pole.

It is to provide a solar cell that can be manufactured using a simple process and excellent in photoelectric conversion efficiency and light absorption. It is also an object of the present invention to provide a method of manufacturing the solar cell.

A solar cell according to an embodiment of the present invention comprises: i) a first electrode comprising a substrate and a plurality of conductive structures disposed on a plate surface of the substrate and spaced apart from each other, ii) being laminated while covering a plurality of conductive structures, and epitaxially A plurality of grown semiconductor layers, iii) a second electrode covering the plurality of semiconductor layers, and iv) a resin fixing layer covering the second electrode. The plurality of semiconductor layers includes: i) a first semiconductor layer in contact with the first electrode, and ii) a second semiconductor layer located on the first semiconductor layer and in contact with the second electrode. The first semiconductor layer has a nonuniform thickness.

The first semiconductor layer may include a plurality of voids. The bonding strength between the first semiconductor layer and the first electrode may be greater than the bonding strength between the second semiconductor layer and the second electrode. A first bond strength between the semiconductor layer and the first electrode may be 100N / cm ² to 1000N / cm ^2.

The plurality of conductive structures may include i) a plurality of first conductive structures, and ii) a second conductive structure having a width greater than the width of the first conductive structure. The solar cell according to the exemplary embodiment of the present invention may further include a third electrode formed on the second conductive structure and in contact with the second electrode. The solar cell according to the exemplary embodiment of the present invention includes a plurality of third conductive structures positioned on the plate surface in a direction crossing the direction in which the second conductive structure extends, and the plurality of third conductive structures are spaced apart from each other and have a partition shape. Can have

The first semiconductor layer may be a p-type semiconductor layer, and the second semiconductor layer may be an n-type semiconductor layer. The first electrode may be opaque than the second electrode.

A method of manufacturing a solar cell according to an embodiment of the present invention, i) providing a template comprising a substrate and a plurality of structures located on a plate surface of the substrate and spaced apart from each other, ii) a first epi covering the template Providing a tactile layer, iii) converting the first epitaxial layer into a porous layer, iv) providing a second epitaxial layer over the porous layer, v) converting the second epitaxial layer into a plurality of semiconductor layers Converting to, vi) providing a conductor over the plurality of semiconductor layers, vii) providing a resin pinning layer covering the conductor, viii) removing the porous layer, and ix) the plurality of semiconductor layers Providing another conductor below.

Removing the porous layer may include: i) forming a hole in the lower portion of the template to expose the porous layer to the outside, and ii) etching the porous layer by injecting an etchant into the hole. In the exposing the porous layer to the outside, the hole may be formed at a position corresponding to the spaced space of the plurality of structures along a direction parallel to the direction in which the plurality of structures extends. In the step of converting the first epitaxial layer to the porous layer, the porosity of the porous layer may be 10% to 70%. Providing a second epitaxial layer and converting the second epitaxial layer into a plurality of semiconductor layers may be simultaneously performed.

Providing the template includes providing a plurality of structures, wherein providing the plurality of structures comprises: i) providing first spaced apart structures, and ii) spaced apart from the first structures, Providing a second structure having a width greater than the width of the first structure. The first structures may have a rod shape, and the second structures may have a partition wall shape.

The method of manufacturing a solar cell according to an embodiment of the present invention may further include providing a plurality of third structures extending in a direction crossing the direction in which the second structure extends and having a partition wall shape. According to an exemplary embodiment of the present invention, a method of manufacturing a solar cell includes a second outgoing conductor connected to a conductor between providing a conductor on a plurality of semiconductor layers and providing a resin fixing layer covering the conductor. It may further comprise providing over the structure.

Converting the second epitaxial layer into a plurality of semiconductor layers may include i) providing a p-type semiconductor layer, and ii) providing an n-type semiconductor layer over the p-type semiconductor layer. The method of manufacturing a solar cell according to an embodiment of the present invention may further include removing a template between removing the porous layer and providing another conductor. In providing another conductor, the second conductor may be formed by electroless plating, and the second conductor may include a substrate and a plurality of conductive structures located on the substrate.

The solar cell having excellent photoelectric conversion efficiency may be manufactured using the porous layer and the plurality of semiconductor layers. In addition, a solar cell can be produced simply by using a template and an electroless etching method.

1 is a schematic cross-sectional view of a solar cell according to an embodiment of the present invention.
FIG. 2 is a plan view of the solar cell taken along the line II-II of FIG. 1.
3 is a schematic flowchart of a method of manufacturing the solar cell of FIG. 1.
4 to 11 are views sequentially showing the method of manufacturing the solar cell of FIG.

If any part is referred to as being "on" another part, it may be directly on the other part or may be accompanied by another part therebetween. In contrast, when a part is mentioned as "directly above" another part, no other part is intervened in between.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” include plural forms as well, unless the phrases clearly indicate the opposite. As used herein, the term "comprising" embodies a particular characteristic, region, integer, step, operation, element, and / or component, and other specific characteristics, region, integer, step, operation, element, component, and / or group. It does not exclude the presence or addition of.

Terms representing relative space, such as "below "," above ", and the like, may be used to more easily describe the relationship to another portion of a portion shown in the figures. These terms are intended to include other meanings or acts of the apparatus in use, as well as intended meanings in the drawings. For example, when inverting a device in the figures, certain parts that are described as being "below" other parts are described as being "above " other parts. Thus, an exemplary term "below" includes both up and down directions. The device can be rotated 90 degrees or rotated at different angles, and the term indicating the relative space is interpreted accordingly.

Unless defined otherwise, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Commonly used predefined terms are further interpreted as having a meaning consistent with the relevant technical literature and the present disclosure, and are not to be construed as ideal or very formal meanings unless defined otherwise.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

1 shows a schematic cross-sectional structure of a solar cell 100 according to an embodiment of the present invention. In the enlarged circle of FIG. 1, the first semiconductor layer 21 is enlarged to schematically show a cross-sectional structure thereof. The cross-sectional structure of the solar cell 100 of FIG. 1 is merely for illustrating the present invention, but the present invention is not limited thereto. Therefore, the cross-sectional structure of the solar cell 100 can be modified in other forms.

As illustrated in FIG. 1, the solar cell 100 includes a first electrode 10, semiconductor layers 21 and 23, a second electrode 30, and a resin fixing layer 40. The solar cell 100 further includes a third electrode 50, and may further include other elements as necessary.

The first electrode 10, the second electrode 30, and the third electrode 50 are connected to a passive element to emit power generated in the solar cell 100 to the outside. Although not shown in FIG. 1, the lead wire may be connected to the third electrode 50 to connect the passive element. Since light is incident through the second electrode 30, the second electrode 30 is made of a transparent conductive layer using a material such as an indium tin oxide (ITO) layer. On the other hand, as the material of the third electrode 50, a metal, for example, silver, aluminum, nickel, copper, or the like can be used. Therefore, the third electrode 50 can efficiently collect electrons or vacancy from the second electrode 30. The third electrode 50 may be formed by a paste coating method, physical vapor deposition method, electroplating or electroless plating, or the like.

As shown in FIG. 1, the first electrode includes a substrate 101 and a plurality of conductive structures 103. The plurality of conductive structures 103 is formed to extend in the z-axis direction on the plate surface 1011 of the substrate 101. An average width of the plurality of conductive structures 103 may be 10 nm to 500 nm. Here, since the cross section cut in the direction parallel to the xy plane may be circular, the width is interpreted to include a diameter. If the average width of the conductive structure 103 is too small, the structure of the solar cell 100 is not robust. On the contrary, when the average width of the conductive structure 103 is too large, it is not suitable for confining light. Therefore, the average width of the conductive structure 103 can be set within the above-described range. As a result, the plurality of conductive structures 103 and the plurality of semiconductor layers 21 and 23 formed thereon form a core shell structure, so that light can be confined well and maximize generation of electromotive force.

On the other hand, the average height of the conductive structure 103 may be 100nm to 100μm. If the average height of the conductive structure 103 is too large, the structure of the solar cell 100 is not robust. On the contrary, when the average height of the conductive structure 103 is too small, light cannot be drawn deeply into the solar cell 100, and the electromotive force generation efficiency is lowered. Therefore, the average height of the conductive structure 103 is adjusted in the above-described range.

The conductive structure 103 includes a first conductive structure 1031 and a second conductive structure 1033. The width of the second conductive structure 1033 is greater than the width of the first conductive structure 1031. Accordingly, the second conductive structure 1033 firmly maintains the structure of the solar cell 100. Therefore, durability of the solar cell 100 can be improved.

As shown in FIG. 1, a third electrode 50 is formed on the second conductive structure 1033 having a relatively wide width. Therefore, the third electrode 50 in contact with the second electrode 30 can be stably fixed to the inside of the solar cell 100. Therefore, the reliability of the electrical connection of the solar cell 100 can be improved.

The first electrode 10 returns the light transmitted through the resin pinned layer 40, the second electrode 30, and the plurality of semiconductor layers 21 and 23 to return to the plurality of semiconductor layers 21 and 23. Maximize the generation of electromotive force. To this end, the first electrode 10 may be manufactured by electroless plating a metal such as aluminum having good reflection. That is, the first electrode 10 is formed more opaque than the second electrode 30. Therefore, light does not pass through the first electrode 10, is totally reflected by the first electrode 10, and converted into electric power by the semiconductor layers 21 and 23.

The semiconductor layers 21 and 23 are positioned on the first electrode 10. The semiconductor layers 21 and 23 include a first semiconductor layer 21 and a second semiconductor layer 23. The first semiconductor layer 21 is in contact with the first electrode 10, and the second semiconductor layer 23 is in contact with the second electrode 30. The semiconductor layers 21 and 23 are doped epitaxially and have high photoelectric conversion efficiency. The semiconductor layers 21 and 23 having concentration differences therebetween may be manufactured by adjusting the doping concentration. For example, when the first semiconductor layer 21 is doped with a p-type, the second semiconductor layer 23 may be doped with an n-type. Thus, the pn junction between the first semiconductor layer 21 and the second semiconductor layer 23 is achieved.

Although not shown in FIG. 1, a band gap is formed by sequentially stacking a p ++ type semiconductor layer, a p + type semiconductor layer, a p type semiconductor layer, an intrinsic layer, an n type semiconductor layer, an n + type semiconductor layer, an n ++ type semiconductor layer, and the like. While minimizing, a doping concentration gradient can be formed. As a result, the photoelectric conversion efficiency of the solar cell 100 can be greatly increased.

The second electrode 30 is formed on the second semiconductor layer 23. The second electrode 30 can be formed on the second semiconductor layer 23 by a method such as vapor deposition. Since the second electrode 30 is electrically connected to the third electrode 50, the generated power is transmitted to the outside of the solar cell 100 through the third electrode 50.

As shown in FIG. 1, the resin fixing layer 40 covers the second electrode 30. The resin fixing layer 40 is filled in the space between the first conductive structure 1031 and the second conductive structure 1033. Therefore, the resin pinned layer 40 may further stabilize the structure of the solar cell 100. The resin pinned layer 40 may be formed of PDMS (polydimethylsiloxane, polydimethylsiloxane) or the like.

As shown in the enlarged circle of FIG. 1, the first semiconductor layer 21 in contact with the first electrode 10 has a non-uniform thickness in the z-axis direction. In addition, the first semiconductor layer 21 includes a plurality of holes 211. After etching the porous layer 19 (shown in FIG. 5, the same below) adjacent to the lower surface of the first semiconductor layer 21, the first electrode 10 is electroless plated and attached to the first semiconductor layer 21. do. Therefore, the cross-sectional structure of the first semiconductor layer 21 shown in the enlarged circle of FIG. 1 appears. That is, due to the etching structure, the porous layer is completely etched and difficult to remove. Thus, a portion of the porous layer 19 still remains in the first semiconductor layer 21.

Since the porous layer 19 is partially present, it can be seen that the porous layer 19 is coalesced with the first semiconductor layer 21. As a result, the lower portion of the first semiconductor layer 21 due to the porous layer 19 includes a plurality of pores 211 and has a non-uniform thickness. Therefore, the first electrode 10 may be attached to the first semiconductor layer 21 well. That is, since the lower surface of the first semiconductor layer 21 has an irregular shape, the first electrode 10 adheres well to the first semiconductor layer 21.

The bonding strength between the first semiconductor layer 21 and the first electrode 10 is greater than the bonding strength between the second semiconductor layer 23 and the second electrode 30. Here, the first bonding strength between the semiconductor layer 21 and the first electrode 10 may be 100N / cm ² to 1000N / cm ^2. When the bonding strength between the first semiconductor layer 21 and the first electrode 10 is too small, the first electrode 10 may not adhere well to the first semiconductor layer 21. In the case where the first electrode 10 is formed by electroless plating, the bonding strength between the first semiconductor layer 21 and the first electrode 10 cannot exceed 1000 N / cm ² due to the manufacturing method. Therefore, the bonding strength between the first semiconductor layer 21 and the first electrode 10 satisfies the above-described range.

Meanwhile, the plurality of pores 211 in the first semiconductor layer 21 scatter or reflect incident light to improve light absorption of the first semiconductor layer 21 and the second semiconductor layer 23. The plurality of pores 211 efficiently absorb wavelengths in the 300 nm to 2000 nm region. As a result, the first semiconductor layer 21 in which the plurality of pores 211 are present at the bottom of the first semiconductor layer 21 and the first semiconductor layer 21 in which the plurality of pores 211 do not exist are present. Since a relative refractive index difference occurs between), incident light does not penetrate the first semiconductor layer 21 and is reflected. Therefore, the reflected light may be converted into electric power while passing through the first semiconductor layer 21 and the second semiconductor layer 23 again. In summary, the plurality of cavities 211 scatter or reflect incident light to help absorb the first semiconductor layer 21 and the second semiconductor layer 23.

The above-described process of forming the first electrode 10 will be described in more detail later with reference to FIGS. 3, 10, and 11.

FIG. 2 illustrates a cross-sectional structure of the solar cell 100 taken along line II-II of FIG. 1, that is, a partial planar structure thereof. The cross-sectional structure of the solar cell 100 of FIG. 2 is merely for illustrating the present invention, but the present invention is not limited thereto. Therefore, the cross-sectional structure of the solar cell 100 may be modified in other forms.

As shown in FIG. 2, the solar cell 100 includes a first conductive structure 1031, a second conductive structure 1033, and a third conductive structure 1035. In addition, the solar cell 100 may further include other conductive structures as necessary. Substantially, the first conductive structure 1031 has a rod shape extending in the z-axis direction, and the second conductive structure 1033 and the third conductive structure 1035 have a partition shape. Therefore, the structure of the solar cell 100 can be stably maintained by the second conductive structure 1033 and the third conductive structure 1035.

As shown in FIG. 2, the second conductive structure 1033 extends in the y-axis direction, and the plurality of third conductive structures 1035 extend in the x-axis direction. Here, the plurality of third conductive structures 1035 are spaced apart from each other and positioned on the plate surface 1011 (shown in FIG. 1) of the substrate 101 (shown in FIG. 1). Since the plurality of third conductive structures 1035 are positioned in a direction crossing the second conductive structures 1033, the structure of the solar cell 100 is firmly maintained. Hereinafter, the manufacturing method of the solar cell 100 of FIG. 1 will be described in more detail with reference to FIGS. 3 to 11.

FIG. 3 schematically shows a flowchart of the manufacturing method of the solar cell 100 of FIG. 1, and FIGS. 4 to 11 are schematic views illustrating respective steps of the manufacturing method of the solar cell 100 of FIG. 1. Hereinafter, the manufacturing method of the solar cell 100 will be described in order with reference to FIGS. 4 to 11 along with FIG. 3. The manufacturing method of such a solar cell 100 is only for illustrating the present invention, and the present invention is not limited thereto. Therefore, the manufacturing method of the solar cell 100 can be modified differently.

First, in step S10 of FIG. 3, a template 60 for manufacturing a solar cell is provided. The template 60 (shown in FIG. 4) may be made of a material such as an organic material or an inorganic material. Template 60 includes a substrate 601 and a plurality of structures 603. The plurality of structures 603 are spaced apart from each other and positioned on the plate surface 6011 of the substrate 601. The plurality of structures 603 are manufactured by providing the first structures 6031 and the second structure 6033. Here, the width of the second structure 6033 is larger than the width of the first structures 6031 spaced apart from each other. Here, the width means the length of the first structure 6031 and the second structure 6033 parallel to the x-axis direction. The solar cell can be stably supported through the second structure 6033.

Next, in step S20 of FIG. 3, a first epitaxial layer is provided, and in step S30, the first epitaxial layer is converted into a porous layer 19. Step S20 and step S30 (shown in Fig. 5) are performed to use the template 60 repeatedly. That is, the porous layer 19 is provided on the template 60 so that the template 60 can be reused by separating the template 60 and forming a new first epitaxial layer thereon. However, as the porous layer 19 is formed, silicon of the template 60 is consumed, and thus it is difficult to maintain the structure of the original template 60. Accordingly, new silicon is deposited in step S20 to provide a first epitaxial layer so that the porous layer 19 can be well deposited without damaging the template 60 through steps S20 and S30. . In step S30, by converting the first epitaxial layer into the porous layer 19 by electrochemical etching or electroless etching, the silicon of the template 60 is not consumed, thereby minimizing the structural deformation of the template 60.

As shown in FIG. 5, the porous layer 19 is located above the template 60. The porous layer 19 may be made of silicon or the like and is formed discontinuously. The thickness of the porous layer 19 may be about 10 μm or less. The porous layer 19 may be formed by depositing and etching silicon on the template 60.

The porous layer 19 converted from the first epitaxial layer formed on the template 60 includes a plurality of pores. Therefore, when the porous layer 19 is etched with the etchant, the porous layer 19 is better etched than other layers due to the voids. Therefore, only the porous layer 19 can be removed without affecting other layers.

The porosity of the porous layer 19 may be 10% to 70%. If the porosity of the porous layer 19 is too high, the porous layer 19 can be easily peeled from the template 60. In addition, when the porosity of the porous layer 19 is too low, it is difficult to remove only the porous layer 19 by etching, so that the peripheral elements can be removed together.

In operation S40 of FIG. 3, a second epitaxial layer is provided on the porous layer 19, and in operation S50, the second epitaxial layer is converted into a plurality of semiconductor layers 21 and 23. (Shown in Figure 6)

That is, as shown in FIG. 6, the doped first semiconductor layer 21 and the second semiconductor layer 23 may be formed while being epitaxially grown on the porous layer 19. Here, the first semiconductor layer 21 may be provided as a p-type semiconductor layer, and the second semiconductor layer 23 may be provided as an n-type semiconductor layer. Accordingly, the first semiconductor layer 21 and the second semiconductor layer 23 function to form pn junctions to generate electromotive force by light. Here, since step S40 and step S50 may be performed simultaneously, the process may be simplified while greatly shortening the manufacturing time of the solar cell.

In operation S60 of FIG. 3, the second electrode 30 is provided on the plurality of semiconductor layers 21 and 23. The second electrode 30 functions as a conductor to draw power generated in the plurality of semiconductor layers 21 and 23 to the outside. Although not shown in FIG. 3, the third electrode 50 may be provided on the second electrode 30. Here, the third electrode 50 functions as an external lead conductor. The third electrode 50 is stably formed on the second structure 6033.

In step S70 of FIG. 3, the resin fixing layer 50 is provided to cover the second electrode 30 and the third electrode 50, which are conductors. The resin fixing layer 50 is used to insulate the second electrode 30 and the third electrode 50 from the outside while solidifying the structure of the solar cell.

Next, in step S80 of FIG. 3, a hole 609 is formed in the lower portion of the template 60. The hole 609 exposes the porous layer 19 (shown in FIG. 9, hereinafter same) externally. The hole 609 is formed at a position corresponding to the spaced space of the plurality of structures 6031 and 6033. Therefore, the distance from the porous layer 19 to be removed by etching can be minimized. The hole 609 is formed along a direction parallel to the z-axis direction in which the plurality of structures 6031 and 6033 extend. The position of the hole 609 can be set by aligning the template 60.

As shown in FIG. 10, the porous layer 19 can be removed by injecting etching liquid through the holes 609. Here, the porous layer 19 includes a plurality of pores, so that the etching is much faster than the peripheral device. Since the etching solution propagates along the direction in which the porous layer 19 extends, only the porous layer 19 can be removed.

Next, as shown in FIG. 11, since the porous layer 19 is removed, the template 60 (FIG. 10) spaced apart from the plurality of semiconductor layers 21 and 23 may be removed. Therefore, the plurality of semiconductor layers 21 and 23 are exposed to the outside.

In operation S90 of FIG. 3, a first electrode 10 (shown below in FIG. 1) is provided under the plurality of semiconductor layers 21 and 23. Here, the first electrode 10 functions as a conductor and may be provided by an electroless plating method. As a result, the solar cell 100 (shown in FIG. 1) can be manufactured.

It will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the following claims.

10. 30, 50. Electrode 19. Porous layer
21, 23. Semiconductor layer 40. Resin fixing layer
211. Public 1031, 1033. Conductive Structure
60.Template 609.Hole
100. Solar cell 1011. Plate

Claims (20)

A first electrode comprising a plurality of conductive structures spaced apart from each other,
A plurality of semiconductor layers stacked to cover the plurality of conductive structures and grown epitaxially,
A second electrode covering the plurality of semiconductor layers, and
Resin-fixed layer covering the second electrode
Including,
The plurality of semiconductor layers,
A first semiconductor layer in contact with the first electrode, and
A second semiconductor layer on the first semiconductor layer and in contact with the second electrode
Including,
The first semiconductor layer has a non-uniform thickness. The method of claim 1,
The first semiconductor layer includes a plurality of pores formed of a porous structure. The method of claim 2,
The bonding strength of the first semiconductor layer and the first electrode is greater than the bonding strength of the second semiconductor layer and the second electrode. The method of claim 3, wherein
Bonding strength between the first semiconductor layer and the first electrode is 100N / cm ² to 1000N / cm ² solar cell. The method of claim 1,
The plurality of conductive structures,
A plurality of first conductive structures, and
A second conductive structure having a width greater than the width of the first conductive structure
Including,
And a third electrode formed on the second conductive structure and in contact with the second electrode. The method of claim 5,
The plurality of conductive structures further include a plurality of third conductive structures connected to the second conductive structure, wherein the plurality of third conductive structures are spaced apart from each other and have a barrier rib shape. The method of claim 1,
The first semiconductor layer is a p-type semiconductor layer, the second semiconductor layer is an n-type semiconductor layer. The method of claim 1,
The first electrode is opaque than the second electrode. Providing a template comprising a plurality of structures spaced apart from each other,
Providing a first epitaxial layer overlying the template,
Converting the first epitaxial layer to a porous layer,
Providing a second epitaxial layer on the porous layer,
Converting the second epitaxial layer into a plurality of semiconductor layers,
Providing a conductor over the plurality of semiconductor layers,
Providing a resin fixing layer covering the conductor,
Removing the porous layer,
Removing the template, and
Providing another conductor under the plurality of semiconductor layers
Including,
Removing the porous layer,
Forming a hole in the lower portion of the template to externally expose the porous layer, and
Etching the porous layer by injecting an etchant into the hole;
Method for manufacturing a solar cell comprising a. delete 10. The method of claim 9,
In the step of exposing the porous layer outside, the hole is formed in a position corresponding to the spaced space of the plurality of structures along a direction parallel to the direction in which the plurality of structures extend. 10. The method of claim 9,
In the step of converting the first epitaxial layer to a porous layer, the porosity of the porous layer is a method of manufacturing a solar cell 10% to 70%. 10. The method of claim 9,
And providing the second epitaxial layer and converting the second epitaxial layer into a plurality of semiconductor layers at the same time. 10. The method of claim 9,
Providing the template comprises providing the plurality of structures,
Providing the plurality of structures,
Providing first structures spaced apart from each other, and
Providing a second structure spaced apart from the first structures, the second structure having a width greater than the width of the first structure
Method for manufacturing a solar cell comprising a. 15. The method of claim 14,
The first structures have a rod shape, and the second structures have a partition wall shape. 15. The method of claim 14,
And providing a plurality of third structures extending in a direction crossing the direction in which the second structure extends and having a partition shape. 17. The method of claim 16,
Providing an outer lead conductor on the second structure connected to the conductor between providing a conductor over the plurality of semiconductor layers and providing a resin pinned layer covering the conductor. Method for producing a battery. 10. The method of claim 9,
Converting the second epitaxial layer into a plurality of semiconductor layers,
providing a p-type semiconductor layer, and
Providing an n-type semiconductor layer on the p-type semiconductor layer
Method for manufacturing a solar cell comprising a. delete 10. The method of claim 9,
In the providing of the another conductor, the second conductor is formed by electroless plating, wherein the second conductor includes a substrate and a plurality of conductive structures positioned on the substrate.

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