KR101203007B1 - Solar cell and method for manufacturing the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solar cell and a method of manufacturing the same, comprising a semiconductor substrate comprising a first region having a first conductivity type and a second region having a second conductivity type; Provided is a solar cell including a semiconductor layer, a first electrode connected to the first region, and a second electrode connected to the second region. As described above, the present invention can increase the surface area of the light-receiving region by forming a semi-spherical semiconductor layer on the front surface of the solar cell, reduce the reflection of light from the surface, and provide a semi-spherical semiconductor layer through the HSG process. It is possible to simplify the process by forming, and the density and size of the hemispherical pattern can be easily adjusted by controlling process factors.

Solar cell, hemispherical, light receiving area, nucleation, HSG, scattering layer

Description

Solar cell and method for manufacturing same

1 is a cross-sectional view of a solar cell according to the prior art.

2 is a cross-sectional view of a solar cell according to a first embodiment of the present invention.

3 is a cross-sectional conceptual view of a hemispherical N-type semiconductor according to a modification of the first embodiment;

4A to 4C are cross-sectional views illustrating a method of manufacturing a solar cell according to a first embodiment of the present invention.

5A and 5B are cross-sectional views illustrating a method for manufacturing a hemispherical N-type semiconductor layer according to a modification of the first embodiment.

6 is a sectional view of a solar cell according to a second embodiment of the present invention.

7 is a sectional view of a solar cell according to a modification of the second embodiment.

<Explanation of symbols for the main parts of the drawings>

10 substrate 20 silicon layer

30, 130, 160: passivation film 40, 140, 180: electrode

110: P type semiconductor layer 120: N type semiconductor layer

The present invention relates to a solar cell and a method for manufacturing the same, and to a solar cell and a method for manufacturing the same having improved light receiving efficiency by increasing a light receiving area of the solar cell.

In general, a solar cell has a pair of electrons and holes generated inside the semiconductor of the solar cell by light from the outside, and the pair of electrons and holes moves to the N-type semiconductor by an electric field generated at the pn junction. Producing power by moving to type semiconductors.

The performance of such solar cells is highly dependent on the efficiency of converting light energy into electrical energy. Therefore, many researches are being conducted to increase the efficiency of solar cells, and one of the methods for increasing the efficiency of solar cells is to maximize the absorption of light by texturing the wafer surface.

1 is a cross-sectional view of a solar cell according to the prior art.

Referring to FIG. 1, the entire surface of the P-type silicon substrate 10 is etched through a texturing method. Thereafter, an N-type silicon layer 20 is formed on the entire surface of the textured substrate 10, and a passivation film 30 is formed on the entire surface of the textured substrate 10. Thereafter, a portion of the passivation film 30 is opened, and then a front electrode 40 is formed thereon. In this case, an n + region 50 may be formed under the front electrode 40. Subsequently, an oxide film 60 is formed on the rear surface of the P-type silicon substrate 10, a portion thereof is opened, and a rear electrode connected to the p + region 70 formed inside the P-type silicon substrate 10. 80).

The texturing methods include plasma etching, mechanical scribing, photolithography, chemical etching, and the like. have.

This texturing method is a process of etching a P-type silicon substrate 10 to form an unevenly shaped surface of a fabric to increase light absorption at the surface of the substrate. Can be reduced and the light absorption into the substrate can be increased.

The texturing method using plasma etching is a method of forming a pattern by applying a photoresist film, exposing and developing the photoresist, and then plasma etching using the pattern as a mask and then removing the mask.

The mechanical scribing method is a method of forming a groove on the wafer surface and then texturing using chemical etching.

In the method using a photolithography process, a photoresist is applied to an oxide-formed wafer, exposed to light, and developed to form a photoresist pattern, the same oxide pattern as that of the photoresist pattern is formed, and then an isotropic or anisotropic etching of the wafer surface using the oxide pattern as a mask. By texturing.

Chemical etching is a method of texturing by performing anisotropic etching using a chemical solution (anisotropic etching).

In the above-described texturing method, since the surface of the substrate is etched, substrate surface defects occur due to the etching process, the substrate is damaged due to excessive etching, and the pattern defect problem due to particles generated during the substrate etching process occurs. do.

In addition, when texturing using a mask using a photoresist film and an oxide film, a process is complicated, and the accuracy of etching is deteriorated.

Therefore, the present invention can improve the light receiving efficiency by forming a hemispherical semiconductor layer on the substrate surface to increase the surface area of the light receiving area in order to solve the above problems, the light absorption rate is increased by the hemispherical pattern to improve the efficiency of the solar cell It is an object of the present invention to provide a solar cell and a manufacturing method thereof that can be increased.

A semiconductor substrate comprising a first region having a first conductivity type and a second region having a second conductivity type, a semiconductive semiconductor layer of a second conductivity type on the second region, and the first region; Provided is a solar cell including a first electrode connected to the second electrode and a second electrode connected to the second region.

The second region of the second conductivity type may be provided on the front surface of the semiconductor substrate, and the first region of the first conductivity type may be provided on the rear surface of the semiconductor substrate.

In addition, a first conductive hemispherical semiconductor layer having a plurality of hemispherical curved surfaces according to the present invention, a second conductive semiconductor layer formed along a step of the hemispherical curved surface of the first conductive type, and the first conductive type Provided is a solar cell including a first electrode connected to the second electrode and a second electrode connected to the second conductive type.

In the above, the hemispherical shape is preferably provided with a plurality of hemispherical patterns continuously or spaced apart from each other.

Here, it is effective to further include a scattering layer formed on the second conductive semispherical semiconductor layer and the second conductive semiconductor layer. And,

It is effective to further include a transparent passivation layer formed on the second conductive hemispherical semiconductor layer and the second conductive semiconductor layer.

Of course, the electrode is preferably connected to a higher concentration of the conductive type than the conductive type.

The method may further include forming a second conductive hemispherical semiconductor layer on the first conductive semiconductor layer, forming a second electrode connected to the second conductive hemispherical semiconductor layer, It provides a solar cell manufacturing method comprising the step of forming a first electrode connected to the first conductive semiconductor layer.

The forming of the second conductive hemispherical semiconductor layer may include forming an amorphous silicon layer on the first conductive semiconductor layer, forming a plurality of silicon nuclei on the amorphous silicon layer, It is preferable to include the step of deforming to hemispherical by moving the silicon around the silicon nucleus through the heat treatment process.

In addition, forming a plurality of hemispherical curved surface on the surface of the first conductive semiconductor layer according to the present invention, forming a second conductive semiconductor layer along the curved step of the first conductive semiconductor layer; And forming a second electrode connected to the semiconductor layer of the second conductivity type, and forming a first electrode connected to the semiconductor layer of the first conductivity type. .

The forming of the plurality of hemispherical curved surfaces on the surface of the first conductive semiconductor layer may include forming a plurality of silicon nuclei on the surface of the first conductive semiconductor layer, and performing heat treatment. It is preferable to include a step of forming a hemispherical curved surface.

The forming of the plurality of hemispherical curved surfaces on the surface of the first conductive semiconductor layer may include forming the first conductive hemisphere semiconductor layer on the first conductive semiconductor layer, and Forming a silicon nucleus on the first conductive semi-spherical semiconductor layer, and preferably forming a hemispherical curved surface around the silicon nucleus through a heat treatment process.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and the scope of the invention to those skilled in the art. It is provided for complete information. Wherein like reference numerals refer to like elements throughout.

2 is a cross-sectional view of a solar cell according to a first embodiment of the present invention.

2, the solar cell according to the present embodiment includes a P-type semiconductor layer 110, a hemispherical N-type semiconductor layer 120 formed on the P-type semiconductor layer 110, and the N-type semiconductor layer ( The front passivation film 130 formed on the 120, the front electrode 140 connected to the N-type semiconductor layer 120, and the back passivation film 160 formed on the rear surface of the P-type semiconductor layer 110. ) And a back electrode 180 connected to the P-type semiconductor layer 110.

The P-type semiconductor layer 110 is preferably a silicon film doped with a low concentration of P-type impurities. The hemispherical N-type semiconductor layer 120 uses a silicon film doped with a low concentration of N-type impurities, but in this embodiment, it is preferable to use a silicon film having a HSG (Hemi-spherical grain) surface. As shown in FIG. 2, the hemispherical N-type semiconductor layer 120 may be formed in a hemispherical pattern in which an upper region thereof is continuous like a wave pattern, and the hemispherical patterns are spaced apart from each other as shown in FIG. 3. It may be formed in a shape. In this case, the present invention may form an active layer between the N-type semiconductor layer 120 and the P-type semiconductor layer 110 to improve the amount of electron hole pair generation by the light.

The front passivation layer 130 uses a light-transmitting insulating film, but in this embodiment, it is preferable to use an insulating film based on an oxide film and a nitride film. The front passivation layer 130 is preferably formed along a step of the hemispherical N-type semiconductor layer 120 formed below. Of course, it may be formed to a thickness thick enough to cover the step. In addition, the front passivation layer 130 is effective to use a material having a light transmittance of 70 to 100%.

A portion of the front passivation film 130 is provided with an opening for exposing the hemispherical N-type semiconductor layer 120 thereunder, and the front electrode 140 is formed on the opening to expose the semi-spherical N-type semiconductor layer 120. Is preferably connected. As the front electrode 140, a transparent electrode including ITO may be used, or a metallic material including Al, Cu, Ag, W, and an alloy thereof. In this case, a heavily doped N-type doped region 150 may be further formed in the lower region of the N-type semiconductor layer 120 to which the front electrode 140 is connected. The N-type doped region 150 may be formed by injecting a high concentration of N-type impurities into the opening region. In addition, a conductive layer 155 including metal or metal silicide may be further formed between the front electrode 140, the N-type semiconductor layer 120, and the N-type doped region 150. As a result, contact resistance between the front electrode 140 and the semiconductor layer may be reduced. The N-type doped region 150 may be implanted using the front passivation layer 130 as an ion implantation mask, or may be formed through a separate ion implantation mask and an ion implantation process before the passivation layer is formed, and then a passivation layer may be formed thereon. It may be.

The back passivation film 160 may use the same material film as the front passivation film 130 described above, or may use a material film having excellent light reflection characteristics. Through this, the light passing through the N-type semiconductor layer 120 and the P-type semiconductor layer 110 and reaching the rear passivation layer 160 is reflected to the P-type semiconductor layer 110 and the N-type semiconductor layer 120. It can also serve to supply.

A portion of the back passivation layer 160 is provided with an opening for exposing the P-type semiconductor layer 110, and a back electrode 180 is formed on the opening to form the P-type semiconductor layer 110 and the back electrode 180. It is preferable to be connected. Here, the P-type doped region 170 in which a high concentration of P-type impurities are implanted may be formed in the P-type semiconductor layer 110 exposed by the opening. In this case, the P-type doped region 170 may be formed through an ion implantation process using the back passivation layer 160 as an ion implantation mask, or may be formed in the P-type semiconductor layer 110 by forming a separate ion implantation mask. Next, a rear passivation film 160 may be formed thereon.

Hereinafter, a method of manufacturing a solar cell according to the present embodiment having the above-described structure will be described.

4A to 4C are cross-sectional views illustrating a method of manufacturing a solar cell according to a first embodiment of the present invention. 5A and 5B are cross-sectional views illustrating a method of manufacturing a hemispherical N-type semiconductor layer according to a modification of the first embodiment.

Referring to FIG. 4A, a hemispherical N-type semiconductor layer 120, that is, an N-type HSG film is formed on the P-type semiconductor layer 110.

The silicon film becomes an amorphous state at a low temperature of about 500 degrees, becomes a crystalline state at a temperature of about 600 degrees high temperature, and at the temperature between amorphous and crystalline, silicon particles are aggregated to form an HSG film having a convex hemispherical shape.

In the HSG film formation method, first, a silicon film doped with N-type impurities (eg, phosphorus (P)) is formed on the P-type semiconductor layer 110. The silicon film is grown at a temperature of 510 to 530 degrees using a silicon source gas (eg, SiH ₄ or Si ₂ H ₆ ) and an impurity gas (eg, PH ₃ ) to form an amorphous silicon doped with N-type impurities. Preference is given to using membranes. Of course, an undoped amorphous silicon film may be used. After this, it is preferable that doping is performed through a subsequent process.

Thereafter, a silicon source gas is supplied to form a silicon nucleus on the surface of the amorphous silicon. At this time, it is preferable to form a silicon nucleus using a silicon source gas including low pressure vapor deposition (LPCVD), plasma deposition, molecular beam deposition, and SiH ₄ or Si ₂ H ₆ . .

After the supply of the source gas is cut off and heat treatment is performed at high temperature, silicon atoms of amorphous silicon move to the silicon nucleus to form an HSG film. After the silicon nucleus is formed, the heat treatment is performed at a temperature of about 550 to 700 degrees, and silicon atoms of the amorphous silicon move to the silicon nucleus to form a rough hemispherical surface. That is, by the heat treatment process, surface atoms having a large free energy around the silicon nucleus move in the nucleus direction to form crystals. Of course, a separate heat treatment process may diffuse impurities and change amorphous silicon into polysilicon.

In the case of such an HSG film, the surface area of the light receiving area can be increased by having a surface area of 2 to 3 times larger than that of the flat surface. The density and size of the HSG can be variously modified by adjusting several process factors of the silicon liquid formation and heat treatment process. That is, as the time for nucleation increases, the silicon nucleus formed on the surface of the amorphous silicon increases, so that the density of the HSG increases. As the heat treatment time increases, the silicon atoms move more and the size of the HSG increases.

In addition, the present invention is not limited to the above description, and the HSG film may be manufactured through various methods. For example, vacuum-heating a doped amorphous silicon film causes redistribution of silicon particles in the silicon to form HSG.

In addition, in this embodiment, as shown in FIG. 5A, another film (see dotted line) stacked on the HSG film may have a tendency to reduce the exposed area of the grain and grain of the HSG, that is, the bone region between the hemisphere and the hemisphere. Therefore, it is preferable to perform the front etching so as to be spaced apart a predetermined interval between the hemisphere and the hemisphere as shown in Figure 5b. The front surface etching may be performed by using a wet or dry method under etching conditions in which the hemispherical shape is not changed. This can be produced so that the bone area is not reduced even if another film is stacked on top of it. It is preferable to adjust the process factors of the front side etching process so that hemispherical grains on the HSG surface are not etched.

Referring to FIG. 4B, a front passivation layer 130 is deposited on the hemispherical N-type semiconductor layer 120. A mask pattern is formed on the front passivation layer 130 to open a region where the front electrode 140 is to be formed, and then an etching process is performed to remove the front passivation layer 130 in the open region to form an opening. Remove the pattern. It is preferable to use a photosensitive film as said mask pattern. In this case, not only the front passivation layer 130 but also a part of the hemispherical N-type semiconductor layer 120 below may be removed.

An N-type doped region 150 is formed by implanting a high concentration of N-type impurity ions into the exposed region under the opening through an ion implantation process. In this case, the N-type doped region 150 may be formed by implanting impurities into the N-type semiconductor layer 120 as well as a portion of the P-type semiconductor layer 110. After ion implantation, a predetermined heat treatment process may be performed to diffuse the doped impurities.

A metallic conductive film 155 is formed on the lower surface of the opening, and then a front electrode 140 is formed on the metallic conductive film 155. The front electrode 140 is preferably formed through a patterning process using a mask after forming a conductive film on the entire structure. Of course, it may be formed through a sputtering or deposition process using a mask.

Referring to FIG. 4C, the back passivation layer 160 is deposited on the back surface of the P-type semiconductor layer 110. Thereafter, a portion of the back passivation layer 160 is removed through a patterning process to form an opening exposing the back surface of the P-type semiconductor layer 110. An ion implantation process is performed to form a high concentration P-type doped region 170 in the P-type semiconductor layer 110 under the opening. Next, a solar cell is manufactured by forming a conductive rear electrode 180 on the rear surface.

As such, a hemispherical N-type semiconductor layer may be formed on the entire surface of the solar cell, that is, through the light receiving region, to increase the surface area of the light receiving region, reduce the reflection of light from the surface, and not etch. Since the hemispherical shape is formed through the method, the film quality can be improved by preventing damage to the thin film due to etching.

The present invention is not limited to the above description and various modifications are possible. That is, the hemispherical shape may be formed on the entire surface of the P-type semiconductor layer instead of the N-type semiconductor layer. Hereinafter, a solar cell according to a second exemplary embodiment of the present invention including a P-type semiconductor layer having a hemispherical pattern on its front surface will be described. Descriptions overlapping with the above-described embodiments will be omitted.

6 is a cross-sectional view of a solar cell according to a second embodiment of the present invention. 7 is a sectional view of a solar cell according to a modification of the second embodiment.

6 and 7, the solar cell according to the present embodiment has an N-type semiconductor formed along a step between a P-type semiconductor layer 110 having a hemispherical curved surface on its front surface and a hemispherical curved surface of the P-type semiconductor layer 110. A layer 120, a front passivation film 130 formed on the N-type semiconductor layer 120, a front electrode 140 connected to the N-type semiconductor layer 130, and the P-type semiconductor layer 110. The back passivation layer 160 formed on the back of the) and the back electrode 180 connected to the P-type silicon semiconductor layer 110.

The hemispherical curved surface on the P-type semiconductor layer 110 is preferably formed through an HSG process. That is, as shown in FIG. 6, it is preferable to form a silicon nucleus on the P-type semiconductor layer 110 in an amorphous state, and then form a hemispherical curved surface on the surface thereof through a heat treatment process. Of course, the present invention is not limited thereto, and a P-type HSG film may be formed on the P-type semiconductor layer 110 in a crystalline state as shown in FIG. 7. That is, a P-type doped amorphous silicon film is formed on the P-type semiconductor layer 110. Thereafter, the silicon source gas may be injected to form a silicon nucleus on the surface thereof, the injection of the silicon source gas may be blocked, and the silicon atoms may be moved around the silicon nucleus through a heat treatment process to form a hemispherical HSG 111 film. .

A silicon film doped with N-type impurities is used as the N-type semiconductor layer 120, but is preferably formed along the step on the entire surface of the P-type semiconductor layer 110 having a hemispherical curved surface. In this case, as shown in FIG. 7, a scattering layer 121, that is, a diffuse reflection layer, may be formed on the surface of the N-type semiconductor layer 120, or a separate scattering pattern may be formed on the surface thereof. As a result, when light incident to the inside of the semiconductor layer through the front surface of the solar cell is reflected to the outside, it is scattered or diffusely reflected to reduce the amount of light reflected to the outside of the semiconductor layer and increases the amount of light staying inside the semiconductor layer. This can increase the amount of electron-electron pair generated to improve the efficiency of the solar cell.

A back passivation layer 160 and a back electrode 180 are formed on the back surface of the P-type semiconductor layer 110. In this case, as shown in FIG. 7, the reflective layer 161 may be formed under the rear passivation layer 160, that is, at the interface between the rear passivation layer 160 and the P-type semiconductor layer 110. The light passing through the semiconductor layer through the reflective layer 161 is reflected from the rear surface of the P-type semiconductor layer 110 to guide the front direction, thereby improving efficiency of the solar cell.

In the above description, the N-type semiconductor layer is formed through a predetermined deposition process on the P-type semiconductor layer, but the present invention is not limited thereto, and the N-type semiconductor layer is injected by injecting N-type impurities into the P-type semiconductor layer. May be formed. In addition, the front electrode may be disposed to the rear side of the solar cell in order to prevent the light receiving area due to the front electrode from decreasing. In addition, the front electrode may be formed in a recessed shape, that is, an electrode may be formed on the recessed portion by a conductive paste or a plating method, or the electrode may be formed by applying a conductive material by a screen printer method.

In addition, the said solar cell can also be manufactured using a separate board | substrate. A P-type semiconductor layer is formed on the substrate, an N-type semiconductor layer and a front electrode are formed thereon, and then the semiconductor substrate is removed. Thereafter, a lower electrode may be formed under the P-type semiconductor layer to manufacture a solar cell.

In addition, the solar cell according to the present embodiment may further include a separate inner pad to be connected to the external terminal. The inner pad includes a first pad connected to a front electrode and a second pad connected to a rear electrode.

As described above, the present invention can increase the surface area of the light-receiving region by forming a semi-spherical semiconductor layer on the entire surface of the solar cell, and can reduce the reflection of light on the surface.

In addition, the process may be simplified by forming a hemispherical semiconductor layer through the HSG process, and the density and size of the hemispherical pattern may be easily controlled by controlling process factors.

In addition, by etching the hemispherical pattern and the hemispherical pattern spaced apart by a predetermined interval can solve the problem of reducing the surface area by the subsequent film deposition.

In addition, a scattering layer may be formed on an outer surface of the semiconductor layer to scatter light reflected from the inside of the semiconductor layer to the outside, thereby improving condensing efficiency.

The present invention is not limited to the above-described embodiments, but may be embodied in various forms. In other words, the above-described embodiments are provided so that the disclosure of the present invention is complete, and those skilled in the art will fully understand the scope of the invention, and the scope of the present invention should be understood by the appended claims .

Claims (12)

A substrate comprising a first region of a first conductivity type and a second region of a second conductivity type having a polarity opposite to the first region; A semiconducting second conductive semiconductor layer formed on the second region; A passivation layer formed on the second conductive semiconductor layer; A first electrode connected to the first region; A second electrode formed on the second region; The second region of the second conductivity type is provided on the front surface of the substrate, the first region of the first conductivity type solar cell is provided on the rear surface of the substrate. delete A first conductive semiconductor layer having a plurality of hemispherical curved surfaces; A second conductive semiconductor layer formed along a step of the first conductive hemispherical curved surface; A passivation layer formed on the second conductive semiconductor layer; A first electrode connected to the first conductive semiconductor layer; A second electrode formed on the second conductive semiconductor layer; Solar cell comprising a. The method according to claim 1 or 3, The second conductive semiconductor layer is provided with a plurality of hemispherical patterns are continuously provided or spaced at regular intervals. The method according to claim 1 or 3, The solar cell further comprises a scattering layer formed on the second conductive semiconductor layer. The method according to claim 1 or 3, The passivation layer is a solar cell, characterized in that the transparent insulating film or insulating film. delete Forming a second conductive hemispherical semiconductor layer on the first conductive semiconductor layer; Forming a passivation layer on the second conductive semiconductor layer; Forming a second electrode connected to the second conductive hemispherical semiconductor layer; Forming a first electrode connected to the first conductive semiconductor layer; Method for manufacturing a solar cell comprising a. The method of claim 8, wherein the forming of the second conductivity-type semispherical semiconductor layer, Forming an amorphous silicon layer on the first conductive semiconductor layer; Forming a plurality of silicon nuclei in the amorphous silicon layer; Transferring the silicon around the silicon nucleus to a hemispherical shape through a heat treatment process; Method for manufacturing a solar cell comprising a. Forming a plurality of hemispherical curved surfaces on the surface of the first conductive semiconductor layer; Forming a second conductive semiconductor layer along a curved step of the first conductive semiconductor layer; Forming a passivation layer on the second conductive semiconductor layer; Forming a second electrode connected to the second conductive semiconductor layer; Forming a first electrode connected to the first conductive semiconductor layer; Method for manufacturing a solar cell comprising a. The method of claim 10, wherein the forming of the plurality of hemispherical curved surfaces on the surface of the first conductive semiconductor layer, Forming a plurality of silicon nuclei on a surface of the first conductive semiconductor layer; Forming a hemispherical curved surface around the silicon nucleus through a heat treatment process; Method for manufacturing a solar cell comprising a. The method of claim 10, wherein the forming of the plurality of hemispherical curved surfaces on the surface of the first conductive semiconductor layer, Forming the first conductive hemisphere semiconductor layer on the first conductive semiconductor layer; Forming a silicon nucleus on the first conductive hemisphere semiconductor layer; Forming a hemispherical curved surface around the silicon nucleus through a heat treatment process; Method for manufacturing a solar cell comprising a.

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