KR101201141B1 - Digital to analog converter - Google Patents

Abstract

Disclosed is a digital-to-analog converter capable of minimizing an area.

The digital-to-analog converter according to the present invention is a first control unit modulated by a predetermined lower bit data signal among n bit data signals and controlled by the modulated signal to select at least one or more analog level signals among a plurality of analog level signals. And a second control unit connected to the first control unit and controlled to a predetermined higher bit data signal among the n bit data signals to select and output any one level of the at least one analog level.

Digital-to-Analog Converter, Decoder, Binary

Description

Digital to analog converter

1 is a view showing a conventional liquid crystal display device.

2 shows a detailed digital-to-analog converter.

3 illustrates another embodiment of the digital-to-analog converter of FIG.

4 is a detailed view of a data driver.

5 shows a detailed digital-to-analog converter according to the invention.

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

101: first control unit 103: second control unit

106: data driver 109: shift register

110: gamma voltage generator 111: latch portion

112: digital-to-analog converter 114: output buffer

115: decoder 116: inverter

The present invention relates to a digital-to-analog converter, and more particularly to a digital-to-analog converter capable of minimizing an area.

As the information society develops, the demand for display devices is increasing in various forms. In response to this, various flat panel display devices such as liquid crystal display (LCD), plasma display panel (PDP), and electro luminescent display (ELD) have been studied, and some of them have already been used as display devices in various devices.

Among them, LCD (hereinafter referred to as 'liquid crystal display device') is most widely used as a substitute for CRTs for mobile image display devices due to its excellent image quality, light weight, thinness, and low power consumption. In addition to mobile applications such as monitors of notebook computers, liquid crystal displays have been developed in various ways such as television monitors.

1 is a view showing a conventional liquid crystal display device.

As shown in FIG. 1, a conventional liquid crystal display device includes a liquid crystal panel 2 in which a plurality of gate lines GL0 to GLn and data lines DL1 to DLm are arranged to display a predetermined image, and the gate line. A gate driver 4 for supplying a scan signal to GL0 to GLn, a data driver 6 for supplying a data voltage to the data lines DL1 to DLm, and the gate driver 4 and a data driver 6 It includes a timing controller 8 for controlling the.

Since the liquid crystal display is a well known technique, a detailed description thereof will be omitted.

The data driver 6 includes a digital-analog converter (not shown) for converting the R, G, and B data signals supplied from the timing controller 8 into data voltages that are analog voltages using gamma voltages. .

The digital-analog converter converts R, G, and B data signals, which are digital signals supplied from the timing controller 8, into analog data voltages using gamma voltages and R-strings provided in the data driver 6. To convert. The converted data voltage is supplied to the plurality of data lines DL1 to DLm.

2 is a detailed view of a digital-analog converter.

As shown in Fig. 2, the digital-to-analog converter 12 includes first to third inverters 16a to 3-1 for generating the complementary data signals d1 'to d3' from the 3-bit data signals d1 to d3. 16c and the first to fourteenth transistors TR1 to TR14 controlled by the data signals d1 to d3 and the complementary data signals d1 'to d3'.

The digital-to-analog converter 12 is an analog signal corresponding to the data signals d1 to d3 and the complementary data signals d1 'to d3', that is, the gamma voltage generated by the gamma voltage generator 10. Convert and output

The gamma voltage generator 10 includes a resistor-string unit in which first to eighth resistors R1 to R8 are connected in series. The first resistor R1 is connected to the input terminal of the power supply voltage Vdd and the eighth resistor R8 is connected to the ground GND voltage. The power supply voltage Vdd is divided by the first to eighth resistors R1 to R8, and the voltages VR1 to VR8 that are divided by the first to eighth resistors R1 to R8 are first divided. It is supplied to the source terminals of the first to eighth transistors TR1 to TR8.

The first to fourth transistors TR1 to TR4 are simultaneously controlled by the third data signal d3, and the fifth to eighth transistors TR5 to TR8 are simultaneously controlled by the third complementary data signal d3 '. Controlled.

A ninth transistor TR9 is connected to the drain terminals of the first and fifth transistors TR1 and TR5, and the eleventh transistor TR11 is connected to the drain terminals of the second and sixth transistors TR2 and TR6. The tenth transistor TR10 is connected to the drain terminals of the third and seventh transistors TR3 and TR7, and the twelfth transistor TR12 is connected to the drain terminals of the fourth and eighth transistors TR4 and TR8. Is connected.

The ninth and tenth transistors TR9 and TR10 are simultaneously controlled by the second data signal d2, and the eleventh and twelfth transistors TR11 and TR12 are simultaneously controlled by the second complementary data signal d2 '. do. A thirteenth transistor TR13 is connected to the drain terminals of the ninth and eleventh transistors TR9 and TR11, and a fourteenth transistor TR14 is connected to the drain terminals of the tenth and twelfth transistors TR10 and TR12. It is.

The thirteenth transistor TR13 is controlled by the first data signal d1, and the fourteenth transistor TR14 is controlled by the first complementary data signal d1 '.

Therefore, when the 3-bit data signals d1 to d3 are supplied to the input terminal of the digital-analog converter 12, the data signals d1 to d3 are complementary data signals via the inverters 16a, 16b, and 16c. (d1 'to d3'), the first to fourteenth transistors TR1 to TR14 are controlled by the data signals d1 to d3 and the complementary data signals d1 'to d3'. The analog gamma voltage of is supplied to the plurality of data lines (DL1 to DLm in FIG. 1) through the output buffer 14.

가 된다.The digital-to-analog converter 12 is formed in a binary manner. If the number of bits of the data signal supplied to the input terminal of the digital-analog converter 12 is 3 bits, the number of transistors TR is

.

가 된다. As a result, when the number of bits of the data signal supplied to the input terminal of the digital-analog converter 12 increases by one bit, the number of transistors TR is

.

As described above, the binary-to-digital analog-to-analog converter 12 increases the number of transistors TR every time the number of bits of the input data signal increases so that the digital-to-analog converter 12 increases. ) Will increase the total area. In addition, in the binary method, since an analog voltage is output through the plurality of transistors TR, a driving time increases.

FIG. 3 illustrates another embodiment of the digital-to-analog converter of FIG. 2.

As shown in Figs. 2 and 3, the digital-analog converter 22 is formed in a decoder manner. The digital-to-analog converter 22 includes a decoder 15 for outputting a three-bit data signal as eight data signals, and first to eighth transistors TR1 to TR8 controlled by the eight data signals. .

Gate terminals of the first to eighth transistors TR1 to TR8 are connected to and controlled with eight data signals output from the decoder 15, respectively. The data signal output from the decoder 15 is supplied to the first to eighth transistors TR1 to TR8, and a plurality of data signals generated by the gamma voltage generator in accordance with the first to eighth transistors TR1 to TR8. The voltage of any one of the analog gamma voltage is selected and output to the output buffer 14. The voltage output to the output buffer 14 is supplied to the plurality of data lines (DL1 to DLm in FIG. 1).

개의 데이터 신호를 출력하고 상기 8 개의 데이터 신호들은 제 1 내지 제 8 트랜지스터(TR1 ~ TR8)로 공급되어, 상기 제 1 내지 제 8 트랜지스터(TR1 ~ TR8)에 의해 선택된 소정의 아날로그 감마전압을 출력하게 된다.The digital-to-analog converter 22 is configured in a decoder manner as mentioned above. Therefore, when the 3-bit data signal is input to the decoder 15, the decoder 15

Output eight data signals and the eight data signals are supplied to first to eighth transistors TR1 to TR8 to output a predetermined analog gamma voltage selected by the first to eighth transistors TR1 to TR8. do.

개의 데이터 신호를 출력하고 상기 16 개의 데이터 신호들에 제어되는 16 개의 트랜지스터가 필요하게 된다. When a 4-bit data signal is input to the digital-to-analog converter 22, the decoder 15

16 transistors are outputted and 16 transistors controlled to the 16 data signals are required.

증가하게 되어 상기 디지털-아날로그 컨버터(22)의 면적이 증가하게 된다.As described above, the digital-to-analog converter 22 made of the decoder method increases the area of the decoder 15 which processes the data whenever the number of bits n of the input data signal is increased. Accordingly, the number of transistors TR depends on the number of bits n of the data signal.

This increases the area of the digital-to-analog converter 22.

It is an object of the present invention to provide a digital-to-analog converter capable of minimizing the area and driving at high speed.

A digital-to-analog converter according to the present invention for achieving the above object is modulated by a predetermined lower bit data signal of the n-bit data signal, controlled by the modulated signal to at least one or more analog level signals of a plurality of analog level signals And a second control unit connected to the first control unit and configured to be controlled by a predetermined higher bit data signal among the n bit data signals to select and output any one of the at least one analog level. .

Hereinafter, embodiments according to the present invention will be described with reference to the accompanying drawings.

4 is a detailed view of a data driver.

As shown in FIG. 4, the data driver 106 includes a shift register 109 for supplying a sequential sampling signal, a latch unit 111 for sequentially latching and simultaneously outputting a digital data signal in response to the sampling signal; A digital-analog converter 112 for converting the digital data signal from the latch unit 111 into an analog voltage, and an output buffer 114 for buffering and outputting the analog voltage supplied from the digital-analog converter 112. It is provided.

In addition, the digital-analog converter 112 is supplied with a gamma voltage generated by the gamma voltage generator 110.

When an externally generated source start pulse SSP is supplied to the shift register 109, the shift register 109 shifts and outputs a sampling signal sequentially according to the source sampling clock signal SSC.

The latch unit 111 sequentially samples and latches the digital data signal supplied from the outside in a predetermined unit in response to the sampling signal supplied from the shift register 109.

The digital-analog converter 112 converts the digital data signal supplied from the latch unit 111 into an analog voltage by using the gamma voltage supplied from the gamma voltage generator 110 and outputs the analog voltage. The analog voltage is supplied to the plurality of data lines DL1 to DLm through the output buffer 114.

As illustrated in FIG. 5, the digital-to-analog converter 112 receives a second and third data signals d3 and d2 and outputs four data signals a, b, c, and d. 115, first to eighth transistors TR1 to TR8 connected to the four data signals, an inverter 116 generating a first complementary data signal d1 ′ from the first data signal d1, and And the ninth and tenth transistors TR9 and TR10 controlled by the first data signal d1 and the first complementary data signal d1 '.

The digital-analog converter 112 includes a first control unit 101 made of the decoder method described above and a second control unit 103 made of a binary method.

When the first to third data signals d1 to d3 having three bits are supplied to the input terminal of the digital-analog converter 112, the digital-analog converter 112 is configured to perform the first to third data signals d1 to d. d3) is converted into a gamma voltage generated by the gamma voltage generator 110 and output.

The gamma voltage generator 110 includes a resistor-string unit in which first to eighth resistors R1 to R8 are connected in series. The first resistor R1 is connected to the input terminal of the power supply voltage Vdd and the eighth resistor R8 is connected to the ground GND voltage.

The power supply voltage Vdd is divided by the first to eighth resistors R1 to R8, and the voltages VR1 to VR8 that are divided by the first to eighth resistors R1 to R8 are first divided. It is supplied to the source terminals of the first to eighth transistors TR1 to TR8.

That is, the first voltage VR1 is connected to the source terminal of the first transistor TR1, the second voltage VR2 is connected to the source terminal of the second transistor TR2, and the third voltage VR3 is The fourth terminal VR4 is connected to the source terminal of the third transistor TR3, and the fourth voltage VR4 is connected to the source terminal of the fourth transistor TR4.

The fifth voltage VR5 is connected to the source terminal of the fifth transistor TR5, the sixth voltage VR6 is the source terminal of the sixth transistor TR6, and the seventh voltage VR7 is the seventh transistor TR7. ) Is connected to the source terminal of (), and the eighth voltage VR8 is connected to the source terminal of the eighth transistor TR8.

When the 3 bit data signals d1 to d3 are supplied to the digital-analog converter 112, the 2 bit data signals d2 and d3 are input to the first control unit 101 formed by the decoder method. The remaining one bit data signal d1 is supplied to the second control unit 103 made in a binary manner.

The first control unit 101 modulates the 2-bit data signals d2 and d3 to output four modulated data signals a, b, c and d, and the modulated data signal ( It consists of the 1st-8th transistors TR1-TR8 controlled by a, b, c, d.

The second controller 103 uses an inverter 116 for converting the one-bit data signal d1 into the complement data signal d1 ', and the one-bit data signal d1 and the complement data signal d1'. The ninth and tenth transistors TR9 and TR10 are controlled.

The second and third data signals d2 and d3 supplied to the decoder 115 are shown in Table 1 below.

d2
d3
Output 0 0 a 0 One b One 0 c One One d

If the second and third data signals d2 and d3 input to the decoder 115 are (0, 0), the decoder 115 outputs a data signal. The a data signal is supplied to the gate terminals of the first and fifth transistors TR1 and TR5 of the first to eighth transistors TR1 to TR8.

The first and fifth transistors TR1 and TR5 are turned on due to a data signal supplied to the gate terminals of the first and fifth transistors TR1 and TR5. As the first and fifth transistors TR1 and TR5 are turned on, a first voltage VR1 is supplied from a source terminal to a drain terminal of the first transistor TR1 to supply the first and fifth transistors TR5. The fifth voltage VR5 is supplied from the source terminal to the drain terminal.

The first voltage VR1 is supplied to the ninth transistor TR9, and the fifth voltage VR5 is supplied to the tenth transistor TR10.

In this case, when the first data signal d1, which is the remaining one bit data signal, is 0, the first data signal d1 is supplied to the ninth transistor TR9 and the inverter 116. In the ninth transistor TR9, the first data signal d1 is turned off by the first data signal d1, and the first data signal d1 supplied to the inverter 116 is 1. ') Is supplied to the tenth transistor TR10.

The tenth transistor TR10 is turned on by the first complementary data signal d1 ′ to output a fifth voltage VR5 supplied to the tenth transistor TR10.

When the first data signal d1 is 1, the ninth transistor TR9 is turned on to output the first voltage VR1 supplied to the ninth transistor TR9.

If the second and third data signals d2 and d3 input to the decoder 115 are (0, 1), the decoder 115 outputs a b data signal. The b data signal is supplied to the gate terminals of the second and sixth transistors TR2 and TR6 of the first to eighth transistors TR1 to TR8.

The second and sixth transistors TR2 and TR6 are turned on due to the b data signal supplied to the gate terminals of the second and sixth transistors TR2 and TR6. As the second and sixth transistors TR2 and TR6 are turned on, a second voltage VR2 is supplied from a source terminal to a drain terminal of the second transistor TR2 and the sixth transistor TR6 The sixth voltage VR6 is supplied from the source terminal to the drain terminal.

The second voltage VR2 is supplied to the ninth transistor TR9, and the sixth voltage VR6 is supplied to the tenth transistor TR10.

In this case, when the first data signal d1, which is the remaining one bit data signal, is 0, the first data signal d1 is supplied to the ninth transistor TR9 and the inverter 116. In the ninth transistor TR9, the first data signal d1 is turned off by the first data signal d1, and the first data signal d1 supplied to the inverter 116 is 1. ') Is supplied to the tenth transistor TR10.

The tenth transistor TR10 is turned on by the first complementary data signal d1 ′ to output the sixth voltage VR6 supplied to the tenth transistor TR10.

When the first data signal d1 is 1, the ninth transistor TR9 is turned on and the second voltage VR2 supplied to the ninth transistor TR9 is output.

If the second and third data signals d2 and d3 input to the decoder 115 are (1, 0), the decoder 115 outputs a c data signal. The c data signal is supplied to the gate terminals of the third and seventh transistors TR3 and TR7 of the first to eighth transistors TR1 to TR8.

The third and seventh transistors TR3 and TR7 are turned on due to the c data signal supplied to the gate terminals of the third and seventh transistors TR3 and TR7. As the third and seventh transistors TR3 and TR7 are turned on, a third voltage VR3 is supplied from a source terminal to a drain terminal of the third transistor TR3 to supply the third voltage VR3. The seventh voltage VR7 is supplied from the source terminal to the drain terminal.

The third voltage VR3 is supplied to the ninth transistor TR9 and the seventh voltage VR7 is supplied to the tenth transistor TR10.

In this case, when the first data signal d1, which is the remaining one bit data signal, is 0, the first data signal d1 is supplied to the ninth transistor TR9 and the inverter 116. In the ninth transistor TR9, the first data signal d1 is turned off by the first data signal d1, and the first data signal d1 supplied to the inverter 116 is 1. ') Is supplied to the tenth transistor TR10.

The tenth transistor TR10 is turned on by the first complementary data signal d1 ′ to output a seventh voltage VR7 supplied to the tenth transistor TR10.

When the first data signal d1 is 1, the ninth transistor TR9 is turned on and the third voltage VR3 supplied to the ninth transistor TR9 is output.

When the second and third data signals d2 and d3 input to the decoder 115 are (1, 1), the d data signal is output to the output terminal of the decoder 115. The d data signal is supplied to the gate terminals of the fourth and eighth transistors TR4 and TR8 of the first to eighth transistors TR1 to TR8.

The fourth and eighth transistors TR4 and TR8 are turned on due to the d data signal supplied to the gate terminals of the fourth and eighth transistors TR4 and TR8. As the fourth and eighth transistors TR4 and TR8 are turned on, the fourth voltage VR4 is supplied from the source terminal of the fourth transistor TR4 to the drain terminal, and the fourth and eighth transistors TR8 are connected to each other. The eighth voltage VR8 is supplied from the source terminal to the drain terminal.

The fourth voltage VR4 is supplied to the ninth transistor TR9, and the eighth voltage VR8 is supplied to the tenth transistor TR10.

In this case, when the first data signal d1, which is the remaining one bit data signal, is 0, the first data signal d1 is supplied to the ninth transistor TR9 and the inverter 116. In the ninth transistor TR9, the first data signal d1 is turned off by the first data signal d1, and the first data signal d1 supplied to the inverter 116 is 1. ') Is supplied to the tenth transistor TR10.

The tenth transistor TR10 is turned on by the first complementary data signal d1 ′ to output an eighth voltage VR8 supplied to the tenth transistor TR10.

When the first data signal d1 is 1, the ninth transistor TR9 is turned on and the fourth voltage VR4 supplied to the ninth transistor TR9 is output.

As described above, the digital-to-analog converter 112 includes a decoder method and a binary method.

The two-bit data signals d2 and d3 of the three-bit data signals d1 to d3 input to the digital-analog converter 112 are input to the decoder 115, and the remaining one-bit data signal d1 is the ninth. And the tenth transistors TR9 and TR10. The decoder 115 outputs an input two-bit data signal as four data signals to control the first to eighth transistors TR1 to TR8 respectively corresponding to the four data signals.

In order to convert the 3-bit data signals d1 to d3 into analog voltages, the digital-to-analog converter 112 outputs two-bit data signals d2 and d3 as four data signals, and First to eighth transistors TR1 to TR8 controlled by two data signals are required. In addition, the ninth and tenth transistors TR9 and TR10 controlled by the remaining one bit data signal d1 are required.

As a result, in order to convert the 3-bit data signals d1 to d3 into analog voltages, the first to tenth transistors TR1 to TR10 and the decoder 115 for processing the 2-bit data signal are required.

의 트랜지스터(TR)가 필요하다. 상기 바이너리(Binary) 방식으로 1 비트의 데이터 신호(d1)를 처리하기 위해서는

의 트랜지스터(TR)이 필요하다.That is, in order to process the 2-bit data signals d2 and d3 by the decoder method, the decoder 115 converts the 2-bit data signals d2 and d3 into four data signals;

Transistor TR is required. In order to process the 1-bit data signal d1 in the binary manner

Transistor TR is required.

When the number of bits of the data signal input to the digital-analog converter 112 increases by one bit, the digital-analog converter 112 processes the 4-bit data signal and converts it into an analog voltage.

In this case, when the 3-bit data signal of the 4-bit data signal is processed by the decoder method and the remaining 1-bit data signal is processed by the binary method, the area of the digital-analog converter 112 can be minimized.

의 트랜지스터(TR)가 필요하고, 나머지 1 비트 데이터 신호를 상기 바이너리(Binary) 방식으로 처리하기 위해서는

의 트랜지스터(TR1)가 필요하게 된다.That is, in order to process the 3-bit data signal by the decoder method, a decoder for converting the 3-bit data signal into eight data signals;

Transistor TR is required, and in order to process the remaining 1-bit data signal in the binary manner,

Transistor TR1 is required.

In particular, in the binary method, the closer to the resistance-string unit included in the gamma voltage generator 110, the greater the number of transistors TR controlled by data signals.

Accordingly, in order to reduce the number of the transistors TR, the digital-analog converter 112 processes the data signal in a decoder manner near the resistance-string portion of the gamma voltage generator 110 and the resistance. Far from the string part, the data signal is processed in a binary manner.

As described above, in order to convert the data signal input with the smallest area into the analog voltage, the digital-analog converter 112 is formed by a decoder method and a binary method.

As mentioned above, the digital-to-analog converter according to the present invention converts an input data signal into an analog voltage using a decoder method and a binary method, thereby minimizing an area even if the number of bits of the input data signal is increased. As a result, the manufacturing cost can be reduced.

As described above, the digital-to-analog converter according to the present invention uses both a decoder method and a binary method to convert an input data signal into an analog voltage, thereby minimizing an area and reducing a manufacturing cost. have.

Claims (7)

a first control unit modulated by a predetermined lower bit data signal among n bit data signals and controlled by the modulated signal to select at least one analog level signal from among a plurality of analog level signals; And A second control unit connected to the first control unit and controlled to a predetermined higher bit data signal among the n bit data signals to select and output any one level of the at least one analog level; The control unit is provided with a decoder that modulates the lower bit data signal using a power of 2 and twice the number of signals modulated by the power of 2 so that the control unit includes a first transistor group by the decoder. To analog converter. The method of claim 1, And the upper bit data signal is composed of the most significant one bit. The method of claim 1, And the lower bit data signal consists of n-1 bits. delete The method of claim 1, And two transistors for each bit data signal of the modulated signal. The method of claim 1,  The second control unit, An inverter for inverting the higher bit data signal; And And a second group of transistors controlled to the upper bit data signal and the bit data signal inverted by the inverter. The method according to claim 6, And the higher bit data signal and the inverted bit data signal have signals inverted from each other.

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