KR101191453B1 - Method for driving liquid crystal display panel - Google Patents

Abstract

A method of driving a liquid crystal display panel implementing a data driving reduction (DDR) method or a data line sharing (DLS) method using a common line having a storage on common line structure formed on a common line as a second gate line, respectively. This is provided. In the method of driving a liquid crystal display panel, a method of driving a liquid crystal display panel having a capacitor structure formed on a common line, the method comprising: a) applying a first scan signal to a first odd gate line and driving all odd data lines; Doing; b) applying a second scan signal to a first common line of a capacitor structure formed on the common line, wherein all even data lines are driven; c) applying a third scan signal to the first even gate line but driving all odd-numbered data lines; And d) applying a fourth scan signal to the second common line of the capacitor structure formed on the common line, driving all of the even-numbered data lines, until a last scan signal is applied, a) to d) step is performed repeatedly.

Liquid Crystal Display, Data Line Sharing, Reduced Data Drive, Dual Gate Line

Description

Driving method of liquid crystal display panel {METHOD FOR DRIVING LIQUID CRYSTAL DISPLAY PANEL}

1 is a perspective view of a general liquid crystal display.

2 is a view schematically showing a configuration of a general liquid crystal panel.

3 is a view for explaining a method of driving a liquid crystal display panel using a dual gate line according to the related art.

FIG. 4 is a diagram for describing a method of driving a liquid crystal display panel implementing data driving reduction (DDR) using a common line as a second gate line according to the first embodiment of the present invention.

FIG. 5 is a diagram for describing a driving method of a liquid crystal display panel implementing data line sharing (DLS) using a common line as a second gate line according to a second embodiment of the present invention.

The present invention relates to a liquid crystal display, and more particularly, to a method of driving a liquid crystal display panel of a data driving reduction (DDR) method and a data line sharing (DLS) method.

1 is a perspective view of a general liquid crystal display.

Referring to FIG. 1, a liquid crystal display device is injected between a first substrate 10, a second substrate 20, and the first substrate 10 and the second substrate 20 bonded to each other with a predetermined space. It consists of the liquid crystal layer 30. In this case, the first substrate 10 is defined as a TFT region TFT, a pixel region Pixel, and a storage region C _ST which are switching regions.

The first substrate 10 has a plurality of gate lines 12 arranged in one direction at regular intervals on the transparent glass substrate 11, and a plurality of gate lines 12 in a direction perpendicular to the gate line 12. By arranging the data lines 16, the pixel area Pixel is defined.

In addition, a pixel electrode 18 is formed in each pixel region Pixel, and a thin film transistor TFT is formed at a portion where each gate line 12 and the data line 16 cross each other. The data signal of the data line 16 is applied to each pixel electrode 18 in accordance with the scan signal applied through (12).

In the second substrate 20, a black matrix layer 22 is formed on the transparent glass substrate 21 to block light except for the pixel region Pixel, and the color corresponding to each pixel region is formed in the second substrate 20. R, G, and B color filter layers 23 are formed to represent the common electrode 24 on the color filter layer 23.

A charging capacitor C _ST connected in parallel with the pixel electrode 18 is configured on the gate line 12, and a portion of the gate line 12 is used as the first electrode of the charging capacitor C _ST . As the second electrode, an island-shaped metal pattern formed of the same material as the source and drain electrodes is used.

In the liquid crystal display, the liquid crystal layer 30 formed between the first substrate 10 and the second substrate 20 is aligned by an electric field between the pixel electrode 18 and the common electrode 24, and the liquid crystal layer is aligned. The desired image can be expressed by adjusting the amount of light passing through the liquid crystal layer 30 according to the degree of alignment of the 30.

2 is a diagram schematically illustrating a configuration of a general liquid crystal display panel.

As shown in FIG. 2, the general liquid crystal display panel includes a timing controller 40, a gate driver 50, a source driver 60, and a display panel region 70.

In the display panel region 70, a plurality of gate lines and data lines are formed in a matrix form. Thin film transistors (TFTs) are formed at intersections of the plurality of gate lines and data lines.

Although not shown in detail, the thin film transistor TFT includes a gate electrode, a source electrode, a drain electrode, an active layer, and an ohmic contact layer, and the drain electrode is connected to the pixel electrode to form a unit pixel. When the gate signal is applied to the gate electrode through the gate line, the thin film transistor TFT having such a structure operates by transferring the data signal applied to the data line from the source electrode to the drain electrode through the ohmic contact layer and the active layer. .

That is, when a data signal is applied to the source electrode, a voltage corresponding thereto is applied to the pixel electrode connected to the source electrode, which causes a voltage difference between the pixel electrode and the common electrode. In addition, due to the voltage difference between the pixel electrode and the common electrode, the molecular arrangement of the liquid crystal injected therein is changed, and the light transmittance of the pixel is changed due to the change in the molecular arrangement of the liquid crystal so that the data signal applied to each pixel is changed. The color difference of the pixel is generated according to the difference. Such a difference in color may be used to control the screen of the liquid crystal display.

In addition, a data signal applied to the source electrode is provided from the source driver 60, and a gate signal applied to the gate electrode is provided from the gate driver 50.

The gate driver 50 sequentially provides a gate signal to each gate line for activating or deactivating the gate electrode. Then, the source driver 60 provides the grayscale voltage corresponding to the data signal to the plurality of data lines in accordance with the timing at which the gate signal is applied. In this case, the synchronization between the source driver 60 and the gate driver 50 is performed by the timing controller T-CON 40.

Meanwhile, the data line sharing (DLS) method for reducing the number of source ICs is a method of independently driving odd and even pixels using two gate lines. Two gate lines are required to drive the pixel separation, but the data lines are cut in half. In addition, since the gate line is required twice as compared with the general driving method, the unit pixel charge time is reduced from 1H (horizontal period) to H / 2. In the case of applying such a DLS method, since an additional gate line is required, there is a problem that the aperture ratio is reduced accordingly.

Meanwhile, FIG. 3 is a view for explaining a method of driving a liquid crystal display panel using a double gate line according to the related art, and illustrates a data driving reduction (DDR) using a double gate line. . Here, reference numeral 80 denotes a unit pixel consisting of R, G, and B subpixels.

Referring to FIG. 3, a method of driving a liquid crystal display panel using a double gate line according to the related art is driven in the order of 1-> 2-> 3-> as shown in the drawing. In order to maintain a space between one gate line and two gate lines, a large area is consumed. Therefore, when the data driving reduction method is implemented, the aperture ratio of the pixel is reduced.

That is, when the data driving reduction method is applied using two gate lines, the aperture ratio of the pixel is reduced by the other gate line. In particular, in the case of a capacitor on common line structure, since the common electrode is formed in the same direction as the gate line, the aperture ratio is greatly reduced, and thus, the luminance of the liquid crystal display panel is reduced.

The technical problem to be achieved by the present invention is to use a common line of a capacitor (storage on common line) structure formed on a common line as the second gate line, it is possible to implement a data drive reduction (DDR) scheme without reducing the aperture ratio An object of the present invention is to provide a driving method of a liquid crystal display panel.

Another technical problem to be solved by the present invention is to drive a liquid crystal display panel capable of implementing a data line sharing (DLS) method of increasing an aperture ratio by using a common line of a capacitor structure formed on a common line as a second gate line. It is to provide a method.

The objects of the present invention are not limited to the above-mentioned objects, and other objects not mentioned can be clearly understood by those skilled in the art from the following description.

In order to achieve the above object, in the method of driving a liquid crystal display panel according to the present invention, a pixel of an m × n matrix array is defined by the intersection of m data lines and n gate lines, and a capacitor is formed on a common line. A method of driving a liquid crystal display panel having a storage on common line structure, the method comprising: a) applying a first scan signal to a first odd gate line and driving all odd-numbered data lines; b) applying a second scan signal to a first common line of a capacitor structure formed on the common line, wherein all even data lines are driven; c) applying a third scan signal to the first even gate line but driving all odd-numbered data lines; And d) applying a fourth scan signal to the second common line of the capacitor structure formed on the common line, driving all of the even-numbered data lines, until the last scan signal is applied; And d) to d).

Here, the gate line may be operated as a charging capacitor during its next stage operation after its stage is sequentially operated.

In this case, the scan signal is applied n times to drive m × n pixels constituting one frame.

The data line may be driven by a data driving reduction (DDR) scheme.

The capacitor common line formed on the gate line and the common line may be connected to a gate of the thin film transistor to apply the scan signal.

Meanwhile, in the method of driving a liquid crystal display panel according to the present invention, a capacitor having an m × n matrix array is defined by the intersection of m / 2 data lines and 2n gate lines, and is formed on a common line. A method of driving a liquid crystal display panel having a common line structure, the method comprising: a) applying a first scan signal to a first odd gate line and driving all odd-numbered data lines; b) applying a second scan signal to a first common line of a capacitor structure formed on the common line, wherein all even data lines are driven; c) applying a third scan signal to the first even gate line but driving all odd-numbered data lines; And d) applying a fourth scan signal to the second common line of the capacitor structure formed on the common line, driving all of the even-numbered data lines, until the last scan signal is applied; It is characterized by performing steps a) to d) repeatedly.

Here, the gate line may be operated as a charging capacitor during its next stage operation after its stage is sequentially operated.

In this case, the scan signal is applied n times to drive m × n pixels constituting one frame.

Here, the data line is driven by a data line sharing (DLS) method.

The capacitor common line formed on the gate line and the common line may be connected to a gate of the thin film transistor to apply the scan signal.

Specific details of other embodiments are included in the detailed description and the drawings. Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various forms, and the present embodiments are merely provided to make the disclosure of the present invention complete and the general knowledge in the art to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, the invention is defined only by the scope of the claims.

Hereinafter, a driving method of a liquid crystal display panel according to the present invention will be described in detail with reference to the accompanying drawings.

First, the embodiment of the present invention is largely divided into two. That is, a method of implementing a data driving reduction (DDR) method without reducing the aperture ratio by using a common line having a storage on common line structure as a second gate line and a capacitor formed on the common line By providing a data line sharing (DLS) scheme using a common line of the structure as the second gate line, a method of increasing the aperture ratio is provided.

4 is a diagram for describing a method of driving a liquid crystal display panel using a common line according to a first embodiment of the present invention as a second gate line.

Referring to FIG. 4, a data driving reduction (DDR) scheme is implemented by using a common line of a capacitor structure formed on an existing common line as a second gate line.

Specifically, in the driving method of the liquid crystal display panel according to the present invention, a pixel of an m × n matrix array is defined by the intersection of m data lines and n gate lines, and a capacitor is formed on a common line. It is applied to a liquid crystal display panel having a line) structure.

First, a first scan signal is applied to the first odd gate line {S (1) _O}, and all odd data lines R1, B1, and G2 are driven.

Next, the second scan signal is applied to the first common line {S (1) _E} of the capacitor structure formed on the common line, and drives all even-numbered data lines G1, R2, and B2.

Next, the third scan signal is applied to the first even gate line {S (2) _O}, and all odd-numbered data lines R3, B3, and G4 are driven.

Next, a fourth scan signal is applied to the second common line {S (2) _E} of the capacitor structure formed on the common line, and all the even-numbered data lines G3, R4, and B4 are driven.

Here, the above steps are repeated until the last n th scan signal is applied, and the scan signal is applied n times to drive m × n pixels constituting one frame.

In addition, the gate lines {S (1) _O and S (2) _O} are sequentially operated with their own stages, and then operate as charging capacitors during the next stage operation.

Here, the gate lines {S (1) _O, S (2) _O} and the common lines {S (1) _E, S (2) _E} of a capacitor structure formed on the common line apply the scan signal. It is connected to the gate of the thin film transistor.

As a result, the data line is driven in a Data Driving Reduction (DDR) scheme, in which the gate line is sequentially operated from above and then operated as a charging capacitor during the next stage operation. The pixels operate in the order of 1-> 2-> 3-> 4 as shown. The aperture ratio is maintained since there is little difference from the existing pixel structure.

5 is a view for explaining a method of driving a liquid crystal display panel using a common line as a second gate line according to the second embodiment of the present invention.

Referring to FIG. 5, a data line sharing (DLS) scheme is implemented by using a common line of a capacitor on a common line structure as a second gate line.

Specifically, on the other hand, in the method of driving the liquid crystal display panel according to the present invention, a capacitor having an m × n matrix array is defined by the intersection of m / 2 data lines and 2n gate lines, and is formed on a common line. The present invention is applied to a method of driving a liquid crystal display panel having a storage on common line structure.

First, a first scan signal is applied to the first odd gate line {S (1) _O}, and all odd data lines R1, B1, and G2 are driven.

Next, the second scan signal is applied to the first common line {S (1) _E} of the capacitor structure formed on the common line, and drives all even-numbered data lines G1, R2, and B2.

Next, the third scan signal is applied to the first even gate line {S (2) _O}, and all odd-numbered data lines R3, B3, and G4 are driven.

Next, a fourth scan signal is applied to the second common line {S (2) _E} of the capacitor structure formed on the common line, and all the even-numbered data lines G3, R4, and B4 are driven.

Here, the above steps are repeated until the last n th scan signal is applied, and the scan signal is applied n times to drive m × n pixels constituting one frame.

In addition, the gate lines {S (1) _O and S (2) _O} are sequentially operated with their own stages, and then operate as charging capacitors during the next stage operation.

Here, the gate lines {S (1) _O, S (2) _O} and the common lines {S (1) _E, S (2) _E} of a capacitor structure formed on the common line apply the scan signal. It is connected to the gate of the thin film transistor.

Therefore, the data line is driven by a data line sharing (DLS) method, in which the gate line operates sequentially from the top thereof, and then operates as a charging capacitor during the next stage operation. Pixel will work. If one of the data lines is removed as above, the aperture ratio is improved by the area.

As a result, the first embodiment of the present invention can implement DDR without reducing the aperture ratio in the existing pixel structure by using a common line of a storage on common line structure formed on a common line as a second gate line, or According to the second embodiment of the present invention, when the DLS is applied using a common line having a storage on common line structure formed on the common line as the second gate line, the aperture ratio may be increased.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. Therefore, the embodiments described above are to be understood in all respects as illustrative and not restrictive.

According to the present invention, the data driving reduction (DDR) can be implemented without reducing the aperture ratio in the existing pixel structure by using a common line having a storage on common line structure formed on the common line as the second gate line. Further, according to the present invention, the aperture ratio can be improved by applying the data line sharing (DLS) by using the common line of the capacitor structure formed on the common line as the second gate line.

Claims (10)

In a driving method of a liquid crystal display panel having pixels of an m × n matrix array defined by the intersection of m data lines and n gate lines, and having a storage on common line structure formed on a common line, a) applying a first scan signal to the first odd gate line, wherein all odd data lines are driven; b) applying a second scan signal to a first common line of a capacitor structure formed on the common line, wherein all even data lines are driven; c) applying a third scan signal to the first even gate line but driving all odd-numbered data lines; And d) applying a fourth scan signal to a second common line of a capacitor structure formed on the common line, and driving all even data lines / RTI > And repeating steps a) to d) until the last scan signal is applied. The method of claim 1, And the gate line is sequentially operated, and then operates as a charging capacitor during the next stage operation. The method of claim 1, The scan signal is applied n times to drive m x n pixels constituting one frame. The method of claim 1, And the data line is driven by a data driving reduction (DDR) method. The method of claim 1, And a capacitor common line formed on the gate line and the common line is connected to a gate of a thin film transistor to apply the scan signal. In a method of driving a liquid crystal display panel having a storage structure on a common line in which pixels of an m × n matrix array are defined by the intersection of m / 2 data lines and 2n gate lines, and are formed on a common line. , a) applying a first scan signal to the first odd gate line, wherein all odd data lines are driven; b) applying a second scan signal to a first common line of a capacitor structure formed on the common line, wherein all even data lines are driven; c) applying a third scan signal to the first even gate line but driving all odd-numbered data lines; And d) applying a fourth scan signal to a second common line of a capacitor structure formed on the common line, and driving all even data lines / RTI > And repeating steps a) to d) until the last scan signal is applied. The method of claim 6, And the gate line is sequentially operated, and then operates as a charging capacitor during the next stage operation. The method of claim 6, The scan signal is applied n times to drive m x n pixels constituting one frame. The method of claim 6, And the data line is driven by a data line sharing (DLS) method. The method of claim 6, And a capacitor common line formed on the gate line and the common line is connected to a gate of a thin film transistor to apply the scan signal.

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