KR101185456B1 - Semiconductor package - Google Patents

Semiconductor package Download PDF

Info

Publication number
KR101185456B1
KR101185456B1 KR1020100116034A KR20100116034A KR101185456B1 KR 101185456 B1 KR101185456 B1 KR 101185456B1 KR 1020100116034 A KR1020100116034 A KR 1020100116034A KR 20100116034 A KR20100116034 A KR 20100116034A KR 101185456 B1 KR101185456 B1 KR 101185456B1
Authority
KR
South Korea
Prior art keywords
chip
mems
semiconductor package
mounting plate
membrane
Prior art date
Application number
KR1020100116034A
Other languages
Korean (ko)
Other versions
KR20120054759A (en
Inventor
정구웅
김병진
이재웅
Original Assignee
앰코 테크놀로지 코리아 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 앰코 테크놀로지 코리아 주식회사 filed Critical 앰코 테크놀로지 코리아 주식회사
Priority to KR1020100116034A priority Critical patent/KR101185456B1/en
Publication of KR20120054759A publication Critical patent/KR20120054759A/en
Application granted granted Critical
Publication of KR101185456B1 publication Critical patent/KR101185456B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS

Abstract

본 발명은 반도체 패키지에 관한 것으로서, 더욱 상세하게는 멤스 칩 및 에이직 칩 등을 비롯한 도전성 와이어를 몰딩하여 견고하게 잡아주는 동시에 멤스칩의 진동 울림 공간인 백 불륨 공간을 용이하게 확보할 수 있는 새로운 구조의 반도체 패키지에 관한 것이다.
즉, 본 발명은 인쇄회로기판에 대신에 저렴한 리드프레임을 사용하되, 멤스 칩 및 에이직 칩을 비롯하여 도전성 와이어를 견고하게 잡아주어 와이어의 양끝단이 탈락되는 볼 오프 현상을 방지할 수 있고, 리드프레임에 다운셋 구조를 적용하여 백 볼륨 공간을 크게 증대시킨 새로운 구조의 반도체 패키지를 제공하고자 한 것이다.The present invention relates to a semiconductor package. More particularly, the present invention relates to a semiconductor package, in which a conductive wire including a MEMS chip and an AIC chip is molded and firmly held, and at the same time, it is possible to easily secure a back volume space, which is a vibration ringing space of the MEMS chip. A semiconductor package having a structure.
That is, the present invention uses an inexpensive lead frame instead of a printed circuit board, and firmly grips the conductive wires including MEMS chips and AIZ chips to prevent the ball-off phenomenon that both ends of the wires fall off. The present invention aims to provide a semiconductor package having a new structure in which a downset structure is applied to a frame, thereby greatly increasing the back volume space.

Description

반도체 패키지{Semiconductor package}Semiconductor Package {Semiconductor package}

본 발명은 반도체 패키지에 관한 것으로서, 더욱 상세하게는 멤스 칩 및 에이직 칩 등을 비롯한 도전성 와이어를 몰딩하여 견고하게 잡아주는 동시에 멤스칩의 진동 울림 공간인 백 불륨 공간을 용이하게 확보할 수 있는 새로운 구조의 반도체 패키지에 관한 것이다.
The present invention relates to a semiconductor package. More particularly, the present invention relates to a semiconductor package, in which a conductive wire including a MEMS chip and an AIC chip is molded and firmly held, and at the same time, it is possible to easily secure a back volume space, which is a vibration ringing space of the MEMS chip. A semiconductor package having a structure.

통상적으로, 압력, 가속도, 소리 또는 광과 같은 물리적 현상을 전기적 신호로 변환하는 마이크로-전자 기계적 시스템(MEMS) 디바이스가 공지되어 있으며, 여기에는 멤스(MEMS) 칩과 에이직(ASIC) 칩이 포함되어 있다.Typically, micro-electro-mechanical system (MEMS) devices are known that convert physical phenomena such as pressure, acceleration, sound or light into electrical signals, including MEMS chips and ASIC chips. It is.

일종의 반도체 패키지인 마이크로-전자 기계적 시스템 디바이스는 멤스 칩과 에이직 칩이 각종 기판(인쇄회로기판, 리드프레임, LCC 등)에 상하로 적층 부착되거나, 측방향으로 배열되는 구조로 제조되고 있다.A micro-electromechanical system device, which is a kind of semiconductor package, is manufactured in a structure in which MEMS chips and AICS chips are stacked on top of each other (printed circuit boards, lead frames, LCCs, etc.) or arranged laterally.

여기서, 종래의 멤스 디바이스에 대한 하나의 예를 첨부한 도 2를 참조로 살펴보면 다음과 같다.Here, referring to FIG. 2 attached to one example of a conventional MEMS device, it will be described.

인쇄회로기판(20)의 상면에 멤스 칩(10)과 이 멤스 칩(10)에 대한 신호 처리 소자인 에이직 칩(12)이 나란히 부착되고, 멤스 칩(10)과 에이직 칩(12)이 전기적 신호 전달 가능하게 도전성 와이어(24)로 연결됨과 함께 에이직 칩(12)과 기판(20) 간에도 전기적 신호 교환 가능하게 도전성 와이어(24)로 연결된다.The MEMS chip 10 and the AC chip 12, which is a signal processing element for the MEMS chip 10, are side by side attached to the upper surface of the printed circuit board 20, and the MEMS chip 10 and the AC chip 12 are attached. The conductive wires 24 are connected to the conductive wires 24 so that the electrical signals can be transferred, and the conductive wires 24 are also connected to the AC chip 12 and the substrate 20 so as to exchange electrical signals.

이때, 상기 멤스 칩(10)은 마이크로폰, 휴대용 마이크 등에 사용될 수 있는 칩으로서, 그 중앙부에 형성된 홀내에 음파를 감지하는 멤브레인(28)이 부착되어 있다.In this case, the MEMS chip 10 is a chip that can be used for a microphone, a portable microphone, and the like, and a membrane 28 for detecting sound waves is attached to a hole formed in the center thereof.

상기 기판(20)에는 음파에 의하여 멤브레인(28)이 진동하는 진동 울림 공간인 백 볼륨(back volume) 공간이 관통 형성되고, 또한 기판(20)의 위에는 멤스 칩(10)과 에이직 칩(12)을 비롯하여 와이어(24)를 외부로부터 보호하기 위한 외부캡(30)이 부착된다.The substrate 20 has a back volume space, which is a vibration ringing space in which the membrane 28 vibrates due to sound waves, and a MEMS chip 10 and an AC chip 12 on the substrate 20. In addition, the outer cap 30 is attached to protect the wire 24 from the outside.

따라서, 상기 외부캡(30)에 형성된 음파 유입구(32)을 통해 음파가 유입되면, 이 유입된 음파에 의하여 멤브레인(28)이 진동 울림 공간인 백 볼륨 공간(16)을 기반으로 진동을 하게 되고, 이 멤브레인(28)의 진동 신호가 멤스 칩(10)에서 에이직 칩(12)으로 전달되어 전기적 신호 처리된 후, 기판(20) 및 입출력단자(22)을 통해 출력된다.Therefore, when sound waves are introduced through the sound wave inlet 32 formed in the outer cap 30, the membrane 28 vibrates based on the back volume space 16 which is a vibration ringing space by the introduced sound waves. In addition, the vibration signal of the membrane 28 is transferred from the MEMS chip 10 to the AIPS chip 12 to be electrically processed, and then output through the substrate 20 and the input / output terminal 22.

그러나, 종래 기술의 일례에 따른 멤스 디바이스는 기판에 형성된 백 볼륨 공간이 작아 멤스 칩의 멤브레인이 제대로 울리지 않는 단점이 있고, 멤스 칩 및 에이직 칩을 비롯하여 와이어들이 단순히 캡에 의하여 씌여져 있을 뿐, 별도의 고정수단이 없기 때문에 외부의 진동 전달에 의하여 와이어의 양끝단이 탈락되는 볼 오프(ball off) 현상이 발생되는 문제점이 있었다.However, the MEMS device according to an example of the prior art has a disadvantage in that the membrane of the MEMS chip does not ring properly due to the small volume of the back volume formed on the substrate, and the wires including the MEMS chip and AIZ chip are simply covered by a cap. Since there is no fixing means, there is a problem that a ball off phenomenon occurs in which both ends of the wire are dropped by external vibration transmission.

종래의 멤스 디바이스에 대한 다른 예를 첨부한 도 3을 참조로 살펴보면 다음과 같다.Referring to Figure 3 attached to another example of a conventional MEMS device as follows.

종래기술의 다른 예에 따른 멤스 디바이스는 백 볼륨 공간(16)을 크게 확보한 점에 특징이 있다.The MEMS device according to another example of the related art is characterized in that the back volume space 16 is largely secured.

즉, 상기한 일례에 따른 멤스 디바이스와 그 구성은 동일하고, 단지 멤스 칩(10) 및 에이직 칩(12)을 기판(20) 상에 부착하지 않고, 기판(20) 상에 부착되는 내부캡(34) 위에 부착된 점에 차이가 있고, 특히 내부캡(34)의 내부공간(기판과의 사이공간)이 멤스 칩(10)의 멤브레인(28)을 위한 진동 울림 공간인 백 볼륨 공간(16)이 된다.That is, the MEMS device and its configuration according to the above example are the same, and the inner cap attached to the substrate 20 without attaching the MEMS chip 10 and the AC chip 12 to the substrate 20 only. There is a difference in the point of attachment above 34, in particular the inner volume of the inner cap 34 (space between the substrate) is the back volume space 16 which is a vibration ringing space for the membrane 28 of the MEMS chip 10. )

그러나, 종래 기술의 다른 예에 따른 멤스 디바이스는 기판에 형성된 백 볼륨 공간이 증대되어 멤스 칩의 멤브레인이 제대로 진동하게 되는 장점은 있으나, 여전히 멤스 칩 및 에이직 칩을 비롯하여 와이어들이 단순히 캡에 의하여 씌여져 있을 뿐, 별도의 고정수단이 없기 때문에 마찬가지로 외부의 진동 전달에 의하여 와이어의 양끝단이 탈락되는 볼 오프(ball off) 현상이 발생되는 문제점이 있었다.However, the MEMS device according to another example of the prior art has an advantage that the back volume space formed on the substrate is increased so that the membrane of the MEMS chip is vibrated properly, but still the wires including the MEMS chip and AIZ chip are simply covered by the cap. Since there is no separate fixing means, there is a problem that a ball off phenomenon occurs in that both ends of the wire are dropped by external vibration transmission.

종래의 멤스 디바이스에 대한 또 다른 예를 첨부한 도 4를 참조로 살펴보면 다음과 같다.Referring to Figure 4 attached to another example of a conventional MEMS device as follows.

종래기술의 또 다른 예에 따른 멤스 디바이스는 기판을 인쇄회로기판을 사용하지 않고 보다 저렴한 리드프레임을 사용한 점에 특징이 있다.MEMS device according to another example of the prior art is characterized in that the use of a cheaper lead frame instead of a printed circuit board.

즉, 리드프레임(40)의 칩탑재판(42)에 멤스 칩(10) 및 에이직 칩(12)이 부착되고, 멤스 칩(10)과 에이직 칩(12)이 도전성 와이어(24)로 연결되는 동시에 에이직 칩(12)과 리드프레임(40)의 각 리드(44)가 도전성 와이어(24)로 연결되며, 또한 칩탑재판(42) 및 리드(44)의 저면이 몰딩 컴파운드 수지(46)로 몰딩되고 그 상면에는 멤스 칩(10)과 에이직 칩(12)을 비롯하여 도전성 와이어(24)를 보호하기 위한 외부캡(30)이 부착된 구조로 제작된다.That is, the MEMS chip 10 and the AC chip 12 are attached to the chip mounting plate 42 of the lead frame 40, and the MEMS chip 10 and the AC chip 12 are connected to the conductive wire 24. At the same time, the lead chip 12 and each lead 44 of the lead frame 40 are connected to each other by a conductive wire 24, and the bottom surface of the chip mounting plate 42 and the lead 44 is formed of a molding compound resin ( 46 is molded into a structure having an outer cap 30 attached to the upper surface of the MEMS chip 10 and the AC chip 12 to protect the conductive wire 24.

이때, 상기 리드프레임(40)의 칩탑재판(42) 및 몰딩 컴파운드 수지(46)에는 멤스 칩(10)의 멤브레인(28)의 진동 울림 공간인 백 볼륨 공간(16)이 관통 형성된다.At this time, the chip mounting plate 42 and the molding compound 46 of the lead frame 40 is formed through the back volume space 16, which is a vibration ringing space of the membrane 28 of the MEMS chip 10.

그러나, 종래 기술의 또 다른 예에 따른 멤스 디바이스는 인쇄회로기판에 대신에 저렴한 리드프레임을 사용하여 제조원가를 절감할 수 있는 장점은 있으나, 여전히 멤스 칩 및 에이직 칩을 비롯하여 와이어들이 단순히 외부캡에 의하여 씌여져 있을 뿐, 별도의 고정수단이 없기 때문에 마찬가지로 외부의 진동 전달에 의하여 와이어의 양끝단이 탈락되는 볼 오프(ball off) 현상이 발생되는 문제점이 있고, 칩탑재판 및 몰딩 컴파운드 수지에 형성된 백 볼륨 공간이 작아 멤브레인의 진동 성능이 제대로 발휘되지 않는 단점이 있다.
However, the MEMS device according to another example of the prior art has the advantage of reducing the manufacturing cost by using an inexpensive lead frame instead of a printed circuit board, but wires including MEMS chips and AIZ chips are simply Since there is no separate fixing means, there is a problem in that a ball off phenomenon occurs at both ends of the wire due to external vibration transmission, and the bag formed on the chip mounting plate and the molding compound resin. Due to the small volume space, the vibration performance of the membrane is not properly exhibited.

본 발명은 상기한 종래 기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 인쇄회로기판에 대신에 저렴한 리드프레임을 사용하되, 멤스 칩 및 에이직 칩을 비롯하여 도전성 와이어를 견고하게 잡아주어 와이어의 양끝단이 탈락되는 볼 오프 현상을 방지할 수 있고, 리드프레임에 다운셋 구조를 적용하여 백 볼륨 공간을 크게 증대시킨 새로운 구조의 반도체 패키지를 제공하는데 그 목적이 있다.
The present invention has been made to solve the above-mentioned problems of the prior art, using an inexpensive lead frame instead of a printed circuit board, and firmly holding the conductive wire, including MEMS chip and AIZ chip, both ends of the wire It is an object of the present invention to provide a semiconductor package having a new structure that can prevent the ball-off phenomenon from falling off and greatly increase the back volume space by applying a downset structure to a lead frame.

상기한 목적을 달성하기 위한 본 발명은 리드프레임의 칩탑재판과; 상기 칩탑재판 상에 안착되는 내부캡과; 상기 내부캡의 상면에 나란히 부착되는 멤스 칩 및 에이직 칩과; 상기 멤스 칩의 멤브레인을 위한 진동 울림 공간으로서, 칩탑재판과 내부캡의 사이공간에 형성되는 백 볼륨 공간과; 상기 멤스 칩과 에이직 칩 간에 전기적 신호 전달 가능하게 연결되고, 상기 리드프레임의 리드와 에이직 칩간에 전기적 신호 전달 가능하게 연결되는 도전성 와이어와; 상기 리드의 외측단을 제외하고, 멤스 칩 및 에이직 칩을 비롯하여 와이어와 칩탑재판을 내재시키며 몰딩된 몰딩 컴파운드 수지; 로 구성된 것을 특징으로 반도체 패키지를 제공한다.The present invention for achieving the above object and the chip mounting plate of the lead frame; An inner cap seated on the chip mounting plate; MEMS chip and AIZ chip attached to the upper surface of the inner cap; Vibration ringing space for the membrane of the MEMS chip, the back volume space formed in the space between the chip mounting plate and the inner cap; A conductive wire connected between the MEMS chip and AIZ chip so as to be capable of transmitting electrical signals, and electrically connected between the lead of the lead frame and AIZ chip; Excluding the outer end of the lead, a molding compound resin molded by embedding the wire and the chip mounting plate, including MEMS chip and AIZ chip; It provides a semiconductor package comprising a.

본 발명의 바람직한 구현예로서, 상기 백 볼륨 공간은 내부캡을 받쳐주는 칩탑재판의 테두리단을 제외하고 그 안쪽영역을 다운셋시켜 형성된 것임을 특징으로 한다.In a preferred embodiment of the present invention, the back volume space is formed by downsetting the inner region of the chip except the edge of the chip mounting plate supporting the inner cap.

더욱 바람직하게는, 상기 칩탑재판의 저면은 몰딩 컴파운드 수지와 동일 평면을 이루면서 외부로 노출된 것을 특징으로 한다.More preferably, the bottom surface of the chip mounting plate is characterized in that it is exposed to the outside while forming the same plane as the molding compound resin.

특히, 상기 몰딩 컴파운드 수지의 상면에서 그 내부에 존재하는 멤스 칩의 멤브레인이 위치한 곳까지 레이저 드릴링에 의한 음파 유입구가 관통 형성된 것을 특징으로 한다.In particular, the sound wave inlet through the laser drilling is formed through the upper surface of the molding compound resin to the place where the membrane of the MEMS chip existing therein.

또한, 상기 내부캡은 평판형 구조로서 그 전체 면적중 멤스 칩의 멤브레인과 상하로 일치하는 곳에 관통구가 형성되어, 멤브레인과 백 볼륨 공간이 서로 연통되는 것을 특징으로 한다.
In addition, the inner cap has a flat plate-like structure, through-holes are formed at the upper and lower portions of the entire area of the membrane, so that the membrane and the back volume space communicate with each other.

상기한 과제 해결 수단을 통하여, 본 발명은 다음과 같은 효과를 제공한다.Through the above-mentioned means for solving the problems, the present invention provides the following effects.

본 발명에 따르면, 일종의 반도체 패키지인 멤스 디바이스를 구성함에 있어서, 인쇄회로기판에 대신에 저렴한 리드프레임을 사용하여 제조 원가를 절감할 수 있음은 물론이고, 멤스 칩 및 에이직 칩을 비롯하여 도전성 와이어를 몰딩 컴파운드 수지로 몰딩하여 도전성 와이어의 양끝단이 탈락되는 볼 오프 현상 등을 완전하게 방지시킬 수 있다.According to the present invention, in constructing a MEMS device, which is a kind of semiconductor package, it is possible to reduce manufacturing costs by using an inexpensive lead frame instead of a printed circuit board, and also to use conductive wires including MEMS chips and AICS chips. By molding with a molding compound resin, it is possible to completely prevent the ball-off phenomenon such that both ends of the conductive wire are dropped.

특히, 리드프레임의 칩탑재판 부분에 아래쪽으로 절곡되는 다운셋 구조를 적용하여, 멤스 칩의 멤브레인을 위한 진동 울림 공간인 백 볼륨 공간을 크게 증대시켜, 멤스 디바이스의 음파 감지 성능을 크게 향상시킬 수 있다.
In particular, by applying the downset structure bent downward to the chip mounting plate part of the lead frame, the back volume space, which is the vibration ringing space for the membrane of the MEMS chip, can be greatly increased, thereby significantly improving the sound wave detection performance of the MEMS device. have.

도 1은 본 발명에 따른 반도체 패키지를 나타내는 단면도,
도 2 내지 도 4는 종래의 반도체 패키지를 나타내는 단면도.1 is a cross-sectional view showing a semiconductor package according to the present invention;
2 to 4 are cross-sectional views showing a conventional semiconductor package.

이하, 본 발명의 바람직한 실시예를 첨부도면을 참조로 상세하게 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명은 리드프레임을 이용한 반도체 패키지의 일종인 멤스 디바이스로서, 멤스 칩 및 에이직 칩을 비롯한 도전성 와이어 등을 몰딩 컴파운드 수지로 몰딩하여, 멤스 칩 및 에이직 칩을 견고하게 고정시킬 수 있고, 또한 도전성 와이어의 양끝단이 탈락되는 볼 오프 현상 등을 완전하게 방지시킬 수 있으며, 멤스 칩의 멤브레인을 위한 진동 울림 공간인 백 볼륨 공간을 크게 증대시킨 점에 특징이 있다.The present invention is a MEMS device, which is a kind of semiconductor package using a lead frame, by molding a conductive compound such as MEMS chips and AICS chips with a molding compound resin, and firmly fixing MEMS chips and AICS chips, and It is possible to completely prevent the ball-off phenomenon such that both ends of the conductive wire are dropped, and the back volume space, which is a vibration ringing space for the membrane of the MEMS chip, is greatly increased.

이를 위해, 첨부한 도 1에 도시된 바와 같이 본 발명의 반도체 패키지에 채택된 리드프레임(40)은 칩탑재판(42)과 다수의 리드(44)가 동일 평면을 이루는 것을 채택되며, 특히 칩탑재판(42)은 테두리 영역을 제외한 그 안쪽 영역이 하향 절곡된 즉, 다운셋된 구조로 구비된다.To this end, as shown in the accompanying FIG. 1, the lead frame 40 adopted in the semiconductor package of the present invention adopts that the chip mounting plate 42 and the plurality of leads 44 form the same plane. The mounting plate 42 has a structure in which its inner region is bent downwardly, ie, downset except for the edge region.

이렇게 구비된 리드프레임(40)의 칩탑재판(42)의 상면 즉, 칩탑재판(42)의 테두리 영역에 평판형 구조를 갖는 내부캡(34)이 안착되는 바, 이 내부캡(34)의 전체 면적중 내부캡(34) 상에 부착되는 멤스 칩(10)의 멤브레인(28)과 상하로 일치하는 위치에 관통구(48)가 형성되어, 멤스 칩(10)의 멤브레인(28)과 백 볼륨 공간(16)이 서로 연통되는 상태가 된다.The inner cap 34 having a flat plate structure is mounted on the upper surface of the chip mounting plate 42 of the lead frame 40, that is, the edge region of the chip mounting plate 42. The through hole 48 is formed at a position vertically coincident with the membrane 28 of the MEMS chip 10 attached to the inner cap 34 of the total area of the MEMS chip 10. The back volume space 16 is in a state of communicating with each other.

이때, 상기 칩탑재판(42)의 다운셋된 공간은 칩탑재판(42)의 테두리 영역에 안착되는 내부캡(34)과 함께 하나의 밀폐된 공간으로 형성되고, 이 밀폐된 공간은 멤스 칩(10)의 멤브레인(28)을 위한 진동 울림 공간인 백 볼륨 공간(16)이 된다.In this case, the downset space of the chip mounting plate 42 is formed as one closed space together with the inner cap 34 seated on the edge region of the chip mounting plate 42, and the closed space is a MEMS chip. Back volume space 16, which is a vibration ringing space for membrane 28 of 10, becomes.

상기 내부캡(34)이 칩탑재판(42)의 테두리 영역에 받쳐지면서 부착된 상태에서, 내부캡(34)의 상면에 멤스 칩(10) 및 에이직 칩(12)이 접착수단을 매개로 좌우로 나란히 배열되며 부착된다.In a state where the inner cap 34 is attached to the edge region of the chip mounting plate 42, the MEMS chip 10 and the ACIC chip 12 are attached to the upper surface of the inner cap 34 by an adhesive means. It is arranged side by side and attached.

이에, 멤스 칩(10)의 멤브레인(28) 및 내부캡(34)의 관통구(48), 그리고 그 아래쪽의 백 볼륨 공간(16)이 서로 연통되는 상태가 된다.Accordingly, the membrane 28 of the MEMS chip 10, the through hole 48 of the inner cap 34, and the back volume space 16 under the MEMS chip 10 are in communication with each other.

이어서, 상기 멤스 칩(10)과 에이직 칩(12) 간에 전기적 신호 전달 가능하게 도전성 와이어(24)가 연결되고, 또한 상기 리드프레임(40)의 리드(44)와 에이직 칩(12) 간에 전기적 신호 전달 가능하게 도전성 와이어(24)가 연결된다.Subsequently, a conductive wire 24 is connected between the MEMS chip 10 and the AC chip 12 so as to transmit electrical signals, and between the lead 44 of the lead frame 40 and the AC chip 12. Conductive wires 24 are connected to enable electrical signal transmission.

다음으로, 상기 리드(44)의 외측단을 제외하고, 멤스 칩(10) 및 에이직 칩(12)을 비롯하여 와이어(24)와 칩탑재판(42)을 내재시키기 위한 몰딩 공정이 진행됨으로써, 마더보드와 같은 상대 부품에 연결되는 리드(44)의 외측단을 제외하고, 멤스 칩(10) 및 에이직 칩(12)을 비롯하여 와이어(24)와 칩탑재판(42) 등이 몰딩 컴파운드 수지(46)에 의하여 봉지되는 상태가 된다.Next, except for the outer end of the lead 44, the molding process for embedding the wire 24 and the chip mounting plate 42, including the MEMS chip 10 and AIZ chip 12, proceeds, Except for the outer end of the lead 44 which is connected to the mating component such as the motherboard, the wire 24 and the chip mounting plate 42, as well as the MEMS chip 10 and the AC chip 12, are molded compound resins. It will be in the state sealed by 46.

따라서, 상기 멤스 칩(10) 및 에이직 칩(12)을 비롯하여 도전성 와이어(24)가 몰딩 컴파운드 수지(46)로 몰딩되어 견고하게 고정되는 상태가 됨으로써, 기존에 외부캡만을 적용한 반도체 패키지에서 도전성 와이어의 양끝단이 외부력에 의하여 탈락되는 볼 오프 현상 등을 완전하게 방지시킬 수 있다.Accordingly, the conductive wires 24, including the MEMS chip 10 and the AC chip 12, are molded with the molding compound resin 46 to be firmly fixed, and thus, in the semiconductor package to which only an external cap is applied, the conductive wire 24 is electrically conductive. It is possible to completely prevent the ball-off phenomenon such that both ends of the wire is dropped by the external force.

한편, 상기 칩탑재판(42)의 저면 즉, 다운셋된 바닥판의 저면은 몰딩 컴파운드 수지(46)와 동일 평면을 이루면서 외부로 노출되도록 함으로써, 멤스 칩(10) 및 에이직 칩(12) 등에서 발생되는 열을 칩탑재판(42)의 저면을 통해 외부로 용이하게 방출시킬 수 있는 효과도 얻을 수 있다.Meanwhile, the bottom surface of the chip mounting plate 42, that is, the bottom surface of the downset bottom plate is exposed to the outside while being coplanar with the molding compound resin 46, so that the MEMS chip 10 and the ACIC chip 12 may be exposed. It is also possible to obtain an effect that the heat generated from the back can be easily released to the outside through the bottom of the chip mounting plate 42.

이렇게 몰딩 공정이 완료된 후, 몰딩 컴파운드 수지(46)의 상면에서 그 내부에 존재하는 멤스 칩(10)의 멤브레인(28)이 위치한 곳까지 몰딩 컴파운드 수지를 파내는 레이저 드릴링을 실시함으로써, 멤브레인(28)에 음파를 유입시키기 위한 음파 유입구(32)가 관통 형성된다.After the molding process is completed, laser drilling is performed to dig out the molding compound resin from the upper surface of the molding compound resin 46 to the place where the membrane 28 of the MEMS chip 10 existing therein, whereby the membrane 28 is formed. A sound wave inlet 32 for penetrating the sound wave is formed through.

이와 같은 구성으로 제작된 본 발명의 반도체 패키지가 마이크로폰을 내장한 스마트폰 또는 휴대용 마이크 등에 탑재된 상태에서의 전기적 신호 동작 흐름을 살펴보면, 먼저 특정 음성으로부터 발생된 음파가 몰딩 컴파운드 수지(46)의 레이저 드릴링에 의하여 형성된 음파 유입구(32)로 유입되어, 멤스 칩(10)의 멤브레인(28)에 닿으면, 멤브레인(28)이 진동을 하게 된다.Looking at the flow of the electrical signal operation in a state in which the semiconductor package of the present invention manufactured in such a configuration is mounted on a smartphone or a portable microphone with a built-in microphone, first, sound waves generated from a specific voice are lasers of the molding compound resin 46. When the membrane is introduced into the sound wave inlet 32 formed by the drilling and contacts the membrane 28 of the MEMS chip 10, the membrane 28 vibrates.

이때, 상기 칩탑재판(42)의 다운셋된 공간 즉, 내부캡(34)과 함께 하나의 밀폐된 공간으로 형성된 진동 울림 공간인 백 볼륨 공간(16)이 넓게 형성됨에 따라, 멤브레인(28)의 진동 울림이 원할하게 이루어지게 되어, 결국 멤브레인(28)의 진동 성능이 최대로 발휘될 수 있다.At this time, as the back volume space of the chip mounting plate 42, that is, the back volume space 16, which is a vibration ringing space formed as one closed space together with the inner cap 34, is widened, the membrane 28 The oscillation of the vibration is made smoothly, so that the vibration performance of the membrane 28 can be maximized.

이에, 멤브레인(28)의 진동 신호가 멤스 칩(10)에서 에이직 칩(12)으로 전달되어 전기적 신호로 변환 처리된 후, 와이어(24) 및 리드(44)를 통해 출력된다.Accordingly, the vibration signal of the membrane 28 is transferred from the MEMS chip 10 to the AIPS chip 12 and converted into an electrical signal, and then output through the wire 24 and the lead 44.

이상과 같이, 본 발명에 따른 반도체 패키지는 인쇄회로기판에 대신에 저렴한 리드프레임을 사용하여 제조 원가를 절감할 수 있고, 멤스 칩 및 에이직 칩을 비롯하여 도전성 와이어를 몰딩 컴파운드 수지로 몰딩하여 외부력에 의하여 도전성 와이어가 단락되는 등의 볼 오프 현상을 완전하게 방지시킬 수 있으며, 칩탑재판에 다운셋 구조를 적용하여 멤스 칩의 멤브레인을 위한 진동 울림 공간인 백 볼륨 공간을 크게 증대시켜, 멤스 디바이스의 음파 감지 성능을 크게 향상시킬 수 있다.
As described above, the semiconductor package according to the present invention can reduce the manufacturing cost by using an inexpensive lead frame instead of a printed circuit board, and by molding the conductive wire, including the MEMS chip and AIZ chip, with a molding compound resin, the external force The ball-off phenomenon such as short circuit of conductive wires can be completely prevented, and the downset structure is applied to the chip mounting board to greatly increase the back volume space, which is a vibration ringing space for the membrane of the MEMS chip. It can greatly improve the sound wave detection performance of.

10 : 멤스 칩 12 : 에이직 칩
16 : 백 볼륨 공간 20 : 기판
22 : 입출력단자 24 : 와이어
28 : 멤브레인 30 : 외부캡
32 : 음파 유입구 34 : 내부캡
40 : 리드프레임 42 : 칩탑재판
44 : 리드 46 : 몰딩 컴파운드 수지
48 : 관통구10: MEMS chip 12: AIZ chip
16: back volume space 20: substrate
22: input and output terminal 24: wire
28: membrane 30: outer cap
32: sound wave inlet 34: inner cap
40: lead frame 42: chip mounting plate
44: lead 46: molding compound resin
48: through hole

Claims (5)

리드프레임(40)의 칩탑재판(42)과;
상기 칩탑재판(42) 상에 안착되는 내부캡(34)과;
상기 내부캡(34)의 상면에 나란히 부착되는 멤스 칩(10) 및 에이직 칩(12)과;
상기 멤스 칩(10)의 멤브레인(28)을 위한 진동 울림 공간으로서, 칩탑재판(42)과 내부캡(34)의 사이공간에 형성되는 백 볼륨 공간(16)과;
상기 멤스 칩(10)과 에이직 칩(12) 간에 전기적 신호 전달 가능하게 연결되고, 상기 리드프레임(40)의 리드(44)와 에이직 칩(12) 간에 전기적 신호 전달 가능하게 연결되는 도전성 와이어(24)와;
상기 리드(44)의 외측단을 제외하고, 멤스 칩(10) 및 에이직 칩(12)을 비롯하여 와이어(24)와 칩탑재판(42)을 내재시키며 몰딩하고, 상면에는 멤스 칩(10)의 멤브레인(28)이 위치한 곳까지 레이저 드릴링에 의한 음파 유입구(32)가 관통 형성된 몰딩 컴파운드 수지(46);
로 구성된 것을 특징으로 반도체 패키지.
A chip mounting plate 42 of the lead frame 40;
An inner cap 34 seated on the chip mounting plate 42;
A MEMS chip 10 and an AC chip 12 attached to the upper surface of the inner cap 34;
A back volume space 16 formed in a space between the chip mounting plate 42 and the inner cap 34 as a vibration ringing space for the membrane 28 of the MEMS chip 10;
A conductive wire connected between the MEMS chip 10 and the AC chip 12 so as to be capable of transmitting electrical signals, and electrically connected between the lead 44 of the lead frame 40 and the AC chip 12. 24;
With the exception of the outer end of the lead 44, the MEMS chip 10 and the AC chip 12, including the wire 24 and the chip mounting plate 42 are embedded therein and molded, and the MEMS chip 10 on the upper surface thereof. A molding compound resin 46 in which a sound wave inlet 32 is penetrated by laser drilling to a place where the membrane 28 is located;
Semiconductor package, characterized in that consisting of.
청구항 1에 있어서,
상기 백 볼륨 공간(16)은 내부캡(34)을 받쳐주는 칩탑재판(42)의 테두리단을 제외하고 그 안쪽영역을 다운셋시켜 형성된 것임을 특징으로 하는 반도체 패키지.
The method according to claim 1,
The back volume space (16) is a semiconductor package, characterized in that formed by downsetting the inner region except the edge of the chip mounting plate 42 supporting the inner cap (34).
청구항 1에 있어서,
상기 칩탑재판(42)의 저면은 몰딩 컴파운드 수지(46)와 동일 평면을 이루면서 외부로 노출된 것을 특징으로 하는 반도체 패키지.
The method according to claim 1,
The bottom surface of the chip mounting plate 42 is a semiconductor package, characterized in that it is exposed to the outside while forming the same plane as the molding compound resin (46).
삭제delete 청구항 1에 있어서,
상기 내부캡(34)은 평판형 구조로서 그 전체 면적중 멤스 칩(10)의 멤브레인(28)과 상하로 일치하는 곳에 관통구(48)가 형성되어, 멤브레인(28)과 백 볼륨 공간(16)이 서로 연통되는 것을 특징으로 하는 반도체 패키지.The method according to claim 1,
The inner cap 34 has a flat plate-like structure, and a through hole 48 is formed at a position corresponding to the membrane 28 of the MEMS chip 10 up and down, and the membrane 28 and the back volume space 16 are formed. ) Is in communication with each other.
KR1020100116034A 2010-11-22 2010-11-22 Semiconductor package KR101185456B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100116034A KR101185456B1 (en) 2010-11-22 2010-11-22 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100116034A KR101185456B1 (en) 2010-11-22 2010-11-22 Semiconductor package

Publications (2)

Publication Number Publication Date
KR20120054759A KR20120054759A (en) 2012-05-31
KR101185456B1 true KR101185456B1 (en) 2012-10-02

Family

ID=46270458

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100116034A KR101185456B1 (en) 2010-11-22 2010-11-22 Semiconductor package

Country Status (1)

Country Link
KR (1) KR101185456B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101688077B1 (en) 2015-01-08 2016-12-20 앰코 테크놀로지 코리아 주식회사 Semiconductor package structure and manufacturing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100722687B1 (en) 2006-05-09 2007-05-30 주식회사 비에스이 Directional silicon condenser microphone having additional back chamber
US20080298621A1 (en) 2007-06-01 2008-12-04 Infineon Technologies Ag Module including a micro-electro-mechanical microphone

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100722687B1 (en) 2006-05-09 2007-05-30 주식회사 비에스이 Directional silicon condenser microphone having additional back chamber
US20080298621A1 (en) 2007-06-01 2008-12-04 Infineon Technologies Ag Module including a micro-electro-mechanical microphone

Also Published As

Publication number Publication date
KR20120054759A (en) 2012-05-31

Similar Documents

Publication Publication Date Title
US9998812B2 (en) Surface mountable microphone package, a microphone arrangement, a mobile phone and a method for recording microphone signals
US9108840B2 (en) MEMS microphone and method for packaging the same
US9648427B2 (en) MEMS microphone
KR101614330B1 (en) An anti-impact silicon based mems microphone, a system and a package with the same
US9992563B2 (en) MEMS microphone
US20200045476A1 (en) Terminal assembly structure of mems microphone
US20170320726A1 (en) MEMS Package
US9319772B2 (en) Multi-floor type MEMS microphone
US20090002961A1 (en) Packaging system with hollow package
US9517928B2 (en) Micromechanical functional apparatus, particularly a loudspeaker apparatus, and appropriate method of manufacture
CN109413554B (en) Directional MEMS microphone
CN109644307B (en) Microphone and pressure sensor package and method of manufacturing microphone and pressure sensor package
CN210579221U (en) Silicon microphone
TW201608904A (en) Stacked MEMS microphone packaging method
CN209072736U (en) A kind of directive property MEMS microphone
KR101185456B1 (en) Semiconductor package
KR101496192B1 (en) Mems microphone having piezo membrane
KR101953089B1 (en) Lead frame-based chip carrier used in the fabrication of mems transducer packages
US20150156575A1 (en) Microphone package and method of manufacturing the same
KR101300572B1 (en) Semicounductor package having Micro Electronic Mechnical System
KR101366418B1 (en) Semiconductor device
US9309108B2 (en) MEMS microphone packaging method
CN213818178U (en) MEMS vibration sensor die
JP2009260924A (en) Microphone and method of manufacturing the same
KR101209475B1 (en) Semiconductor package using interposer

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20150902

Year of fee payment: 4

FPAY Annual fee payment

Payment date: 20160902

Year of fee payment: 5

FPAY Annual fee payment

Payment date: 20170911

Year of fee payment: 6

FPAY Annual fee payment

Payment date: 20180911

Year of fee payment: 7