KR101167519B1 - Balancer of electric double layer capacitor - Google Patents

Abstract

PURPOSE: A balancer of an electric double layer capacitor is provided to prevent internal short by alternatively operating a first balancing transistor and a second balancing transistor. CONSTITUTION: A first electric double layer capacitor(10) includes a first terminal(11) and a second terminal(12). A second electric double capacitor(20) is connected to the first electric double layer capacitor in series. A first voltage detector(30) detects a charging voltage of the first electric double layer capacitor. A second voltage detector(40) detects a charging voltage of the second electric double layer capacitor. A balancing control circuit(80) generates a balancing control signal by sensing an output of the first voltage detector and the second voltage detector.

Description

BALANCER OF ELECTRIC DOUBLE LAYER CAPACITOR}

The present invention relates to a balancer of an electric double layer capacitor, and more particularly, to reduce the cost by reducing the number of balancing resistors in half in an electric double layer capacitor (EDLC) module, when both electric double layer capacitors are overcharged. The present invention relates to a balancer of an electric double layer capacitor capable of preventing an internal short circuit from occurring by alternately operating the first balancing transistor and the second balancing transistor.

In general, an electric double layer capacitor (EDLC) has an advantage of having a large capacitance due to its structural characteristics, but has a disadvantage that the rated voltage is significantly lower than that of other capacitors.

Accordingly, since the voltage normally required in practical use is significantly higher than the EDLC rated voltage, a module in which several EDLC cells are connected in series is used. However, as described above, in a module in which several cells are connected in series, charging voltages appearing at both ends of the cells are not the same due to characteristic variations such as capacitance and leakage current of the cells constituting the module.

On the other hand, the rated voltage of the module can be seen as the sum of the rated voltages of all the cells constituting the module. In addition, a high voltage exceeding a rated voltage is applied to a specific cell, which may cause a problem of damage to the cell.

Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to use two balancing transistors as transistors of different polarity in an electric double layer capacitor (EDLC) module, so that the circuits are complementary to each other. Complementarity allows the use of a single balancing resistor for two electric double layer capacitors, effectively discharging the electrical energy of multiple overcharged electric double layer capacitors (EDLC) and reducing the number of balancing resistors In addition to savings, the company also offers a balancer of electrical double layer capacitors that can reduce the weight of the entire module.

Another object of the present invention is to operate two balancing transistors in time when two electric double layer capacitors constituting a block are both overcharged so that the two balancing transistors are not turned on at the same time. In addition, while maintaining the balancing operation, by sending a signal to the external circuit that the block is in an overcharged state, the charger operation can be freely controlled in consideration of the voltage charged in the entire module from the outside and the number of blocks in the overcharged state. It is possible to provide a balancer that can solve both the problem of not getting enough charging voltage to protect the cell and the problem of damaging the cell by being charged for a long time in an overcharge state.

The balancer of the electric double layer capacitor according to the present invention for achieving the above objects comprises: a first electric double layer capacitor having a first terminal and a second terminal; A second electric double layer capacitor connected in series with said first electric double layer capacitor, said second electric double layer capacitor having a first terminal and a second terminal; A first voltage detector connected in parallel to the first electric double layer capacitor and detecting a charging voltage of the first electric double layer capacitor; A second voltage detector connected in parallel to the second electric double layer capacitor and detecting a charging voltage of the second electric double layer capacitor; A balancing control circuit for sensing outputs of the first and second voltage detectors to generate a balancing control signal; First and second balancing transistors having different polarities, each of which is turned on / off in accordance with a control signal of the balancing control circuit; One end is electrically connected between the first and second balancing transistors having different polarities, and the other end is electrically connected between the first and second electric double layer capacitors so that the first and second electric double layer capacitors are electrically connected. It is characterized by consisting of a single balancing resistor to discharge the excess current of.

Here, the first and second voltage detectors output Low as the control signal before the charging voltage reaches the set maximum charging voltage, and when the charging voltage reaches the maximum charging voltage, the control signal is changed from low to high. And the first and second voltage detectors maintain the control signal high until the first and second electric double layer capacitors are discharged and the charging voltage drops to reach a predetermined balancing stop voltage. When the charging voltage reaches the balancing stop voltage, it is preferable that the respective control signals are outputted by switching from high to low.

The output of the first voltage detector is connected to a first input terminal of the balancing control circuit, and the output of the second voltage detector is connected to a second input terminal of the balancing control circuit. The first output terminal of is connected to the gate (Gate) of the first balancing transistor via an inverting logic circuit, the second output terminal of the balancing control circuit is connected to the gate (Gate) of the second balancing transistor, the balancing Preferably, the third output terminal of the control circuit is connected to an external circuit terminal.

The output of the first voltage detector is connected to the first input terminal of the first logic circuit and the first input terminal of the second logic circuit, and the output of the second voltage detector is connected to the second input of the first logic circuit. An input terminal and a second input terminal of a third logic circuit, an output of the first logic circuit is connected to an input terminal of the time signal generator, and a first output terminal of the time signal generator A second output terminal of the time signal generator is connected to a first input terminal of the third logic circuit, an output terminal of the second logic circuit is connected to a gate of the first balancing transistor, Preferably, the output terminal of the third logic circuit is connected to the gate of the second balancing transistor.

Further, when the inputs of the first input terminal and the second input terminal of the balancing control circuit are both High (1), the outputs of the first and second output terminals of the balancing control circuit are set to High (1) at a predetermined time period. ) And Low (0) are alternately outputted, and the output of the third output terminal is Low (0).

In addition, the one end of the balancing resistor is connected to the drain of the first and second balancing transistor, the other terminal is the second terminal of the first electric double layer capacitor and the second of the second electric double layer capacitor It is preferably connected to one terminal.

In addition, the current flowing through the balancing resistor may flow in a wave form according to a period arbitrarily set in the time signal generator.

In addition, when the first balancing transistor is a P-channel FET or a PNP transistor, it is preferable that the second balancing transistor is an N-channel FET or an NPN transistor, respectively.

Further, if the first balancing transistor is the P-Channel FET, the second logic circuit is configured as a NAND circuit, and if the second balancing transistor is the N-Channel FET, the third logic circuit is preferably configured as an AND circuit. Do.

In addition, it is preferable that the two first and second electric double layer capacitors are connected in series to form one block, and the blocks are again connected in series to form one module.

Further, when the output of the first voltage detector is high and the output of the second voltage detector is low, the first balancing transistor is turned on and maintained until the output of the first voltage detector changes to low. When the output of the second voltage detector is high and the output of the first voltage detector is low, the second balancing transistor is turned on and maintained until the output of the second voltage detector changes to low. If the output is high and the output of the second voltage detector is also high, the operation of alternately turning on the first balancing transistor and the second balancing transistor is either one of the output of the first voltage detector or the output of the second voltage detector is low. It is preferable to keep until it changes to.

In addition, when the output of the first voltage detector is high and the output of the second voltage detector is also high, the output of the third output terminal is turned low so that either the output of the first voltage detector or the output of the second voltage detector is It is desirable to provide information so that the charger can be controlled in consideration of the number of blocks in an overcharge state in the external circuit by keeping it until the low level is changed.

According to the balancer of the electric double layer capacitor as described above, the EDLC module does not internally short-circuit the balancing transistor even when the charging voltages of the two first and second electric double layer capacitors constituting the block reach the rated voltage. Since the balancing operation can be continued, the external circuit can add an appropriate number of blocks from the point when the charging voltages of the two electric double layer capacitors constituting the specific block first reach the rated voltage in the module composed of a plurality of blocks. Since the charge voltage of all the double layer capacitors does not exceed the rated voltage until the charger is shut down because it determines that both pairs of electrical double layer capacitors have overcharged, the damage of the electric double layer capacitors due to overcharge is prevented. Preventable In addition, since the two electric double layer capacitors are not damaged due to continuous balancing operation even after the charge voltages of the two electric double layer capacitors reach the rated voltage, the overcharge signal output from multiple blocks and the voltage charged across the module A comprehensive analysis can be performed to stop or restart the charger when one or more of the blocks or an appropriate number of blocks reach an overcharge state and the charging voltage of the module as a whole reaches an appropriate voltage. It is possible to freely select the conditions at the time of starting and the time of recharging, which is an excellent effect of ensuring high charging energy throughout the module.

1 is a schematic circuit diagram illustrating a balancer of an electric double layer capacitor according to an embodiment of the present invention.
2 is a truth table for explaining a balancing control circuit of an electric double layer capacitor according to an embodiment of the present invention.
Figure 3 is a waveform diagram for explaining the operation of the balancer according to an embodiment of the present invention more easily.
4 is a schematic circuit diagram illustrating a balancer of an electric double layer capacitor according to another embodiment of the present invention.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. .

1 is a schematic circuit diagram illustrating a balancer of an electric double layer capacitor according to an embodiment of the present invention, and FIG. 2 is a truth table for explaining a balancing control circuit of the electric double layer capacitor according to an embodiment of the present invention. .

First, as shown in FIG. 1, a balancer 1 of an electric double layer capacitor according to an embodiment of the present invention includes a first electric double layer capacitor 10 having a first terminal 11 and a second terminal 12. )Wow; A second electric double layer capacitor (20) connected in series with said first electric double layer capacitor (10) and having a first terminal (21) and a second terminal (22); A first voltage detector (30) connected in parallel with the first electric double layer capacitor (10) and detecting a charging voltage of the first electric double layer capacitor (10); A second voltage detector (40) connected in parallel with the second electric double layer capacitor (20) to detect a charging voltage of the second electric double layer capacitor (20); A balancing control circuit (80) for detecting outputs of the first and second voltage detectors (30) and (40) to generate a balancing control signal; First and second balancing transistors (50) (60) having different polarities in which turn-on / turn-off is controlled according to a control signal of the balancing control circuit; One terminal is electrically connected between the first and second balancing transistors 50 and 60 having different polarities, and the other terminal is electrically connected between the first and second electric double layer capacitors 10 and 20. And a single balancing resistor 70 which discharges excess current of the first and second electric double layer capacitors.

Here, although the first and second electric double layer capacitors 10 and 20 are shown in the illustrated example, at least another pair of electric double layer capacitors is additionally configured in block units. That is, two first and second electric double layer capacitors 10 and 20 are connected in series to form one block, and the blocks are again connected in series to form one module. Accordingly, when both of the first and second electric double layer capacitors 10 and 20 constituting the block are overcharged, the first and second balancing transistors 50 and 60 are alternately operated in time to perform the first operation. And maintaining the balancing operation while preventing the second balancing transistors 50 and 60 from being turned on at the same time, and sending a signal to the external circuit as described below to indicate that the block is in an overcharged state and charged to the entire module from the outside. Considering the voltage and the number of blocks in the overcharge state, the charger operation can be properly controlled.

The first electric double layer capacitor 10 stores electrical energy and includes a first terminal 11 and a second terminal 12. The first electric double layer capacitor 10 has a large capacitance and is capable of rapid charging within a few seconds to several tens of seconds.

The second electric double layer capacitor 20 also stores electrical energy in the same manner as the first electric double layer capacitor 10. The second electric double layer capacitor 20 is connected in series with the first electric double layer capacitor 10 and includes a first terminal 21 and a second terminal 22. That is, the second terminal 12 of the first electric double layer capacitor 10 and the first terminal 21 of the second electric double layer capacitor 20 are electrically connected to each other so that the first electric double layer capacitor 10 is connected. And the second electric double layer capacitor 20 are connected in series.

Meanwhile, the first voltage detector 30 is connected in parallel with the first electric double layer capacitor 10 to detect the charging voltage of the first electric double layer capacitor 10. The output of the first voltage detector 30 is connected to the first input terminal 81-1 of the balancing control circuit 80. Here, the first voltage detector 30 outputs Low as the control signal DS1 before the charging voltage VC1 reaches the arbitrarily set maximum charging voltage VH1, and then the charging voltage VC1 reaches the maximum charging. When the voltage VH1 is reached, the control signal DS1 is switched from low to high (see FIG. 3).

The second voltage detector 40 is connected in parallel with the second electric double layer capacitor 20 to detect the charging voltage of the second electric double layer capacitor 20. The output of the second voltage detector 40 is connected to the second input terminal 81-2 of the balancing control circuit 80. The second voltage detector 40 outputs Low to the balancing control circuit 80 as the control signal DS2 before the charging voltage VC2 reaches the arbitrarily set maximum charging voltage VH2. When VC2 reaches the maximum charging voltage VH2, the control signal DS2 is switched from low to high (see FIG. 3).

The first output terminal 82-1 of the balancing control circuit 80 is connected to a gate of the first balancing transistor 50 via an inversion logic circuit 90 whose polarity is inverted. The second output terminal 82-2 of the balancing control circuit 80 is connected to a gate of the second balancing transistor 60, and the third output terminal 82-3 of the balancing control circuit 80 is provided. ) Is connected to the external circuit terminal (3).

On the other hand, since the first balancing transistor 50 is a P channel FET, the polarity of the signal supplied to its gate should be inverted through the inversion logic circuit 90. Therefore, the output signal of the first output terminal 82-1 of the balancing control circuit 80 is inverted from High to Low or Low to High through the inversion logic circuit 90 to be supplied to the gate. .

On the other hand, the first voltage detector 30 has a hysteresis characteristic so that the first electric double layer capacitor 10 is discharged and the charging voltage VC1 is lowered to the balancing stop voltage VL1 that is arbitrarily set. It maintains a high state until it reaches, but when the charging voltage VC1 reaches the balancing stop voltage VL1, the control signal DS1 is outputted by switching from high to low (see FIG. 3).

Here, the second voltage detector 40 also has a hysteresis characteristic, so that the second electric double layer capacitor 20 is discharged so that the charging voltage VC2 drops to the balancing stop voltage VL2 arbitrarily set. It maintains high state until it reaches | attains, and when charging voltage VC2 reaches the balancing stop voltage VL2, control signal DS2 is switched from high to low, and it outputs to the balancing control circuit 80 (FIG. 3). Reference).

Here, when the first balancing transistor 50 is a known P-channel FET or a PNP transistor, the second balancing transistor 50 may be a known N-channel FET or an NPN transistor. It consists of. Of course, when the first balancing transistor 40 is an N-channel FET or an NPN transistor, the second balancing transistor 50 is configured as a P-channel FET or a PNP transistor to have different polarities. do.

Of course, the illustrated example shows a case in which the first and second balancing transistors 50 and 60 are P or N channel FETs or PNP or NPN transistors. It can also comprise, and does not limit the kind in this invention.

Thus, by using the first and second balancing transistors 50 and 60 as transistors of different polarities, the circuits have complementarity to each other, thus providing a single for the two electric double layer capacitors 10 and 20. Will be able to use the balancing resistor (70).

The single balancing resistor 70 discharges excess current that is overcharged in the first and second electric double layer capacitors 10 and 20 to emit thermal energy.

One end (one terminal) of the balancing resistor 70 is connected to the second terminal 12 of the first electric double layer capacitor 10 and the first terminal 21 of the second electric double layer capacitor 20 and the balancing resistor. The other terminal of 70 is connected to the drains of the first and second balancing transistors 50 and 60.

On the other hand, the above-described balancing control circuit 80, as described above, the first and second input terminals 81-1 and 81-2 and the first to third output terminals 82-1 and 82-. 2) 82-3, wherein the first and second input terminals 81-1 and 81-2 are electrically connected to the outputs of the first and second voltage detectors 30 and 40, respectively. The first output terminal 82-1 of the balancing control circuit 80 is connected to a gate of the first balancing transistor 50 via an inverting logic circuit 90, and the balancing control circuit. The second output terminal 82-2 of 80 is connected to the gate of the second balancing transistor 60, and the third output terminal 82-3 of the balancing control circuit 80 is external. It is connected to the circuit terminal (3).

More specifically, this will be described with the truth table (眞 理 表) of FIG. 2 as follows.

That is, as shown in FIG. 2, when both the first input terminal 81-1 and the second input terminal 81-2 of the balancing control circuit 80 are Low (0), the first output terminal 82 is used. -1) and the output of the second output terminal 82-2 are low (0), and the output of the third output terminal 82-3 is high (1).

If the input of the first input terminal 81-1 is High (1) and the input of the second input terminal 81-2 is Low (0), the first and third output terminals 82-1 ( The output of 82-3) is High (1), and the output of the second output terminal 82-2 is Low (0).

In addition, when the input of the first input terminal 81-1 is Low (0) and the input of the second input terminal 81-2 is High (1), the output of the first output terminal 82-1 is Low (0), and the outputs of the second and third output terminals 82-2 and 82-3 are high (1).

Here, when the inputs of the first input terminal 81-1 and the second input terminal 81-2 are both high (1), the output of the first and second output terminals 82-1 and 82-2. Outputs alternating High (1) and Low (0) alternately at randomly set time intervals, and the output of the third output terminal 82-3 is Low (0).

That is, when the output of the first output terminal 82-1 is High (1) when the inputs of the first input terminal 81-1 and the second input terminal 81-2 are both High (1), 2 If the output of the output terminal 82-2 is Low (0), and the output of the second output terminal 82-2 is High (1), the first and second output terminals 82-1 and 82-2. ) Output becomes Low (0).

On the other hand, Figure 3 is a waveform diagram for explaining the operation of the balancer according to an embodiment of the present invention more easily understood, the operation of the entire balancer according to the present invention with reference to Figures 1 and 2 together It will be described below in detail to make it easier to do.

First, since the first electric double layer capacitor 10 and the second electric double layer capacitor 20 are not fully charged at the time t0, the control signals DS1 and DS2 are both kept low (0). Therefore, since the first input terminal 81-1 (hereinafter referred to as I1) and the second input terminal 81-2 (hereinafter referred to as I2) are both Low (0), the first output terminal 82-1 ( Hereinafter, both O1 and the second output terminal 82-2 (hereinafter O2) are Low (0), and the third output terminal 82-3 (hereinafter O3) is High (1). Accordingly, O1 and O2 of the balancing control circuit 80 also maintain Low (0), so that the first balancing transistor 50 and the second balancing transistor 60 are turned off and the charger (not shown) continuously supplies current. And charges the first electric double layer capacitor 10 and the second electric double layer capacitor 20.

When the charging voltage of the first electric double layer capacitor 10 reaches the maximum charging voltage VH1 at the time t1, the first voltage detector 30 switches the control signal from low to high to I1 of the balancing control circuit 80. It is supplied from low to high.

At this time, since the charging voltage of the second electric double layer capacitor 20 has not yet reached the maximum charging voltage VH2, the second voltage detector 40 keeps the control signal DS2 low and I2 switches. It will keep low as it is.

Accordingly, the balancing control circuit 80 turns on the first balancing transistor 50 by switching the output of O1 from low to high, while the balancing control circuit 80 maintains the output of O2 low. The balancing transistor 60 is turned off. Of course, O3 of the balancing control circuit 80 remains High.

Here, when the first balancing transistor 50 is turned on, since the closed circuit is configured through the first balancing transistor 50 and the balancing resistor 70 in the first electric double layer capacitor 10, the first electric double layer capacitor 10 is formed. The discharge current IC1 of the second of the first electric double layer capacitor 10 via the first balancing transistor 50 and the balancing resistor 70 at the first terminal 11 of the first electric double layer capacitor 10. Flow to terminal 12.

At this time, the current IR flowing in the balancing resistor 70 flows toward the second terminal 12 of the first electric double layer capacitor 10 at the left side of the drawing, that is, at the drain of the first balancing transistor 50.

Here, FIG. 3 expresses the direction of IR as positive (+) for flowing from left to right of the figure and negative (-) for flowing from right to left of the figure.

Since the discharge current flows in the first electric double layer capacitor 10, the first electric double layer capacitor 10 is discharged and its charging voltage VC1 is lowered.

When the charging voltage of the first electric double layer capacitor 10 falls and reaches the balancing stop voltage VL1 due to the balancing operation of the first balancing transistor 50 at the time t2, the first voltage detector 30 receives the control signal. Is changed from High to Low so that the I1 of the balancing control circuit 80 is switched to Low, whereby the balancing control circuit 80 turns the output of O1 from High to Low to turn off the first balancing transistor 50. Let's do it. Here, the output of O2 is low, and O3 is high.

As such, when the first balancing transistor 50 is turned off, a closed circuit composed of the first electric double layer capacitor 10, the first balancing transistor 50, and the balancing resistor 70 is opened to open the first electric double layer. Since the discharge current of the capacitor 10 no longer flows, the first electric double layer capacitor 10 is charged by the charging current supplied from the charger, and the charging voltage gradually rises again.

In Fig. 3, the direction of IC1 is expressed as positive when charged and negative when discharged.

When the charging voltage of the second electric double layer capacitor 20 reaches the maximum charging voltage VH2 at the time t3, the second voltage detector 40 switches its control signal from low to high, so that the balancing control circuit 80 Since I2 is supplied from low to high, the balancing control circuit 80 turns the output of O2 from low to high to turn on the second balancing transistor 60.

At this time, since the charging voltage of the first electric double layer capacitor 10 has not yet reached the maximum charging voltage, the first voltage detector 30 maintains the control signal in a low state, and O1 maintains a low state. The first balancing transistor 50 remains turned off.

As such, when the second balancing transistor 60 is turned on, since the closed circuit is configured in the second electric double layer capacitor 20 via the balancing resistor 70 and the second balancing transistor 60, the second electric double layer capacitor ( The discharge current IC2 of the second electric double layer capacitor 20 of the second electric double layer capacitor 20 is passed through the balancing resistor 70 and the second balancing transistor 60 at the first terminal 21 of the second electric double layer capacitor 20. It flows to the second terminal 22.

At this time, the current IR flowing in the balancing resistor 70 flows from the left side to the right side of the drawing, that is, from the first terminal 21 of the second electric double layer capacitor 20 toward the drain of the second balancing transistor 60.

In FIG. 3, the direction of the IR expresses the flow flowing from the left to the right of the figure as positive (+) and from the right to the left of the figure as the negative (−).

Since the discharge current IC2 flows in the second electric double layer capacitor 20, the second electric double layer capacitor 20 is discharged and the charging voltage drops.

When the charging voltage of the second electric double layer capacitor 20 reaches the balancing stop voltage VL2 at the time t4, the second voltage detector 40 switches the control signal from high to low to balance the control circuit ( I2 of 80 is switched from high to low so that the balancing control circuit 80 turns off the output of O2 from high to low, thereby turning off the second balancing transistor 60. Of course, at this time, O1 is Low and O3 is High.

As such, when the second balancing transistor 60 is turned off, a closed circuit including the second electric double layer capacitor 20, the balancing resistor 70, and the second balancing transistor 60 is opened to open the second electric double layer capacitor. Since the discharge current of 20 no longer flows, the second electric double layer capacitor 20 is charged by the charging current supplied from the charger, and the charging voltage gradually rises again.

In Fig. 3, the direction of IC2 is expressed as positive when charged and negative when discharged.

Due to the difficulty in specifying something at the time t5, the charging voltage of the first electric double layer capacitor 10 reaches the maximum charging voltage, and the charging voltage of the second electric double layer capacitor 20 also reaches the maximum charging voltage.

Such a situation may occur due to an unspecified situation that occurs externally or internally, but for example, the charging voltage of the second electric double layer capacitor 20 may be reduced when the first balancing transistor 50 is turned on first to flow a discharge current. It can also occur when the maximum charging voltage is reached.

If the control signals DS1 (DS2) are simultaneously switched from low to high, or DS1 is first maintained high by maintaining the state, DS2 is switched from low to high or DS2 is first switched to high. If DS1 goes from low to high while maintaining the state, both I1 and I2 go from low to high, and O3, which has been kept high until now, goes from high to low.

At this time, during the arbitrarily set time t5 to t6, the balancing control circuit 80 switches the output of O1 to High while maintaining the output of O2 to Low, so that only O1 is high and O2 and O3 are Low. do.

Therefore, even if two control signals, i.e., DS1 and DS2 are both input to High, only the first balancing transistor 50 is turned on during the arbitrarily set time t5 to t6 under the control of the balancing control circuit 80. The two balancing transistors 60 are turned off.

Subsequently, the output of O1 is set to Low, the output of O2 is set to High, and the output of O1 is set to High and the output of O2 is set to Lowh during the arbitrarily set time (t6 to t7). And again during the arbitrarily set time (t8 ~ t9), even if the output of O1 to Low, the output of O2 to High, alternately outputting so that both DS1 and DS2 are input to High, the first balancing transistor 50 ) And the second balancing transistor 60 are alternately turned on and off to repeat the balancing operation as described above.

In addition, the balancing control circuit 80 switches the output of O3 from high to low during the time when both DS1 and DS2 are input high, and the external circuit as the overcharge state signal SIG through the external circuit terminal 3. (Not shown) to allow the external circuit to determine whether to stop the charger (not shown).

This state continues and repeats until two control signals, one or both of DS1 and DS2, or both control signals are switched from high to low.

As described above, when the inputs of I1 and I2 are both high, the balancing control circuit 80 alternately outputs the first balancing transistor 50 and the second balancing transistor 60 at regular intervals and outputs a high internally. The low circuit is sent as an overcharge state signal (SIG) to the external circuit through the external circuit terminal 3 while maintaining the balancing operation while preventing the circuit from being shorted. The result of overcharging is compared with the charging voltage of the entire module to determine the most appropriate charger shutdown and restart time.

4 is a schematic circuit diagram illustrating a balancer of an electric double layer capacitor according to another embodiment of the present invention.

Here, in the balancer 100 of the electric double layer capacitor according to another embodiment of the present invention, the first balancing transistor 150 and the second balancing transistor 160 are not turned on at the same time without first turning on the first balancing transistor 150 and the second. Substantially except that the balancing transistor 160 is circuited together with the first to third logic circuitry 191, 192, 193 and the time signal generator 180 to operate alternately at predetermined time intervals. It is the same as the embodiment of 1, and the differences will be mainly described.

That is, as shown in FIG. 4, the output of the first voltage detector 130 is the first input terminal 191-1 of the first logic circuit 191 and the first input terminal of the second logic circuit 192. 192-1, the output of the second voltage detector 140 is the second input terminal 191-2 of the first logic circuit 191 and the second input terminal of the third logic circuit 193. (193-2).

In addition, the output of the first logic circuit 191 is connected to the input terminal 181 of the time signal generator 180, the first output terminal 182-1 of the time signal generator 180 is connected to the second logic circuit ( 192 is connected to the second input terminal 192-2, and the second output terminal 182-2 of the time signal generator 180 is the first input terminal 193-1 of the third logic circuit 193. The output terminal of the second logic circuit 192 is connected to the gate of the first balancing transistor 150, and the output terminal of the third logic circuit 193 is connected to the gate of the second balancing transistor 160. have.

Here, the reason why the second logic circuit 192 is configured as a NAND circuit is that the first balancing transistor 150 is a P-Channel FET, and the third logic circuit 193 is configured as an AND circuit, and the second balancing transistor 160 is configured as an NAND circuit. ) Is an N-Channel FET.

In addition, when Low is input to the input terminal 181, the time signal generator 180 maintains both of the first and second output terminals 182-1 and 182-2, and optionally sets a time when High is input. The first and second output terminals 182-1 and 182-2 alternately output High at a cycle.

That is, when the input terminal 181 is low, the first and second output terminals 182-1 and 182-2 are both low, and when the input terminal 181 is high, the first output terminal 182-1. Is high, the second output terminal 182-2 is low. On the contrary, if the second output terminal 182-2 is high, the first output terminal 182-1 is low.

When the first voltage detector 130 is high and the second voltage detector 140 is low, the output of the first logic circuit 191 is high, so that the time signal generator 180 operates to meet the arbitrarily set period. The first and second output terminals 182-1 and 182-2 alternately appear high.

However, since High is input from the first voltage detector 130 to the first input terminal 192-1 of the second logic circuit 192, the output of the first output terminal 182-1 is the first balancing transistor. Although the output of the second voltage detector 140 is Low because the output of the second voltage detector 140 is Low, the second input transistor 193-2 of the third logic circuit 193 enters the second balancing transistor ( The output of the second output terminal 182-2 of the time signal generator 180 is not transmitted to the gate of 160.

When the output of the first output terminal 182-1 of the time signal generator 180 is transferred to the gate of the first balancing transistor 150, the subsequent operation is the same as the embodiment shown in FIG. 1.

However, in the embodiment illustrated in FIG. 1, the current flowing through the balancing resistor 70 continuously flows, whereas in the embodiment illustrated in FIG. 4, the current flows in a wave form according to a period arbitrarily set in the time signal generator 180. The point is different.

When the second voltage detector 140 is high and the first voltage detector 130 is low, the output of the first logic circuit 191 is high, so that the time signal generator 180 operates to match the arbitrarily set period. And High alternately appear at the second output terminals 182-1 and 182-2.

However, since the high voltage is input from the second voltage detector 140 to the second input terminal of the third logic circuit 193, the output of the second output terminal 182-2 is the gate of the second balancing transistor 160. However, since the output of the first voltage detector 130 is low, the first input terminal 192-1 of the second logic circuit 192 is low, so that the gate of the first balancing transistor 150 The output of the first output terminal 182-1 is not transmitted.

When the output of the second output terminal 182-2 of the time signal generator 180 is transferred to the gate of the second balancing transistor 160, the subsequent operation is the same as the embodiment shown in FIG. 1.

However, in the embodiment illustrated in FIG. 1, the current flowing through the balancing resistor 70 continuously flows, whereas in the embodiment illustrated in FIG. 4, the current flows in a wave form according to a period arbitrarily set in the time signal generator 180. The point is different.

When the first and second voltage detectors 130 and 140 are simultaneously high, the output of the first logic circuit 191 is high, so that the time signal generator 180 operates to match the arbitrarily set period to the first output terminal 182-. High appears alternately between 1) and the second output terminal 182-2.

In this case, since both of the first input terminal 192-1 of the second logic circuit 192 and the second input terminal 193-1 of the third logic circuit 193 are high, the first voltage detector 130 is configured to be first. Both the gate of the first balancing transistor 150 and the second voltage detector 140 are delivered to the gate of the second balancing transistor 160 but according to a period set arbitrarily in the time signal generator 180. When the first output terminal 182-1 is high, when the second output terminal 182-2 is low and when the second output terminal 182-2 is high, the first output terminal 182-1 is low. Therefore, the first balancing transistor 150 and the second balancing transistor 160 operate alternately so as not to cause a short internally. Of course, the subsequent operation situation is the same as that described in FIG.

Although the present invention has been described in detail with reference to preferred embodiments, it is not intended to limit the present invention only to illustrate the present invention, and various changes and modifications can be made by those skilled in the art without departing from the gist and scope of the present invention. Of course, this is also within the scope of the present invention.

1, 100: balancer of electric double layer capacitor according to the present invention
10, 110: first electric double layer capacitor 11, 111: first terminal
12, 112: second terminal
120, 120: second electric double layer capacitor 21, 121: first terminal
22, 122: second terminal
30, 130: first voltage detector 40, 140: second voltage detector
50, 150: first balancing transistor 60, 160: second balancing transistor
70, 170: balancing resistor 80: balancing control circuit
180: time signal generator
191: first logic circuit
192: second logic circuit 193: third logic circuit
3: external circuit terminal

Claims (12)

A first electric double layer capacitor having a first terminal and a second terminal,
A second electric double layer capacitor connected in series with said first electric double layer capacitor, said second electric double layer capacitor having a first terminal and a second terminal;
A first voltage detector connected in parallel to the first electric double layer capacitor and detecting a charging voltage of the first electric double layer capacitor;
A second voltage detector connected in parallel to the second electric double layer capacitor and detecting a charging voltage of the second electric double layer capacitor;
A balancing control circuit for sensing outputs of the first and second voltage detectors to generate a balancing control signal;
First and second balancing transistors having different polarities in which turn-on / turn-off is controlled according to a control signal of the balancing control circuit;
One end is electrically connected between the first and second balancing transistors having different polarities, and the other end is electrically connected between the first and second electric double layer capacitors so that the first and second electric double layer capacitors are electrically connected. The balancer of an electric double layer capacitor, characterized by consisting of a single balancing resistor to discharge the excess current of. The method of claim 1, wherein
The first and second voltage detectors output Low as the control signal before the charge voltage reaches the set maximum charge voltage, and convert the control signal from Low to High when the charge voltage reaches the maximum charge voltage. ,
Each of the first and second voltage detectors maintains the control signal high until the first and second electric double layer capacitors are discharged and the charging voltage drops to reach a predetermined balancing stop voltage. And when the balancing stop voltage is reached, the respective control signals are switched from high to low to be output. The method of claim 1,
An output of the first voltage detector is connected to a first input terminal of the balancing control circuit, an output of the second voltage detector is connected to a second input terminal of the balancing control circuit,
The first output terminal of the balancing control circuit is connected to the gate of the first balancing transistor via an inverting logic circuit, and the second output terminal of the balancing control circuit is connected to the gate of the second balancing transistor. And a third output terminal of the balancing control circuit is connected to an external circuit terminal. The method of claim 1,
The output of the first voltage detector is connected to the first input terminal of the first logic circuit and the first input terminal of the second logic circuit, and the output of the second voltage detector is connected to the second input terminal of the first logic circuit. Connected to a second input terminal of a third logic circuit,
The output of the first logic circuit is connected to the input terminal of the time signal generator, the first output terminal of the time signal generator is connected to the second input terminal of the second logic circuit, and the second output terminal of the time signal generator is A first input terminal of the third logic circuit, an output terminal of the second logic circuit is connected to a gate of the first balancing transistor, and an output terminal of the third logic circuit is connected to a gate of the second balancing transistor Balancer of electric double layer capacitor, characterized in that connected. The method of claim 3, wherein
When the inputs of the first input terminal and the second input terminal of the balancing control circuit are both High (1), the outputs of the first and second output terminals of the balancing control circuit are set to High (1) at a predetermined time period. Low (0) is alternately output, the output of the third output terminal is a balancer of the electric double layer capacitor, characterized in that Low (0). The method of claim 1,
The one end of the balancing resistor is connected to a drain of the first and second balancing transistors, the other end of the first terminal of the first electric double layer capacitor and the first terminal of the second electric double layer capacitor The balancer of the electric double layer capacitor, characterized in that connected to. The method of claim 4, wherein
And a current flowing through the balancing resistor flows in a wave form according to a period arbitrarily set in the time signal generator. The method of claim 3, wherein
And the second balancing transistor is an N-channel FET or an NPN transistor when the first balancing transistor is a P-channel FET or a PNP transistor, respectively. The method of claim 4, wherein
If the first balancing transistor is the P-Channel FET, the second logic circuit is configured as a NAND circuit. If the second balancing transistor is the N-Channel FET, the third logic circuit is configured as an AND circuit. Balancer of electric double layer capacitor. The method of claim 5, wherein
Wherein the two first and second electric double layer capacitors are connected in series to form a block, and the blocks are again connected in series to form a module. The method of claim 5, wherein
When the output of the first voltage detector is high and the output of the second voltage detector is low, the first balancing transistor is turned on and maintained until the output of the first voltage detector changes to low,
When the output of the second voltage detector is high and the output of the first voltage detector is low, the second balancing transistor is turned on and maintained until the output of the second voltage detector changes to low,
When the output of the first voltage detector is high and the output of the second voltage detector is also high, an operation of alternately turning on the first balancing transistor and the second balancing transistor may be performed by the output of the first voltage detector or the second voltage detector. A balancer for an electric double layer capacitor characterized by holding until either of the outputs goes low. 11. The method of claim 10,
If the output of the first voltage detector is high and the output of the second voltage detector is also high, the output of the third output terminal is turned low so that either the output of the first voltage detector or the output of the second voltage detector is The balancer of the electric double layer capacitor, characterized in that the information can be provided to control the charger in consideration of the number of blocks in the over-charge state in the external circuit by holding until until low.

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