KR101150496B1 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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KR101150496B1
KR101150496B1 KR1020060042953A KR20060042953A KR101150496B1 KR 101150496 B1 KR101150496 B1 KR 101150496B1 KR 1020060042953 A KR1020060042953 A KR 1020060042953A KR 20060042953 A KR20060042953 A KR 20060042953A KR 101150496 B1 KR101150496 B1 KR 101150496B1
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semiconductor device
film
abandoned
pattern
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KR20070109650A (en
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복철규
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에스케이하이닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 하드마스크층을 다층 구조로 형성함으로써 감광막의 높이를 감소시켜 미세 패턴의 선폭을 균일하게 하며, 미세 패턴 측벽에 스페이서를 형성하여 스페이서의 선폭만큼 미세 패턴간 스페이스 영역의 간격을 감소시켜 소자의 특성을 향상시키는 반도체 소자의 수율을 향상시키는 기술을 나타낸다. The present invention relates to a method of manufacturing a semiconductor device, by forming a hard mask layer in a multi-layer structure to reduce the height of the photosensitive film to uniform the line width of the fine pattern, to form a spacer on the sidewall of the fine pattern to form a fine pattern by the line width of the spacer The technique of improving the yield of a semiconductor device which improves the characteristic of a device by reducing the space | interval of an inter space area | region is shown.

Description

반도체 소자의 제조 방법{METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자의 제조 방법을 도시한 단면도들. 1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

도 2a 및 도 2b는 패턴 모양을 도시한 평면도. 2A and 2B are plan views showing pattern shapes.

도 3은 종래 기술에 따른 반도체 소자 제조 방법의 문제점을 도시한 사진.Figure 3 is a photograph showing a problem of the semiconductor device manufacturing method according to the prior art.

도 4a 내지 도 4g는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 단면도들. 4A to 4G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

도 5는 본 발명에 따른 반도체 소자의 제조 방법의 효과를 도시한 사진.5 is a photograph showing the effect of the method of manufacturing a semiconductor device according to the present invention.

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 하드마스크층을 다층 구조로 형성함으로써 감광막의 높이를 감소시켜 미세 패턴의 선폭을 균일하게 하며, 미세 패턴 측벽에 스페이서를 형성하여 스페이서의 선폭만큼 미세 패턴간 스페이스 영역의 간격을 감소시켜 소자의 특성을 향상시키는 반도체 소자의 수율을 향상시키는 기술을 나타낸다. The present invention relates to a method of manufacturing a semiconductor device, by forming a hard mask layer in a multi-layer structure to reduce the height of the photosensitive film to uniform the line width of the fine pattern, to form a spacer on the sidewall of the fine pattern to form a fine pattern by the line width of the spacer The technique of improving the yield of a semiconductor device which improves the characteristic of a device by reducing the space | interval of an inter space area | region is shown.

도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자의 제조 방법을 도시한 단 면도들이다. 1A to 1D are diagrams illustrating a method of manufacturing a semiconductor device according to the prior art.

도 1a를 참조하면, 반도체 기판(10) 상부에 반사방지막(15) 및 감광막(20)을 형성한다. Referring to FIG. 1A, an anti-reflection film 15 and a photoresist film 20 are formed on the semiconductor substrate 10.

도 1b를 참조하면, 마스크를 이용한 노광 공정을 통해 감광막(20)을 노광한다. Referring to FIG. 1B, the photosensitive film 20 is exposed through an exposure process using a mask.

도 1c를 참조하면, 현상 공정을 수행하여 노광 영역(20b)은 제거하고, 비노광 영역만 남도록 하여 감광막 패턴(20a)을 형성한다. Referring to FIG. 1C, the development process is performed to remove the exposure area 20b and to form the photoresist pattern 20a so that only the non-exposure area remains.

도 1d를 참조하면, 감광막 패턴(20a)를 마스크로 반사방지막(15)을 식각하여 감광막 패턴(20a)과 반사방지막 패턴(15a)의 미세 패턴(25)을 형성한다. Referring to FIG. 1D, the antireflection film 15 is etched using the photoresist pattern 20a as a mask to form a fine pattern 25 of the photoresist pattern 20a and the antireflection film pattern 15a.

도 2a와 같은 고립형 패턴은 반도체 소자의 소자분리 공정에서 이용되는 가장 일반적인 패턴으로, 도 2b의 라인/스페이스 패턴은 동일한 방향으로 일정 주기를 가지고 반복되는데 비해 상기 고립형 패턴은 단축 및 장축의 두 방향으로 패턴이 반복되므로 형성이 어려운 문제점이 있다. The isolated pattern as shown in FIG. 2A is the most common pattern used in a device isolation process of a semiconductor device. The line / space pattern of FIG. 2B is repeated with a constant period in the same direction, whereas the isolated pattern has two axes of short axis and long axis. Since the pattern is repeated in the direction there is a problem that is difficult to form.

도 3은 고립형 패턴의 문제점을 도시한 사진으로, 장축 방향의 스페이스 영역이 100nm 이하로 형성되기 어려우며, 장축 방향의 패턴 선폭이 균일하지 않게 형성된다. 3 is a photograph showing a problem of the isolated pattern, in which the space region in the long axis direction is less than 100 nm, and the pattern line width in the long axis direction is not uniform.

상술한 종래 기술에 따른 반도체 소자의 제조 방법에서, 고립형 패턴과 같은 2차원 패턴을 형성하는 경우 해상도 부족으로 인하여 미세 패턴 간 스페이스 영역의 간격을 좁히는데 한계가 있으며, 미세 패턴의 선폭이 균일하지 않게 형성되는 문제점이 있다.In the above-described method of manufacturing a semiconductor device according to the related art, when forming a two-dimensional pattern such as an isolated pattern, there is a limit in narrowing the space area between fine patterns due to lack of resolution, and the line width of the fine pattern is not uniform. There is a problem that is not formed.

상기 문제점을 해결하기 위하여, 하드마스크층을 다층 구조로 형성함으로써 감광막의 높이를 감소시켜 미세 패턴의 선폭을 균일하게 하며, 미세 패턴 측벽에 스페이서를 형성하여 스페이서의 선폭만큼 미세 패턴 간 스페이스 영역의 간격을 감소시켜 소자의 특성을 향상시키는 반도체 소자의 제조 방법을 제공하는 것을 목적으로 한다. In order to solve the above problems, by forming a hard mask layer in a multi-layer structure, the height of the photoresist film is reduced to uniform the line width of the fine pattern, and spacers are formed on the sidewalls of the fine pattern to form a spacer on the space between the fine patterns by the line width of the spacer. It is an object of the present invention to provide a method for manufacturing a semiconductor device which reduces the characteristics and improves the characteristics of the device.

본 발명에 따른 반도체 소자의 제조 방법은Method for manufacturing a semiconductor device according to the present invention

반도체 기판 상부에 하드마스크층, 반사방지막 및 감광막을 형성하는 단계와,Forming a hard mask layer, an antireflection film, and a photoresist film on the semiconductor substrate;

상기 감광막에 대해 노광 및 현상 공정을 수행하여 감광막 패턴을 형성하는 단계와,Forming a photoresist pattern by performing exposure and development processes on the photoresist;

상기 감광막 패턴을 마스크로 상기 반사방지막 및 하드마스크층을 식각한 후 상기 감광막 패턴을 제거하여 미세 패턴을 형성하는 단계와,Etching the anti-reflection film and the hard mask layer using the photoresist pattern as a mask and then removing the photoresist pattern to form a fine pattern;

상기 미세 패턴을 측벽에 스페이서를 형성하는 단계Forming spacers on sidewalls of the fine patterns;

를 포함하는 것을 특징으로 한다. Characterized in that it comprises a.

이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다. Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

도 4a 내지 도 4g는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 단면도들이다.4A to 4G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

도 4a를 참조하면, 반도체 기판(100) 상부에 하드마스크층(120), 반사방지 막(130) 및 감광막(140)을 형성한다. Referring to FIG. 4A, a hard mask layer 120, an antireflection film 130, and a photosensitive film 140 are formed on the semiconductor substrate 100.

여기서, 하드마스크층(120)은 비정질 탄소층(110) 및 실리콘 산화질화막(115)의 적층구조 또는 스핀 코팅(Spin Coating) 방식에 의한 폴리머(Polymer)막으로 형성한다. Here, the hard mask layer 120 is formed of a laminated structure of the amorphous carbon layer 110 and the silicon oxynitride film 115 or a polymer film by spin coating.

상기 적층구조는 500 내지 600℃의 온도에서 1500 내지 2500Å의 두께로 비정질 탄소층(110)을 형성하고, 300 내지 500℃의 온도에서 300 내지 500Å의 두께로 실리콘 산화질화막(115)을 형성한다. The laminated structure forms an amorphous carbon layer 110 at a thickness of 1500 to 2500 kPa at a temperature of 500 to 600 ° C, and forms a silicon oxynitride film 115 at a thickness of 300 to 500 kPa at a temperature of 300 to 500 ° C.

또한, 반사방지막(120) 형성 후에 200 내지 220℃의 온도에서 80 내지 100초 동안 베이크 공정을 수행하며, KrF용 감광막을 0.1 내지 0.3um의 두께로 형성한 후 100 내지 120℃의 온도에서 80 내지 100초 동안 소프트 베이크 공정을 수행한다. Further, after the anti-reflection film 120 is formed, a baking process is performed at a temperature of 200 to 220 ° C. for 80 to 100 seconds, and a KrF photosensitive film is formed to a thickness of 0.1 to 0.3 μm, and then 80 to 80 at a temperature of 100 to 120 ° C. Run the soft bake process for 100 seconds.

도 4b를 참조하면, 마스크를 이용하여 248nm의 파장을 갖는 KrF 레이저로 노광 공정을 수행한다. Referring to FIG. 4B, an exposure process is performed with a KrF laser having a wavelength of 248 nm using a mask.

이때, 노광 공정은 NA(Numerical Aperture)가 0.8이고, DOE(Diffractive Optical Element)는 다이폴 어퍼쳐를 사용한다. In this case, the exposure process has a NA (Numerical Aperture) of 0.8 and the DOE (Diffractive Optical Element) uses a dipole aperture.

도 4c를 참조하면, TMAH 2.38% 수용액을 사용한 퍼들(Puddle) 방식으로 30초간 현상 공정을 수행하여 노광 지역(140b)은 용해되고, 비노광 지역만 감광막 패턴(140a)으로 남게된다. Referring to FIG. 4C, the exposure area 140b is dissolved by a development process for 30 seconds using a Puddle method using a TMAH 2.38% aqueous solution, and only the non-exposure area remains as the photoresist pattern 140a.

도 4d를 참조하면, 감광막 패턴(140a)을 마스크로 반사방지막(130) 및 실리콘 산화질화막(115)을 식각하여 반사방지막 패턴(130a) 및 실리콘 산화질화막 패턴(115a)을 형성한다. Referring to FIG. 4D, the anti-reflection film 130 and the silicon oxynitride film 115 are etched using the photoresist pattern 140a as a mask to form the anti-reflection film pattern 130a and the silicon oxynitride film pattern 115a.

이때, 상기 식각 공정은 70 내지 90mT 압력, 250 내지 350W 파워의 챔버에서 45 내지 55 sccm의 CF4, 25 내지 35 sccm의 CHF3, 3 내지 7sccm의 O2의 혼합가스를 사용하여 20 내지 40초간 수행한다. At this time, the etching process using a mixture gas of 45 to 55 sccm CF 4 , 25 to 35 sccm CHF 3 , 3 to 7 sccm O 2 in a chamber of 70 to 90mT pressure, 250 to 350W power for 20 to 40 seconds To perform.

도 4e를 참조하면, 감광막 패턴(140a)를 제거하고, 실리콘 산화질화막 패턴(115a)를 마스크로 비정질 탄소층(110)을 식각하여 실리콘 산화질화막 패턴(115a)및 비정질 탄소층 패턴(110a)의 적층구조인 미세 패턴(120a)을 형성한다. Referring to FIG. 4E, the photoresist layer pattern 140a is removed, and the amorphous carbon layer 110 is etched using the silicon oxynitride layer pattern 115a as a mask to form the silicon oxynitride layer pattern 115a and the amorphous carbon layer pattern 110a. A fine pattern 120a having a stacked structure is formed.

여기서, 상기 식각 공정은 10 내지 20mT 압력, 1000 내지 2000W 파워의 챔버에서 35 내지 45 sccm의 N2와 55 내지 65 sccm의 O2의 혼합가스를 사용하여 10 내지 30초간 수행한다. Here, the etching process is performed for 10 to 30 seconds using a mixed gas of 35 to 45 sccm N2 and 55 to 65 sccm O 2 in a chamber of 10 to 20 mT pressure, 1000 to 2000W power.

이때, 실리콘 산화질화막 패턴(115a) 상부의 감광막 패턴(140a) 및 반사방지막 패턴(130a)은 비정질 탄소층(110)이 식각됨과 동시에 제거되는 것이 바람직하다. In this case, the photoresist layer pattern 140a and the anti-reflection layer pattern 130a on the silicon oxynitride layer pattern 115a may be removed at the same time as the amorphous carbon layer 110 is etched.

도 4f를 참조하면, 미세 패턴(120a)을 포함하는 반도체 기판(100) 전면에 일정 두께의 스페이서 물질층(160)을 형성한다. Referring to FIG. 4F, a spacer material layer 160 having a predetermined thickness is formed on the entire surface of the semiconductor substrate 100 including the fine pattern 120a.

이때, 스페이서 물질층(160)은 실리콘 산화질화막, 질화막, 산화막 또는 비정질 탄소층으로 형성된다. In this case, the spacer material layer 160 is formed of a silicon oxynitride film, a nitride film, an oxide film, or an amorphous carbon layer.

여기서, 실리콘 산화질화막은 350 내지 450℃의 온도에서 형성하는 것이 바람직하다. Here, it is preferable to form a silicon oxynitride film at the temperature of 350-450 degreeC.

도 4g를 참조하면, 비등방성 식각 공정을 수행하여 스페이서 물질층(160)을 식각하여 미세 패턴(120a) 측벽에 스페이서(165)를 형성한다. Referring to FIG. 4G, the spacer material layer 160 is etched by performing an anisotropic etching process to form spacers 165 on sidewalls of the fine pattern 120a.

여기서, 상기 비등방성 식각 공정은 70 내지 90mT 압력, 250 내지 350W 파워의 챔버에서 40 내지 60sccm의 CF4, 20 내지 40sccm의 CHF3 및 3 내지 7sccm의 02 의 혼합한 가스를 사용하여 수행하는 것이 바람직하다. Here, the anisotropic etching process is performed using a mixed gas of 40 to 60 sccm CF 4 , 20 to 40 sccm CHF 3 and 3 to 7 sccm 0 2 in a chamber of 70 to 90 mT pressure, 250 to 350W power. desirable.

이때, 비등방성 식각 공정의 특성으로 인해 미세 패턴(120a) 상부 및 하부에 존재하는 스페이서 물질층(160)이 식각되는 동안 측벽에 있는 스페이서 물질층(160)은 식각되지 않는다. At this time, the spacer material layer 160 on the sidewall is not etched while the spacer material layer 160 on the upper and lower portions of the fine pattern 120a is etched due to the characteristics of the anisotropic etching process.

따라서, 스페이서(165)의 선폭 만큼 미세 패턴(120a)간 스페이스 영역의 선폭이 감소하게 되어 해상도가 향상되는 효과를 얻을 수 있다.Therefore, the line width of the space area between the fine patterns 120a may be reduced by the line width of the spacer 165, thereby improving the resolution.

도 5를 참조하면, 장축 방향의 미세 패턴 간의 스페이스 영역이 100nm 이하이며, 미세 패턴의 선폭이 일정하게 형성된 것을 알 수 있다. Referring to FIG. 5, it can be seen that the space region between the fine patterns in the long axis direction is 100 nm or less, and the line width of the fine patterns is formed uniformly.

본 발명에 따른 반도체 소자의 제조 방법은 노광장비의 파장이나 렌즈 개구수의 변경없이 미세 패턴간 스페이스 영역의 선폭을 감소시켜 공정 비용을 감소시키며, 비정질 탄소층을 식각 마스크로 사용하여 식각 선택비가 증가되고, 프로세스 윈도우가 향상되며, 반도체 기판 상에 단차가 있는 경우 비정질 탄소층이 단차를 평탄화시켜 감광막의 두께가 균일하게 형성되기 때문에 미세 패턴의 선폭 균일도가 개선되어 소자의 생산 수율이 향상되는 효과가 있다. The method of manufacturing a semiconductor device according to the present invention reduces the process cost by reducing the line width of the space area between fine patterns without changing the wavelength of the exposure equipment or the lens numerical aperture, and increases the etching selectivity by using an amorphous carbon layer as an etching mask. The process window is improved, and when there is a step on the semiconductor substrate, the amorphous carbon layer flattens the step so that the thickness of the photoresist film is uniformly formed, thereby improving the line width uniformity of the fine pattern, thereby improving the production yield of the device. have.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라 면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다. In addition, the preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and modifications are the following patents It should be regarded as belonging to the claims.

Claims (11)

반도체 기판 상부에 하드마스크층, 반사방지막 및 감광막을 형성하는 단계;Forming a hard mask layer, an antireflection film, and a photoresist film on the semiconductor substrate; 상기 감광막에 대해 노광 및 현상 공정을 수행하여 감광막 패턴을 형성하는 단계;Forming a photoresist pattern by performing an exposure and development process on the photoresist; 상기 감광막 패턴을 마스크로 상기 반사방지막 및 하드마스크층을 식각한 후 상기 감광막 패턴을 제거하여 미세 패턴을 형성하는 단계;Etching the anti-reflection film and the hard mask layer using the photoresist pattern as a mask and then removing the photoresist pattern to form a fine pattern; 상기 미세 패턴을 포함하는 상기 반도체 기판 전면에 스페이서 물질층을 형성하는 단계; 및Forming a spacer material layer on an entire surface of the semiconductor substrate including the fine pattern; And 비등방성 식각 공정을 수행하여 상기 스페이서 물질층을 식각하여 미세 패턴 측벽에 스페이서를 형성하는 단계Performing an anisotropic etching process to etch the spacer material layer to form spacers on the sidewalls of the fine patterns 를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.Method of manufacturing a semiconductor device comprising a. 청구항 2은(는) 설정등록료 납부시 포기되었습니다.Claim 2 has been abandoned due to the setting registration fee. 제 1 항에 있어서, The method of claim 1, 상기 하드마스크층은 비정질 탄소층 및 실리콘 산화질화막의 적층구조로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.The hard mask layer is a semiconductor device manufacturing method, characterized in that formed in a laminated structure of an amorphous carbon layer and a silicon oxynitride film. 청구항 3은(는) 설정등록료 납부시 포기되었습니다.Claim 3 was abandoned when the setup registration fee was paid. 제 2 항에 있어서, The method of claim 2, 상기 비정질 탄소층은 500 내지 600℃의 온도에서 1500 내지 2500Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법. The amorphous carbon layer is a semiconductor device manufacturing method, characterized in that formed at a thickness of 1500 to 2500 내지 at a temperature of 500 to 600 ℃. 청구항 4은(는) 설정등록료 납부시 포기되었습니다.Claim 4 was abandoned when the registration fee was paid. 제 2 항에 있어서, The method of claim 2, 상기 실리콘 산화질화막은 300 내지 500℃의 온도에서 300 내지 500Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법. The silicon oxynitride film is a semiconductor device manufacturing method, characterized in that formed at a thickness of 300 to 500 kPa at a temperature of 300 to 500 ℃. 청구항 5은(는) 설정등록료 납부시 포기되었습니다.Claim 5 was abandoned upon payment of a set-up fee. 제 1 항에 있어서, The method of claim 1, 상기 하드마스크층은 스핀 코팅 방식에 의한 폴리머막으로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.The hard mask layer is a semiconductor device manufacturing method, characterized in that formed by a spin coating method polymer film. 청구항 6은(는) 설정등록료 납부시 포기되었습니다.Claim 6 was abandoned when the registration fee was paid. 제 1 항에 있어서, The method of claim 1, 상기 감광막을 형성하는 단계 전에 200 내지 220℃의 온도에서 80 내지 100초 동안 베이크 공정을 수행하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of manufacturing a semiconductor device further comprising the step of performing a baking process for 80 to 100 seconds at a temperature of 200 to 220 ℃ before forming the photosensitive film. 청구항 7은(는) 설정등록료 납부시 포기되었습니다.Claim 7 was abandoned upon payment of a set-up fee. 제 1 항에 있어서, The method of claim 1, 상기 감광막을 형성하는 단계 후 100 내지 120℃의 온도에서 80 내지 100초 동안 소프트 베이크 공정을 수행하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법. And performing a soft bake process at a temperature of 100 to 120 ° C. for 80 to 100 seconds after the forming of the photosensitive film. 청구항 8은(는) 설정등록료 납부시 포기되었습니다.Claim 8 was abandoned when the registration fee was paid. 제 1 항에 있어서, The method of claim 1, 상기 스페이서는 실리콘 산화질화막, 질화막, 산화막 또는 비정질 탄소층으로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법. And the spacer is formed of a silicon oxynitride film, a nitride film, an oxide film, or an amorphous carbon layer. 삭제delete 청구항 10은(는) 설정등록료 납부시 포기되었습니다.Claim 10 has been abandoned due to the setting registration fee. 제 1 항에 있어서,The method of claim 1, 상기 비등방성 식각 공정은 70 내지 90mT 압력, 250 내지 350W 파워의 챔버에서 수행하는 것을 특징으로 하는 반도체 소자의 제조 방법. The anisotropic etching process is a semiconductor device manufacturing method, characterized in that performed in a chamber of 70 to 90mT pressure, 250 to 350W power. 청구항 11은(는) 설정등록료 납부시 포기되었습니다.Claim 11 was abandoned upon payment of a setup registration fee. 제 1 항에 있어서,The method of claim 1, 상기 비등방성 식각 공정은 40 내지 60sccm의 CF4, 20 내지 40sccm의 CHF3 및 3 내지 7sccm의 02 혼합한 가스를 사용하여 수행하는 것을 특징으로 하는 반도체 소자의 제조 방법. The anisotropic etching process is performed using a mixed gas of 40 to 40 sccm CF 4 , 20 to 40 sccm CHF 3 and 3 to 7 sccm 0 2 mixed gas.
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KR100435785B1 (en) * 2001-12-22 2004-06-12 동부전자 주식회사 Fabricating method of metal wire in semiconductor device
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100435785B1 (en) * 2001-12-22 2004-06-12 동부전자 주식회사 Fabricating method of metal wire in semiconductor device
KR20060036733A (en) * 2004-10-26 2006-05-02 주식회사 하이닉스반도체 Method for fabrication of semiconductor device

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