KR101147942B1 - Method and apparatus for code space search in a receiver - Google Patents

Abstract

Described herein are apparatus and methods for implementing code space search of a received signal. Code space search is implemented with a searcher 220 that performs dynamically reconfigurable subtasks at each boundary of the initial integration time. Each particular subtask refers to a programmable construct of a coherent integration hypothesis that is performed during the initial integration time. The searcher stores the result of the coherent integration hypothesis in the first portion of the memory. Search accelerator 250 operates on the initial integration result. The search accelerator may perform coherent integration of various frequency bins of different timing hypotheses, generate energy values of the coherent integration result, and generate non-coherent energy sums. The energy value of the coherent integration and the non-coherent energy sum are stored in the second portion of the memory. Reconfiguring the subtask and the performance of the accelerator operation provide flexibility in search space area.

Code Space Search, Coherent Integral Result, Coherent Accumulation, Hypothesis, Flexibility

Description

METHOD AND APPARATUS FOR CODE SPACE SEARCH IN A RECEIVER}

Cross Reference to Related Application

This application is directed to US Provisional Application No. 60 / 779,172, filed March 2, 2006, entitled "Long Coherent Integration Apparatus and Method for Signal Acquisition," and "Method and Apparatus for Code Space Search." in a Reciever ", filed Jan. 17, 2007, with priority to US Provisional Application No. 60 / 885,523, all of which are assigned to the assignee of the present invention and expressly incorporated herein by reference.

Technical background

This disclosure relates to position location of a wireless communication device. More particularly, this disclosure relates to a reconfiguration system for code space search in a wireless communication device.

Many wireless communications use direct sequence spread spectrum to communicate information. Typically, the codes used to spread the signal are pseudo random codes. Typically, the receiver retrieves the underlying information by associating locally generated codes with spreading codes.

At times, the receiver may use a time offset associated with the code to establish a timing reference that can be used to perform position determination. Determining the position based on the timing established from the pseudo random spread signal is performed in various position determination systems.

For example, a GPS (Global Positioning System) navigation system employs satellites in orbit around the earth. Any GPS user can get accurate navigation information, including three-dimensional position, speed and vision, anywhere on the earth. The GPS system includes 24 satellites arranged in a circular orbit with a radius of 26,600 kilometers in three planes tilted 55 ° to the equator and 120 ° to each other. The eight satellites fall equally within each of the three orbital paths. Position measurement using GPS is based on the measurement of the propagation delay time of a GPS signal broadcast from orbiting satellites to a GPS receiver. Usually, signal reception from four satellites requires accurate positioning in four dimensions (latitude, longitude, altitude, and time). First, the receiver measures each signal propagation delay and calculates the range for each satellite by incrementing each delay with the speed of light. Then, a set of four equations with four unknown integral measurement ranges and known satellite positions are solved to find the position and time. The exact performance of the GPS system is maintained by means of onboard atomic clocks for each satellite and by a ground tracking station that continuously monitors and corrects satellite clocks and orbital parameters.

Each GPS satellite transmits two direct-sequence-coded spread spectrum signals within the L-band. The Ll signal is at a carrier frequency of 1.57542 GHz and the L2 signal is at 1.2276 GHz. The L1 signal includes two phase-shift keyed (PSK) spread spectrum signals modulated in a phase quadrature, which is a P-code signal (strictly P) and C / A-code signal (C / A in the case of coarse / acquisition). The L2 signal includes only the P-code signal. P and C / A codes repeat a pseudo-random sequence (also referred to as a "chip") of bits that are modulated on a carrier. The clock-like nature of these codes is used by this receiver in measuring the time delay. The codes for each satellite are unique and allow the receiver to distinguish which satellite transmits a given code even if they are all on the same carrier frequency. Also modulated for each carrier is a 50 bit / second data stream containing information about system state and satellite orbital parameters required for navigation calculations. P-code signals are encrypted and generally not available to commercial and personal users. C / A signals are available to all users.

Typically, the operations performed at the GPS receiver are the majority of the operations performed at any direct-sequence spread spectrum receiver. The spreading effect of pseudo-random code modulation must be removed from each signal by multiplexing it by copying the time-arranged, locally generated code in a process known as despreading. Since an appropriate time arrangement, or code delay, is not easily known at receiver startup, an appropriate time arrangement, or code delay, should be determined by searching during the initial "acquisition" phase of operation of the GPS receiver. Once determined, the appropriate code time-array is maintained during the "tracking" phase of GPS receiver operation.

Once the received signal is despread, each signal constitutes a 50 bit / second PSK signal at the intermediate carrier frequency. The exact frequency of this signal is uncertain due to the Doppler effect caused by the relative movement between the satellite and the terminal unit, and the local receiver GPS clock reference error. Also, since the Doppler frequency is usually unknown before acquisition, this Doppler frequency must be retrieved during initial signal acquisition. Once the Doppler frequency is properly determined, carrier demodulation proceeds.

After carrier demodulation, the data bit timing is derived by the bit synchronization loop, and finally the data stream is detected. Once the signals from the four satellites are acquired and closed, the required time delay and Doppler measurements are made, and navigation data may be undertaken once a sufficient number of data bits (sufficient to determine the GPS time reference and orbital parameters) are received. have.

One drawback of a GPS system for positioning is that the time required for the initial signal acquisition phase is too long. As mentioned above, before four satellite signals are tracked, the satellite signals must be searched in a two-dimensional search "space" whose area is code-phase delay, and Doppler frequency shift. Typically, the Doppler frequency (about 15) is obtained and tracked if there is no prior knowledge of the location of the signal within this search space as in the case of receiver "cold start", after a number of code delays (about 2000). Should be searched for satellites. Therefore, up to 30,000 positions in the search space must be tested for each signal. Typically, without prior information about the signal location in this search space, a number of (about 2000) code delays and (about 15) Doppler frequencies are obtained, as in the case after the cold start of the receiver. And for each satellite to be tracked. Typically, these locations are tested sequentially, in a process that can take 5 to 10 minutes. If the identity of the four satellites (ie, PN-code) is unknown within the field of view of the receiving antenna, the acquisition time is longer.

In the case where the GPS receiver has already acquired satellite signals and in the following tracking mode, the positioning process is substantially simultaneous. However, in using the routine of the wireless terminal, the user turns on the power and starts operation quickly. This may be the case when emergency communication is intended. In this situation, the time delay associated with the GPS satellite signal acquisition cold-start by the GPS / wireless terminal unit before the fixed position can be obtained limits the response time of the system.

Accordingly, there is a need for a system and method description that reduces the time required to acquire a GPS satellite signal and provide a fixed position in a GPS / wireless terminal unit.

summary

Described herein is an apparatus and method for implementing code space search of a received signal. Code space search is implemented as a searcher that performs dynamically reconfigurable subtasks at each boundary of the initial integration time. Each particular subtask refers to a programmable construct of a coherent integration hypothesis that is performed during the initial integration time. The searcher stores the result of the coherent integration hypothesis in a first portion of the memory. The search accelerator operates the initial integration result. The search accelerator can perform coherent integration of various frequency bins of different timing hypotheses, generate energy values of the coherent integration result, and generate non-coherent energy sums. The energy value of the coherent integration and the non-coherent energy sum are stored in the second portion of the memory. The ability to reconfigure subtasks and operate accelerators provides flexibility in search space area.

Aspects of the present invention include an apparatus for code space search. The apparatus includes a memory, a searcher configured to perform a plurality of programmable tasks and generate a plurality of coherent integration results obtained during an initial integration time for each programmable task, one or more coherent integrations determined by a selectable search mode. An accelerator configured to determine at least one coherent accumulation of an integral result of the searcher based on the length and frequency offset, and data configured to transfer the integral result from the searcher to the memory and to transmit the integral result from the memory to the accelerator. Include a mover.

Aspects of the present invention include an apparatus for code space search. The apparatus is a memory having a portion allocated for code space searching, the portion including the memory relying on an active programmable search mode, and an integrated circuit coupled to the memory. The integrated circuit may be configured to generate a plurality of coherent integration results determined during an initial integration period for each of the plurality of programmable search tasks, the coherent through a coherent integration length and frequency hypothesis determined by an active programmable search mode. An accelerator configured to determine a coherent accumulation of integration result values, and a data mover configured to perform DMA data transfer between the searcher and the memory and between the accelerator and the memory.

Aspects of the present invention include a method of code space search. The method includes capturing a complex sample of a received wireless signal, configuring a plurality of code space search tasks, and generating each of the code space search tasks to generate a plurality of coherent integration result values obtained during the initial integration time. Executing and determining a coherent accumulation of a plurality of coherent integration result values, wherein the accumulation length and frequency offset are associated with the coherent accumulation based on a programmable code space search mode. Steps.

Aspects of the present invention include a code space search method. The method includes capturing a complex sample of a received wireless signal, executing each of the plurality of code space search tasks to generate a plurality of coherent accumulation results corresponding to the plurality of code space hypotheses, the plurality of cohes Storing the runt integration result in a memory; Retrieving a plurality of coherent integration result values corresponding to the integration length from memory, and determining a coherent accumulation of the plurality of coherent integration result values.

Brief description of the drawings

The nature, nature, and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the drawings, in which like reference characters designate the same objects.

1 is a simplified block diagram of an embodiment of a wireless communication system that supports location determination.

2 is a simplified functional block diagram of an embodiment of a positioning signal for processing a system implementing code space search.

3 is a simplified functional block diagram illustrating an embodiment of a data flow at a receiver implementing code space search.

4 is a flowchart of an embodiment of a code space search method.

5 is a simplified functional block diagram of an embodiment of a position determination signal processing system implementing code space search.

details

DETAILED DESCRIPTION Herein are described dynamically reconfigurable code space retrieval systems and methods for acquiring and tracking signals in a wireless communication environment. The reconfigurable system includes a sample memory configured to store samples via one or more search increments.

The reconfigurable searcher accesses the stored samples for code space search and coherent integration. The reconfigurable searcher includes multiple correlators that can be dynamically configured to support any one of a predetermined number of channels. The configuration of the searcher and the assignment of correlators to channels can be updated every searcher increment.

The accelerator can generate a correlation result for each of the corresponding channel assignments, and the retriever can write the result to storage. The size of the storage can be dynamically reallocated based on the desired coherent integration time.

The data mover accesses the storage device and sends the retriever results to the sample buffer. The sample server may be configured as a double buffer having a first sample buffer unit and a second sample buffer unit. The data mover alternately writes to either the first or second buffer section, allowing simultaneous reading of the unrecorded buffer section. The size of the first and second sample buffer portions can be dynamically configured to correspond to an initial integration time, which can be a coherent integration time.

The accelerator accesses the correlation result from the sample buffer and alternately accesses the first and second sample portions in a manner complementary to the timing of writing to the sample buffer. The accelerator can determine the coherent accumulation of the searcher results for an initial integration time that can be dynamically adjusted. The length of the initial integration time may extend beyond the time of modulating the data. For example, by tracking edge transitions and received data, the initial integration time can be extended beyond 20 millisecond data modulation periods. The accelerator may selectively transform the correlation result based on the position of the edge transition and the value of the underlying data.

The accelerator may generate energy or magnitude for each of the coherent accumulation results. The accelerator writes the energy result to the energy buffer. In addition, the energy buffer may be configured as a double buffer having first and second energy buffer portions. The accelerator can write to the first portion of the energy buffer and simultaneously read from the second portion of the energy buffer.

The data mover may also be configured to read and write to the energy buffer. The data mover can read the energy result from the energy buffer and write it to storage, and read the previous energy result from the storage into the energy buffer.

The accelerator can determine the non-coherent integration by summing multiple energy results. The result is buffered in an energy buffer, and the data mover can store non-coherent sums in storage.

1 is a simplified block diagram of an embodiment of a wireless communication system 100 that supports location determination.

The wireless communication system 100 may include one or more terrestrial elements that may be in communication with the user terminal 110. For example, user terminal 110 may be a wireless telephone configured to operate in accordance with one or more communication standards. One or more communication standards may include, for example, GSM, WCDMA, and CDMA2000. The user terminal 110 can be a portable unit, a mobile unit, or a stationary unit. User terminal 110 may also be referred to as a mobile unit, mobile terminal, mobile station, user equipment, portable device, telephone, or the like.

Typically, user terminal 110 communicates with one or more base stations 120a, 120b, shown herein as a split cellular tower. Typically, user terminal 110 communicates with 120b, which provides the strongest signal strength at a base station, for example, a receiver within user terminal 110. 1, two base stations 120a, 120b, and one user terminal 110 are shown for convenience and clarity. Typically, a system may have multiple base stations and support one or more user terminals.

The user terminal 110 may determine its location in part based on the positioning signal received from one or more signal sources. The signal source may include one or more satellites 130, which may be part of a satellite based positioning system such as GPS. In addition, the signal source may include one or more base stations 120a or 120b.

User terminal 110 may determine its location in part by determining a pseudo range for each positioning signal source. Each positioning signal source transmits a spreading positioning signal using a pseudo noise code, and the user terminal correlates the received signal with the locally generated pseudo noise code to determine the phase of the received pseudo noise signal. Partial decision can be made. User terminal 110 may determine a pseudo range that correlates time or distance to each other based on the phase of the partially received pseudo noise signal.

Each of the base stations 120a and 120b may be coupled to a base station controller (BSC) 150 that routes communications signals to and from the appropriate base stations 120a and 120b. The BSC 140 may be coupled to a Mobile Switching Center (MSC) 150, which may be configured to operate as an interface between the user terminal 110 and the Public Switched Telephone Network (PSTN) 170. Therefore, MSC 150 is also coupled to PSTN 170. In addition, MSC 150 may be configured to coordinate inter-system handoff with other communication systems.

In addition, a Position Location Center (PLC) 160 may be coupled to the BSC 140. For example, PLC 160 may be configured to store location information such as the location of each of base stations 120a and 120b in location system 100. In one embodiment, PLC 160 may be configured to provide information to user terminal 110 such that user terminal 110 may determine its location based in part on pseudo range in multiplexing signal sources, Here, the pseudo range may be a relative time-of-arrival value. In another embodiment, the PLC 160 may be configured to determine the location of the user terminal 110 based on the pseudo range information provided by the user terminal 110. In the latter embodiment, a network server (not shown) in PLC 160 may perform location determination to offload processing from user terminal 110.

PLC 160 may be configured to instruct base stations 120a and 120b via BSC 140 and generate a positioning signal. In another embodiment, the base stations 120a and 120b may be configured to periodically generate a positioning signal.

User terminal 110 together with PLC 160 may determine its location using any one of several positioning techniques. The user terminal 110 or the PLC 160 can select a technique based in part on the signal source used to generate the pseudo range value. For example, user terminal 110 may use time of arrival (TOA), time difference of arrival (TDOA), advanced forward link trilateration (AFLT), or some other positioning technique. The user terminal 110 or PLC 160 is based on GPS, augments GPS signals with terrestrial based beacons such as hybrid positioning systems, and implements positioning techniques based on pseudo range values derived from terrestrial based beacons. As a result, the position of the user terminal 110 can be determined.

 In order to generate a first fixation, such as power up, a receiver in user terminal 110 configured to process a GPS satellite signal requires all satellite PN-code sequences, all PN-code phase hypotheses, and all Doppler to receive the necessary satellite signals. You need to search across the frequency offset. This averages the search through 24 satellites, a predetermined range of Doppler frequencies, and 1023 code hypotheses (typically, this is implemented with 2046 discrete half-chip code shifts and calculations). After determining the initial fixed position, user terminal 110 may limit the number of frequencies and code phases retrieved to a subset based on the satellite signal used to determine the initial fixed position. User terminal 110 may reduce the number of retrieved discrete satellite PN-code sequences from 24 to typically eight sets of visible satellites, but may only reduce to four.

However, if location fixation is not possible simply by using GPS satellite information, the user terminal 110 may need to retrieve one or more PN-code sequences for one or more terrestrial beacons. Typically, the code sequence used by terrestrial beacons is distinct from the code sequence used by GPS satellites. In addition, the time line and processing of terrestrial waves, which are typically based on positioning signals, are also distinguished from the time line and processing of GPS.

The user terminal 110 can include a reconfigurable receive signal processor. The reconfigurable signal processor can include multiple independently reconfigurable resources and can support multiple integration times. The independently reconfigurable resource may be configured to perform a search of the selected code space portion for a reconfigurable time. The search results can be integrated coherently for a reconfigurable integration time, and the integration results can also be integrated non-coherently.

The implementation of the reconfigurable receive signal processor at the user terminal 110 allows the user terminal 110 to dedicate resources in a manner that is effective for the current processing state. For example, upon initial position fixation, the user terminal 110 may configure a reconfigurable receive signal processor to retrieve through the maximum number of positioning sources to quickly identify the identity of the positioning signal source. For example, the user terminal 110 first searches all of the predetermined maximum number of GPS satellites to identify which GPS satellites have transmitted the received signal. Once user terminal 110 determines the signal of the GPS satellite that is causing the received signal, user terminal 110 may reconfigure the received signal processor to allow more focused processing of the identified satellite signal. For example, user terminal 110 may configure a longer coherent integration time to improve the reception sensitivity as well as the frequency sensitivity.

2 is a simplified functional block diagram of an embodiment of a reconfigurable position determination signal processing system 200 that implements code space search. The signal processing system 200 includes a sample server 210 coupled with the searcher 220. Searcher 220 generates a result that is stored in memory 240. Accelerator 250 accesses searcher results in memory 240 and performs additional signal processing.

Data mover 230 writes the results from retriever 220 to a location in memory 240. Data mover 230 also controls read and write operations between memory 240 and buffer 260 associated with accelerator 250. The buffer 260 can be divided into a sample buffer 262 and an energy buffer 264. Each of the sample buffer 262 and the energy buffer 264 can be configured as a double buffer, where data is written to the first part of the buffer and at the same time other data is read from the second part of the buffer.

Controller 270 operates to configure searcher 220 and accelerator 250. For example, the controller 270 can organize the subtasks performed by the retriever 220. In addition, the controller 270 may configure the length of the coherent integration time or length as well as the non-coherent energy sum performed by the accelerator 250.

In addition, the controller 270 can configure the amount of memory needed to store various correlation values and energy sums. The amount of memory needed to store the correlation result is determined in part based on the length of the coherent integration and the number of non-coherent energy sums. The controller 270 uses the memory resources needed to support the configuration and allows any unused memory to be used for other processes. When reading or writing to the memory 240, the controller 270 can communicate the dynamic memory map with the data mover 230 so that the data mover 130 can access the appropriate memory location.

Typically, sample server 210 is implemented with a memory, such as RAM, that temporarily stores complex samples of a received signal. In another embodiment, sample server 210 is a signal, such as a complex analog to digital converter (ADC), configured to sample the received baseband signal and generate in-phase (I) and quadrature phase (Q) samples. Contains a sampler.

For example, sample server 210 may be configured to store up to 4 milliseconds of complex samples taken at twice the chip rate. Of course, the sample server 210 is not limited to samples captured at twice the chip rate, and the actual sample rate may be some other fraction or multiple chip rates. For example, sample server 210 may be configured to store samples captured at a chip rate, four chip rates, or some other interval. Where signal processing system 200 is configured to process the received GPS signal, the sampling rate may be approximately 2 MHz. The sample server 210 may be synchronized to a real time clock (not shown) so that the millisecond boundaries of the samples stored at the sample server 210 coincide with the GPS millisecond boundaries corresponding to the code period.

The retriever 220 operates on complex samples stored in the sample server 210. The retriever 220 supports 32 independently configurable subtasks, each of which can be reallocated every millisecond. Each subtask retrieves 32 chip windows across up to 64 different hypotheses. Subtasks may be assigned to retrieve the same or different codes corresponding to GPS satellites. Increasing the number of subtasks allocated to search the code space of a particular satellite reduces the average search time. The total number of different hypotheses and the length of each window can be changed by changing the hardware configuration, and the actual number and configuration of subtasks is not limited to the above-described embodiment.

For example, in GPS code phase search, the subtask may be configured to search the 32 chip windows of the sample over up to 64 different hypotheses. The number of hypotheses retrieved can be programmable by the controller 270 and can range from 2 to 64, for example, multiples of two.

Prior to performing the code phase search, the searcher 220 corrects the frequency offset in the received signal. In one embodiment, searcher 220 may implement a rotator to rotate the search sample to a desired center frequency. The amount of frequency offset complemented by the rotator may be determined based in part on a frequency correction loop that may be implemented with a frequency search performed by the signal processing system 200.

The retriever 220 may optionally perform interpolation of the oversampled receive chip sequence. The interpolation process can also be referred to as resampling the input signal prior to correlation. In one embodiment, the received signal is sampled at twice the code sequence chip rate (chip x2). The sampler corrects two consecutive samples and introduces a variable delay. Typically, the variable delay is less than one half of the chip period, and can be, for example, one quarter chip period or a multiple of the smaller fraction of the chip period. For example, the sampler may introduce a variable delay in multiples of one eighth of the chip period, where the multiples range from zero to three.

The searcher 220 despreads 32 chips each using one hypothesis, where the hypothesis corresponds to a particular phase of the locally generated PN code sequence. Each hypothesis can be arranged, for example, to allow retrieval of 23 code phase offsets at a 1/2 boundary. In other embodiments, each hypothesis can be arranged at chip boundaries, thus allowing retrieval of 64 different code phase offsets. The searcher 220 is configured to store each complex correlation result in the searcher buffer. Data mover 230 may store the buffered search result at a location in memory 240. In one embodiment, the search buffer 224 is configured as a double buffer. The retriever 220 can be configured to update the first portion of the double buffer, where the second portion of the double buffer is accessed by the data mover 230 to move the previous search result value to the memory 240. The double buffer configuration allows the searcher 220 to be computationally limited rather than limited to data transmission. By configuring a double buffer, the transmission of previously calculated results need not be completed prior to the next searcher task, and the data transmission of the previous results may occur concurrently with the processing of the most recent task. Of course, searcher 220 is not limited to using a double buffer configuration, and may use some other memory configuration that allows for simultaneous processing and data transfer. For example, retriever 220 may implement a circular buffer that is large enough to allow all data transfers to occur prior to the next update of a particular memory location.

The configuration of the searcher 220, and in particular the construction of the hypothesis and the number of code spaces retrieved, may be configured in each correlation increment. In the above embodiment, the correlation increment occurs every millisecond.

Retrieval 220 includes a hardware command register that each correlation increment can be updated. The controller 270 can write the location and the size of the task queue to a hardware command register. As noted above, the searcher 220 may be controlled to perform up to 32 separate tasks in a single queue.

The retriever 220 is configured to access the queue pointed to by the hardware command register. The retriever 220 may obtain a task queue during processing of the task and determine the start time of the task indicated in the hardware command register based on the valid comparison value.

Accelerator 250 is configured to process correlation results from searcher 220. Accelerator 250 may be configured to operate on data stored in buffer 260 to reduce the number of different data transmissions that need to be initialized. The buffer 260 can include a sample buffer 262 and an energy grid buffer 264. Each of sample buffer 262 and energy grid buffer 264 may be arranged in a double buffer to eliminate any possible memory contention issues related to reading and writing locations in memory 240.

Each of the dual buffers may comprise a first and a second portion or bank of memories. At any given time, one bank of buffers is coupled to the integrator engine of the accelerator 250, and the other bank of buffers is coupled or otherwise accessible to the data mover 280. The association (integration) of the bank with the integration engine or data mover 280 is swapped after each processing interval.

Accelerator 250 includes an integration engine that includes a plurality of parallel accumulators configured to generate coherent integration sums over a configurable integration time and multiple frequencies. Although accelerator 250 may be controlled to support substantially (virtually) any coherent integration length, accelerator 250 may be adjusted to support a discrete set of integration lengths. In one embodiment, accelerator 250 may be configured to generate a coherent integration sum, also referred to as a coherent accumulation for an integration time of 10, 20, 39, 80, or 160 milliseconds. Since searcher 220 generates a coherent integration result for one millisecond period, the coherent accumulation time in milliseconds corresponds to the coherent integration length. Accelerator 250 may be configured to track bit edges and bit values to adjust the integral length extended beyond one or more bit edges.

The number of parallel accumulation paths depends on the level of complexity acceptable within the accelerator 250. In one embodiment, accelerator 250 may include six parallel multiplayer-accumulator paths that may sum up a set of samples over six different frequencies, for example. The operation of the parallel accumulation path can be repeated to support many frequencies and many sample sets. Accelerator buffer 262 may be sufficient to integrate for 20 milliseconds for all hypotheses of one task. Similarly, energy buffer 264 may be large enough to support 20 frequencies during each of the 64 offsets. Integration longer than 20 milliseconds can be performed by processing a subset of the total offset number in a single operation. When performing 20 * N millisecond integration, N accelerator operations are used. Each operation processes 63 / N time hypotheses. Each energy memory maintains 20 * N milliseconds for each of the 64 / N time offsets. The resulting memory bandwidth and accelerator processing rates required to support different integration lengths are the same. For example, accelerator 250 may be configured to simultaneously support 20 millisecond accumulate time through 64 different time hypotheses in a single operation, or 160 millisecond accumulate through 8 different time hypotheses in the same single operation. It can be configured to support time. Accelerator 250 performs eight separate operations to retrieve the same 64 frequency hypotheses. In this way, the data bandwidth used by the accelerator is constant regardless of the integration time.

Typically, the magnitude of the frequency range spanned by the accelerator 250 is 500 hertz, extending fully to approximately 250 hertz below the nominal frequency and 250 hertz above the nominal frequency. The number of frequency hypotheses analyzed simultaneously by the accelerator 250 varies depending on the coherent integration length. In one embodiment, the number of frequency hypotheses processed simultaneously is set equal to the coherent integration length. Accelerator 250 spacing different frequency bins approximately uniformly throughout the frequency span.

Accelerator 250 determines the coherent integration at a particular frequency offset by rotating the input sample by the desired frequency offset and summing over the coherent integration length. The accelerator 250 can then calculate the coherent energy sum to locate the two-dimensional energy grid. The two-dimensional energy grid may include energy for the current coherent integration length for each time hypothesis and each frequency offset.

Accelerator 250 may be configured to determine a coherent sum for all frequencies of a particular time hypothesis before determining the coherent sum of other time hypotheses. Performing coherent sums in this way can minimize the number of times memory is accessed. Of course, in other embodiments, the application of frequency offset may be a more intensive processor, and the coherent sum of each frequency offset may be completed before determining the coherent sum for other frequency offsets throughout the hypothesis. Other embodiments may determine the sum in some other order.

Data mover 230 operates as a DMA engine to transfer information between searcher 220 and memory 240 and memory 240 and accelerator 250. Data mover 230 performs a memory transfer to a location depending at least in part on the retrieval mode and the associated integration length. Data mover 230 may determine the memory map based on the task queue from controller 270.

Data mover 230 copies the coherent sum generated by searcher 220 for each of the scheduled subtasks. In an embodiment where the searcher 220 double buffers the coherent sum, the data mover 230 operates to send a block from a buffer that is not being written by the searcher 220. Data mover 230 is configured to operate on data in a block of a buffer that is not associated with a current subtask operation.

Similarly, data mover 230 records previously determined searcher output and energy sums previously determined from memory 240 associated with buffer 262 in accelerator 250, in particular memory transfer, and recorded by accelerator 250. To a buffer block that does not exist. Data mover 230 also copies the most recent energy sum from the accelerator buffer to memory 240.

The controller 270 generates association control information recorded in the task queue and the hardware command register of the searcher 220. Controller 270 can substantially configure any search and integration length that can be supported by the space available in memory 240. However, controller 270 typically has a predetermined number of search configurations or modes that can be selected and programmed at each control boundary. For example, controller 270 may have a high search mode spanning 1600 Hz, 20 different frequency bins, 64 hypotheses, and a coherent length of 20, a first low search mode spanning 400 Hz, 80 different frequency bins, 16 Hypothesis, and 80 in coherent length, second low search mode spanning 200 Hz, 160 different frequency bins, eight hypotheses, and 160 in coherent length, inferior acquired search mode spanning 1600 Hz, 20 different frequency bins, 64 One can choose a hypothesis, and a 10 in coherent length, and a bit edge search mode spanning 1600 Hz, eight different frequency bins, eight hypotheses, and a 20 in coherent length.

3 is a simplified functional block diagram illustrating an embodiment of a data flow at a receiver that implements a positioning signal processing system 200 for code space search. System 200 is described in the context of GPS space search processing. However, similar code space searches may be processed for some other PN code spreading information, such as AFLT.

Sample server 210 receives complex input samples at approximately twice the chip rate and writes the samples to a memory such as RAM. Sample server 210 may be configured to arrange RAM, such as a circular buffer, and overwrite the oldest entry with the most recent sample.

Finder 220 examines the contents of the hardware command register to determine the location and size of the task queue. The hardware command register in searcher 220 may be programmed during processing of the task queue pointed to by the previous hardware command register content. The retriever 220 may determine a start time for a nested scheduled search task and start a new search task as soon as the current search task is finished.

Each task queue may control a predetermined maximum number of subtasks that may be processed in an initial search period, which may be one millisecond. The retriever 220 processes the subtasks and writes the coherent sums for each hypothesis to a buffer in the retriever 220. The retriever buffer can be organized as a double buffer. Two blocks of the retriever double buffer may alternately be associated with one retriever 220 or data mover 230. The block associated with the searcher 220 receives the correlation result generated by the searcher 220, while the block associated with the data mover 230 allows block data transfer from the searcher 220 to the memory 240. . Associations of blocks in the retriever double buffer are swapped at a predetermined time. For example, the association of a block can be swapped as soon as the retriever 220 fills the associated block.

Data mover 230 performs data transfer 310 between associated retriever 220 buffer and memory 240. The data mover 230 does not need to synchronize the data transfer 310 with the coherent integration processing performed at the retriever 220. Instead, data mover 230 may be configured to perform data transfer 310 at any time while the buffer block association is valid. Data mover 230 determines a location within memory 240 and records its value based at least in part on an active search mode initiated by a controller (not shown). The size of the memory 240 allocated to the system 200 can be dynamic, for example, changing based on the active code retrieval mode. As an example, the bit edge search mode spanning 1600 Hz, eight different frequency bins, eight hypotheses, and a coherent length of 20 are low search mode spanning 200 Hz, 160 different frequency bins, eight hypotheses, and 160 incohi It requires less storage space memory 240 than the runt length.

If memory 240 is shared with a process that differs from code space retrieval, such as when memory 240 is a system memory of a wireless communication device, dynamic allocation of memory space maximizes the amount of available memory space to distinguish it from code retrieval. Supported tasks. System 200 only needs to be allocated with enough memory 240 space to support the active code retrieval mode.

In addition, the data mover 230 may control the data transfer 320 of the search result value stored in the memory to the double buffered sample buffer 262. Since accelerator 250 consumes search result values during coherent integration, data transfer 320 from memory 240 to sample buffer 262 may be unidirectional.

The double buffered sample buffer 262 may replace the association of the first and second blocks between the data mover 230 and the accelerator 250. Accelerator 250 controls read operation 340 from its associated sample buffer 262 block. Once accelerator 250 accesses all of the data in its associated sample buffer 262 block, data mover 230 and accelerator 250 can swap the sample buffer 262 block association.

Accelerator 250 determines the coherent sum of the searcher results via the coherent accumulation length determined based on the search mode programmed by the controller. Accelerator 250 may generate an energy value for each coherent integration by summing the squares of the complex components of the coherent integration result.

Accelerator 250 may write an energy value to energy buffer 264 for transmission to memory 240. Alternatively, accelerator 250 may be configured to generate a non-coherent accumulation of energy values by summing up previous energy values and current energy values calculated for the same energy grid location.

Accelerator 250 controls data transfer 350 of energy values to / from the associated block of double buffered energy buffer 264. The energy buffer 264 may be configured as a double buffer with blocks alternatively associated with either the data mover 230 or the accelerator 250.

Data mover 230 controls data transfer 330 of energy values between memory 240 and associated blocks of energy buffer 264. Similarly, accelerator 250 controls energy buffer read and write operations 350 between its associated blocks of energy buffer 350. Associated blocks of energy buffer 264 may be swapped based on a schedule determined by the active search mode.

Data mover 230 may access the previously stored energy result from memory 240 and copy the value to the associated block of energy buffer 264 in data transfer operation 330. After block associative swap, accelerator 250 may access the energy value previously sent by data mover 230 and, for example, determine the non-coherent accumulation using the current energy value. Accelerator 250 controls write operation 350 with that block of energy buffer 264. When a block of energy buffer 264 is swapped again, data mover 230 may perform data transfer 330 of the updated energy value from energy buffer 264 to memory 240. Accelerator 250 processing may be performed in a pipelined fashion to process data more effectively. For example, the pipeline process may be a pipeline of three different operations. The pipeline transfers input data for one operation, processes coherent accumulation and energy values for a second operation, and transfers data of previous results from accelerator 250 to memory 240 for a third operation. Can support Thus, while accelerator 250 performs on the search result value for the previous data transfer (operation N), data mover 230 may transmit the search result value from memory to the sample buffer (operation N + 1). In addition, the data mover 230 accumulates from the energy buffer into the memory 240 for a third different operation prior to loading the energy buffer from the external memory 240 to a previously stored value (operation N + 1). The energy sum can be transferred (operation N-1).

4 is a flowchart of an embodiment of a method 400 of code space search. The method 400 may be implemented by the position determination signal processing system of FIG. 2 and may be implemented within the user terminal of FIG. 1. Method 400 represents a process that extends through functional blocks. The operational sequence in method 400 represents the processing of a set of samples throughout the system. Multiple operations may occur simultaneously in the system to continue operation of the method without reconfiguration or latency for data transmission.

The method 400 begins at block 402, where the system captures a complex sample of the received signal to be retrieved. For example, the signal sampler may sample the received GPS signal at a rate that is approximately twice the PN code rate. The complex sample may be stored in RAM, or some other storage device.

The system proceeds to block 410, where the searcher is configured to support a particular code search processing mode. The searcher may determine the processing mode for future samples while processing the samples according to the current processing mode. For example, the browser can read the hardware command registers to determine the location and size of the task queue. The retriever may perform tasks in the task queue at the task boundary or when processing of the current task is complete. The task queue may include a plurality of tasks with a predetermined maximum number of tasks. For example, the task queue may include up to 32 tasks for the retriever to be performed in each initial integration period, which may be 1 millisecond.

Each search task may support search through a predetermined number of code chips through multiple hypotheses. The number of retrieved hypotheses can be programmed and can range from a predetermined maximum number of hypotheses. For example, each task may be configured to search a window containing 32 code chips, and may be configured to search up to 64 different hypotheses through the search window, where each code space hypothesis is the most It can be offset from the hypothesis by one half of the chip period.

The system proceeds to block 412 and sends a sample associated with the retriever configuration from the sample memory to the retriever. Using the sample provided above, the searcher may be configured to search the entire code space of a single satellite vehicle in one initial integration period of 1 millisecond. Typically, however, the searcher is configured to retrieve the received code through a portion of the multiple codes.

After sending the relevant sample, the system proceeds to block 414 and executes the previously set task in the task queue. Each task results in coherent integration of the sample during an initial integration period of one millisecond through each of the hypotheses applied by the task, although other embodiments may use other initial integration periods.

The searcher proceeds to block 416 and writes the coherent integration results from each hypothesis into the associated block of the double buffer. The double buffer includes two blocks that are alternately associated with either a searcher or a data mover. The retriever writes to the associated buffer block to allow the data mover to transfer data from the associated buffer block. By double buffering the searcher output, both the searcher and the data mover avoid memory contention in accessing data from the buffer. Previously buffered results can be read from one part of the double buffer, and the retriever runs the sample and writes to another part of the double buffer. The double buffer allows for more flexible data transfer, so the transfer of previous searcher results does not have to be completed before starting the next searcher operation. Also, if the DMA memory transfer by the data mover can be completed in less than the time used to locate the retriever result, the result transfer to the memory is more flexibly scheduled.

Since the transfer of the result only occurs from a block of retriever buffers associated with the data mover, the system proceeds to block 418 and swaps the association of blocks of the double buffer. Swapping an associative block makes the block of buffer available for storage of the current integral result while allowing the most recent result to be transferred to memory.

After swapping the block association of the retriever double buffer, the system proceeds to block 420 where the data mover sends the initial coherent integral result from the searcher to memory. In one embodiment, the memory is shared with other processes and the data mover performs a DMA transfer of the searcher buffer to a location in the shared memory.

After transferring the retriever result to memory, the system proceeds to block 430. At block 430, the data mover sends at least a portion of the retriever results from the memory to an associated block of sample buffers for processing by the accelerator. In addition, the sample buffer consists of a double buffer, with each block of the sample buffer associated with either a data mover or an accelerator. The sample buffer block association is swapped after a predetermined event, which may be the filling, timing, or some other event of the buffer.

The system proceeds to block 432 and sends at least a portion of the previous energy accumulation value from the memory to the associated block of the energy buffer for access by the accelerator. The system may also move the updated result from the energy buffer to the memory prior to transferring the energy accumulation value to be updated from the memory to the energy buffer. The energy buffer also consists of a double buffer. One block of the double buffer is associated with the data mover, and the other block of the double buffer is associated with the accelerator. The energy buffer association may be swapped after a predetermined event that may be distinguished from an event that initiates swap of the sample buffer block.

The accelerator accesses only blocks of associated sample buffers and energy buffers. Thus, the system proceeds to block 434 where the accelerator can access the most recent value sent from memory by the data mover by swapping the association of the sample buffer and the energy buffer. The data mover can also access the most recent energy result from the accelerator. The accelerator consumes searcher results and does not rewrite the results to the searcher buffer. Hence, swapping of the searcher buffer block makes it possible to transfer additional space for the data mover to the sample buffer.

After swapping the buffer associations, the system proceeds to block 450 and determines a coherent accumulation value for search results accessible in the associated sample buffer. The accelerator determines the coherent accumulation value based on the active code search mode. The accelerator may need to wait for multiple swaps of the sample buffer to support the desired integration length, depending on the size of the sample buffer.

If the integral length crosses a data boundary, such as the 20 millisecond data boundary used in the GPS signal, the accelerator can track the occurrence of the bit boundary and compensate the bit value in calculating the accumulated value.

The accelerator can also determine the coherent accumulation value via multiple frequency bins based on the active search mode. The accelerator may include multiple parallel paths, and the accumulated value across multiple frequencies or multiple searcher results may coexist.

The system proceeds to block 452 and determines the energy associated with each coherent accumulation. The accelerator can determine the energy associated with the complex accumulated value, for example, by summing the squared and orthogonal values of the in-phase. In some embodiments. The accelerator may omit determining the accumulated energy or instead store the complex accumulated value in an energy buffer. In embodiments in which the accelerator stores the coherent accumulation sum rather than the energy value in the buffer, the operation at blocks 452-454 may be omitted. The accelerator can also update the energy buffer directly with coherent accumulation values.

The system proceeds to block 454 to determine any non-coherent energy accumulation values that may be specified by the code search mode. To determine the non-coherent accumulation, the accelerator reads the previous energy value from the desired portion of the energy grid stored in the energy buffer and sums the corresponding energy values. In some embodiments, the accelerator may determine the weighted sum and scale the previously accumulated energy sum with a predetermined fraction before summing the most recent energy values.

The system proceeds to block 456, where the accelerator writes the accumulated energy value to the energy buffer. Typically, the system cannot directly access a block of energy buffers associated with the accelerator. Thus, the system proceeds to block 458 waiting for the next occurrence of an energy block associative swap.

At block 460, the data mover has access to the most recent energy value updated by the accelerator. The data mover performs a DAM transfer of the updated energy accumulation value to the memory. The data mover also loads any energy value from the memory into the energy buffer to support the next non-coherent accumulation.

After block 460, processing of the particular received sample is completed in one entire processing path from sampling to energy accumulation. Double buffering and memory storage of various intermediate values allow the entire process to run substantially continuously. Since the searcher may be reconfigured per initial accumulation boundary, the system does not need to stop or otherwise waits for a change in the search configuration, and the searcher runs a previously scheduled task. Double buffering of search results at both the input to the searcher and the accelerator eliminates memory contention while increasing flexibility in accessing the memory and can share external memory for modules or integrated circuits with the searcher and accelerator.

Separating the initial coherent integration from the longer coherent integration that corresponds to the desired integration length allows more flexibility in scheduling and configuration of the system. The one millisecond integration result from the searcher can be used to support substantially any integration length.

5 is a simplified functional block diagram of an embodiment of a position determination signal processing system 500 that implements code space search. The system 500 of FIG. 5 may be implemented, for example, in a user terminal of FIG. 1.

System 500 includes means 510 for capturing a complex sample of a received wireless signal. The means 510 for capturing the complex sample is coupled to the retrieval means 520.

The retrieval means 520 can operate in accordance with each of the code space retrieval tasks indicated by the hardware register 522, which acts as a means for constructing a plurality of code space retrieval tasks. The search means 520 generates a plurality of coherent integration result values obtained during the initial integration time, which can be one millisecond. The search means 520 can be configured to generate a plurality of coherent integration result values corresponding to the plurality of code space hypotheses as defined by the search task.

The control means 570 controls the value recorded in the hardware register 522. The value in hardware register 522 may be pointed to a task queue in memory that is determined based on, for example, a code space search mode. The data transmission means 530 is coupled to the retrieval means 520 and is operative to transmit a plurality of coherent integration result values to the storage means 540. In addition, the data transmission means 530 operates to transmit the plurality of coherent integration result values from the storage means 540 to the buffering means 562 and 564 coupled to the acceleration means in the acceleration means 550. In particular, the data transmission means 530 transmits a plurality of coherent integration result values corresponding to the integration length.

Acceleration means 550 acts as means for determining coherent accumulation of a plurality of coherent integration result values. The integral length and frequency offset associated with the coherent accumulation are based on the programmable code space search mode.

Described herein is a system, apparatus, and method of code space search. The described systems, apparatus, and methods may be implemented in a user terminal to process GPS signals, AFLT signals, or the like, or some other code spreading signal. For example, the code space search process and apparatus is applicable to any code space search of the received spread spectrum signal. Although applications have been described in particular embodiments for GPS signals, the claimed subject matter is not limited to GPS and is typical for code space searches. The searcher is configured to determine the coherent integration result for the initial integration time or period. The searcher results are used as intermediate values for coherent integration and non-coherent energy accumulation performed in the accelerator.

The intermediate value is stored in a double buffer to transfer data to the effective and uncompetitive memory. The use of double buffering allows reconfiguration of low or no latency code search mode.

In addition, the separation of coherent integration processing following the initial integration period allows for flexible reconfiguration of the code space search mode without the need for extra acquisition and analysis of the data. The ability to substantially reconstruct the code space search in real time allows for more efficient code space search and allows reconstruction from fast code acquisition to high sensitivity code space search.

As used herein, the term coupled or connected is used to mean indirect coupling as well as direct coupling or connection. In cases where two or more blocks, modules, devices, or devices are coupled, one or more intervening blocks exist between the two coupled blocks.

Various illustrative logic blocks, modules, and circuits described in connection with the embodiments described herein include general purpose processors, digital signal processors (DSPs), reduced instruction set computer (RISC) processors, and application specific integrated circuits. ), A field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in other ways, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, eg, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other configuration.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be implemented directly in hardware, a software module, or a combination of the two executed by a processor. The various steps or activities in the method or process may be performed in the order shown, or may be performed in another order. In addition, one or more process or method steps may be omitted, or one or more process or method steps may be added to the methods and processes. Additional steps, blocks, or activities may be added to elements that exist at the beginning, end, or in the middle of methods and processes.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (33)

Device for code space searching, Memory; A searcher configured to perform a plurality of programmable tasks and generate a plurality of coherent integration result values obtained during an initial integration time period for each programmable task; An accelerator configured to determine at least one coherent accumulation of an integral result of the searcher based on one or more coherent integration lengths and frequency offsets determined by the selectable search mode; And And a data mover configured to transfer the integral result value from the searcher to the memory, the data mover configured to transmit the integral result value from the memory to the accelerator. The method of claim 1, The retriever comprises a double buffered retriever result buffer, wherein each block of the double buffered retriever result buffer is associated with either the retriever or the data mover. The method of claim 1, And the searcher is configured to perform up to 32 tasks in one initial integration period. The method of claim 1, Each task specifies a plurality of code phase hypotheses of an associated code, and wherein each of the plurality of coherent integration result values is based on one of the plurality of code phase hypotheses. The method of claim 1, And the initial integration period comprises a code period. The method of claim 1, And the initial integration period comprises one millisecond. The method of claim 1, And the retriever is configured to determine the plurality of programmable tasks based on a task queue that can be updated every initial integration period. The method of claim 7, wherein And the searcher is configured to determine a task queue for a future initial integration period during processing of tasks in the task queue corresponding to the current initial integration period. The method of claim 1, And the accelerator is further configured to generate an energy value for each of the at least one coherent accumulation. The method of claim 9, And the accelerator is further configured to generate a non-coherent integration of energy values. The method of claim 1, And the accelerator is configured to generate the at least one coherent accumulation over a frequency span that is greater than 0 hertz and less than 500 hertz. The method of claim 1, The accelerator including a double buffer, each block of the double buffer being associated with one of the accelerator or the data mover, wherein access by the accelerator and the data mover is defined to the block of the double buffer to which it is associated, Device for code space searching. The method of claim 1, Wherein the number of frequency offsets is determined based in part on the coherent integration length. Device for code space searching, A memory having a portion allocated for code space search, the portion depending on an active programmable search mode; And An integrated circuit coupled to the memory, The integrated circuit, A searcher configured to generate a plurality of coherent integration result values determined during an initial integration period for each of the plurality of programmable search tasks; An accelerator configured to determine a coherent accumulation of coherent integration results through the coherent integration length and frequency hypothesis determined by the active programmable search mode; And And a data mover configured to perform DMA data transfer between the searcher and the memory and between the accelerator and the memory. The method of claim 14, Each search task specifies a set of code hypotheses selected from a code. The method of claim 14, And the searcher is configured to support up to 32 different search tasks in one initial integration period. The method of claim 14, And the data mover is configured to perform data transfer from the memory to an associated block of the double buffered sample buffer of the accelerator. The method of claim 14, And the data mover is configured to perform a data transfer from the associated block of the double buffered retriever buffer of the retriever to the memory. As a code space search method, Capturing complex samples of the received wireless signal; Configuring a plurality of code space search tasks; Executing each of the code space search tasks to generate a plurality of coherent integration result values obtained during an initial integration time; And Determining a coherent accumulation of a plurality of coherent integration results, a frequency offset associated with the coherent accumulation, and an integration length based on a programmable code space search mode. 20. The method of claim 19, Determining the energy of the coherent accumulation. 20. The method of claim 19, Determining energy of the coherent accumulation; And Determining a non-coherent integration of an energy grid location corresponding to the energy. 22. The method of claim 21, Storing the non-coherent integral in a block of energy double buffer associated with an accelerator; Swapping an association of blocks of the energy double buffer with a data mover; And And transmitting the non-coherent integral from the block of energy double buffer to a memory. 20. The method of claim 19, Storing the plurality of coherent integration result values in a block of a retriever double buffer associated with a retriever. 24. The method of claim 23, Swapping an association of blocks of the retriever double buffer with a data mover; And And transmitting a coherent integral result from the block of the retriever double buffer to memory. 20. The method of claim 19, Executing each of the code space search tasks, Determining a plurality of code space hypotheses; And Correlating each of the code space hypotheses to at least some of the complex samples. 20. The method of claim 19, Determining the coherent accumulation, Transferring the plurality of coherent integration results from a memory to a first block of a sample double buffer; Swapping an association of the first block of the double buffer with an accelerator; And Determining the coherent accumulation of the plurality of coherent integration result values in the first block. As a code space search method, Capturing complex samples of the received wireless signal; Executing a plurality of code space search tasks to generate a plurality of coherent integration result values corresponding to the plurality of code space hypotheses; Storing the plurality of coherent integration result values in a memory; Retrieving from the memory the number of coherent integration result values corresponding to the integration length; And Determining a coherent accumulation of the number of coherent integration results. 28. The method of claim 27, Determining the energy of the coherent accumulation. 28. The method of claim 27, And determining a non-coherent energy integration based on the energy of the coherent accumulation. 28. The method of claim 27, Executing each of the plurality of code space search tasks includes determining a correlation of a plurality of code hypotheses for at least some of the complex samples. 28. The method of claim 27, The storing of the plurality of coherent integration result values in a memory may include: Storing at least a portion of the plurality of coherent integration results in a block of double buffers; Swapping associations of blocks of the double buffer; And Transferring said portion of said plurality of coherent integration result values from a block of said double buffer to a memory. Device for code space searching, Means for capturing complex samples of a received wireless signal; Means for configuring a plurality of code space search tasks; Means for searching according to each of said code search tasks to generate a plurality of coherent integration result values obtained during an initial integration time; And Means for determining a coherent accumulation of a plurality of coherent integration result values, a frequency offset associated with the coherent accumulation, and an integral length based on a programmable code space search mode. Code space lookup device, Means for capturing complex samples of a received wireless signal; Means for retrieving the complex samples according to each of the plurality of code space retrieval tasks to generate a plurality of coherent integration result values corresponding to a plurality of code space hypotheses; Means for storing the plurality of coherent integration result values; Means for transmitting the number of coherent integration result values corresponding to the integration length; And And means for determining a coherent accumulation of the plurality of coherent integration result values.

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