JP5295788B2 - Method and apparatus for performing code space search at receiver - Google Patents

Abstract

Apparatus and methods of implementing code space search of received signals are described herein. A code space search is implemented as a searcher (220) that perform a subtask that is dynamically reconf igurable at each boundary of an initial integration time. Each particular subtask sets forth a programmabl configuration of coherent integration hypothesis that are performed during th initial integration time. The searcher stores the results of the coherent integration hypothesis in a first portion of memory. A search accelerator (250) operates on the initial integration results. The search accelerator can perform coherent integration of various frequency bins of different timing hypothesis, can generate energy values of the coherent integration results, and can generate a non-coherent energy summation. The energy values of the coherent integrations and non-coherent energy summations are stored in a second portion of memory. The ability to reconfigure the subtasks and accelerator operation provides flexibility in search space dimensions.

Description

(Cross-reference of related applications)
This application claims priority from US Provisional Application No. 60 / 779,172, filed March 2, 2006, "Long Coherent Integrator and Method for Signal Acquisition", and US Patent Provisional Application No. 60 / 885,523, filed Jan. 17, 2007, "Method and apparatus for performing code space search at receiver". Both of the above related applications are assigned to the assignee and are incorporated herein by reference in their entirety.

  The present disclosure relates to locating a wireless communication device. More specifically, the present disclosure relates to a reconfigurable system for code space search in a wireless communication device.

  Many wireless communications communicate information using a direct sequence spread spectrum. The code used to spread the signal is generally a pseudo-random code. The receiver typically recovers the underlying information by correlating the spreading code with the locally generated code.

  The receiver uses the time offset associated with the code to establish a time reference that can be used to locate. Positioning based on timing established from the pseudo-random spread signal is performed in various position location systems.

  For example, the Global Positioning System (GPS) navigation system employs satellites that exist in orbit around the earth. A GPS user can derive accurate navigation information anywhere on the globe including 3D position, speed and date. The GPS system consists of 24 satellites deployed in a circular orbit with a radius of 26,600 kilometers in three planes inclined at an angle of 55 ° to the equator and spaced at an angle of 120 ° to each other. Contains. The eight satellites are equally spaced in each of the three orbital paths. Position measurement using GPS is based on measurement of a propagation delay time of a GPS signal broadcast from an orbiting satellite to a GPS receiver. Usually, the reception of signals from four satellites is necessary for accurate positioning in four dimensions (latitude, longitude, altitude, time). When the receiver measures the received signal propagation delay, the distance to each satellite is calculated by multiplying each delay by the speed of light. It is then determined by solving a set of 4 equations that are 4 unknowns, including location and time measured distance and known satellite location. The exact function of the GPS system is maintained by an on-board atomic clock means for each satellite and a ground tracking station that continuously monitors and modifies the satellite clock and orbit parameters.

  Each GPS satellite transmits two direct sequence coded spread spectrum signals in the L band. The L1 signal is at a carrier frequency of 1.57542 GHz and the L2 signal is at 1.2276 GHz. The L1 signal is composed of two phase shift key (PSK) spread spectrum signals modulated in phase quadrature. That is, a P code signal (P is strictly) and a C / A code signal (C / A is coarse / acquisition). The L2 signal includes only the P code signal. P and C / A codes are repetitive pseudo-random sequences of bits (also called “chips”) modulated on a carrier. The clock nature of these codes is utilized by the receiver in performing time delay measurements. The codes for each satellite are unique and allow the receiver to identify which satellite has transmitted the given code even if all the satellites are on the same carrier frequency. In addition, a 50 bit / second data stream containing information about system conditions and satellite orbit parameters required for navigation calculations is also modulated onto each carrier. P-code signals are encrypted and are generally not available to commercial and private users. The C / A signal can be used by all users.

  The operations performed in the GPS receiver are generally performed in most direct sequence spread spectrum receivers for the most part. The pseudo-random code modulation spreading effect needs to be removed from each signal by multiplying this effect by a time-aligned locally generated copy of the code in a process known as despreading. Since proper time alignment and code delays tend not to be known at receiver startup, this needs to be determined by searching during the initial “acquisition” phase of GPS receiver operation. Once an accurate code time alignment is determined, this is maintained during the “tracking” phase of GPS receiver operation.

  When the received signal is spread, each signal is composed of a 50 bit / second PSK signal at an intermediate carrier frequency. The exact frequency of this signal is indeterminate due to the Doppler effect caused by the relative motion between the satellite and the terminal unit, and the local receiver GPS clock reference error. Normally, it is necessary to search for this Doppler frequency during initial signal acquisition, which is not known before initial signal acquisition. When the Doppler frequency is almost determined, the carrier demodulation is performed.

  After carrier demodulation, the data bit timing is derived by a bit synchronization loop and the data stream is finally detected. The navigation calculations are performed with the signals from the four satellites acquired and locked, and the necessary time delay and Doppler measurements are made, sufficient to determine the GPS time base and orbital parameters. It can be implemented when a data bit is received.

  One drawback of the GPS system for location determination is that the initial signal acquisition phase takes a long time. As mentioned above, before four satellite signals can be tracked, these satellites need to be searched with a two-dimensional search “space” whose dimensions are code phase delay and Doppler frequency shift. In general, unlike after the receiver “cold start”, if you do not have prior information about the location of the signal within this search space, a large number of code delays (approximately 2000) and Doppler frequencies (about 15) need to be searched. Therefore, for each signal, it is necessary to inspect locations within the search space of 30,000. In general, these locations are inspected sequentially one by one and take 5-10 minutes per process. This acquisition time is even longer if the proofs (ie PN codes) of the four satellites in the field of view of the receiving antenna are unknown.

  If the GPS receiver has already acquired satellite signals and is now in tracking mode, the positioning process is practically immediate. However, when using the routine of the wireless terminal, the user turns on the power and starts the operation promptly. This is a case where emergency communication is intended. In these situations, the time delay associated with the 5-10 minute GPS satellite signal acquisition cold start by the GPS / wireless terminal unit before being located limits the response time of the system.

  Thus, there remains a need in the art for a system and method that reduces the time required to acquire and determine a GPS satellite signal in a GPS / wireless terminal unit.

Summary of the Invention

  Here, an apparatus and method for performing a code space search of a received signal will be described. The code space search is implemented as a searcher that performs subtasks that can be dynamically reconfigured at each boundary of the initial integration period. Each specific subtask reveals a programmable configuration of the coherent integration hypothesis that takes place during the initial integration period. The searcher stores the result of the coherent integration hypothesis in the first part of the memory. A search accelerator operates on this initial integration result. The search accelerator can perform coherent integration of various frequency bins with different timing hypotheses, can generate energy values of coherent integration results, and can generate a sum of non-coherent energies. The energy value of the sum of the coherent integration energy and the non-coherent energy is stored in the second part of the memory. The ability to reconfigure accelerator operations and subtasks provides flexibility in the search space aspect.

  Aspects of the invention include an apparatus for code space search. The apparatus includes a memory, a searcher configured to perform a plurality of programmable tasks, and for each programmable task to generate a plurality of coherent integration results acquired over an initial integration period, and a selectable search mode An accelerator configured to determine at least one coherent accumulation of searcher integration results based on a period length and frequency offset of one or more coherent integrations determined by, and transferring the integration results from the searcher to the memory And a data mover configured to transfer the integration result from the memory to the accelerator.

  Aspects of the invention include an apparatus for code space search. The apparatus includes a memory having a portion assigned to code space search and dependent on an active programmable search mode, and an integration circuit coupled to the memory. The integrator circuit is determined by an active programmable search mode, a searcher configured to generate a plurality of coherent integration results determined over an initial integration period for each of a plurality of programmable search tasks. An accelerator configured to determine coherent accumulation of coherent integration results over the frequency hypothesis and the period length of the coherent integration, and configured to perform DMA data transfer between the accelerator and memory between the searcher and memory Data mover to be included.

  Aspects of the invention include a code space search method. This method captures complex samples of the received radio signal, configures multiple code space search tasks, and generates multiple coherent integration results obtained over the initial integration period. And determining a coherent accumulation of a plurality of coherent integration results, a period length of integration associated with the coherent accumulation, and a frequency offset based on a programmable code space search mode.

  Aspects of the invention include a code space search method. The method captures complex samples of a received radio signal and performs each of a plurality of code space search tasks to generate a plurality of coherent integration results associated with a plurality of code space hypotheses. Storing a plurality of coherent integration results in a memory, reading a plurality of coherent integration results corresponding to the integration period length from the memory, and determining a coherent accumulation of the plurality of coherent integration results.

  Features, objects, and advantages of embodiments of the present disclosure will become more apparent from the drawings and detailed description set forth below. In the drawings, similar elements are denoted by similar reference numerals.

Detailed description

  Systems and methods are described that can dynamically reconfigure code space search for signal acquisition and tracking in a wireless communication environment. The reconfigurable system includes a sample memory configured to store samples for one or more search increments.

  A reconfigurable searcher accesses stored samples for code space search and coherent integration. The reconfigurable searcher includes a plurality of correlators that can be dynamically configured to support any one of a predetermined number of channels. Searcher configuration, as well as correlator assignments for channels, can be updated with each search increment.

  These correlators can generate a correlation result for each of the corresponding channel assignments, and the searcher can write this result into storage. The size of the storage device can be dynamically reassigned based on the desired coherent integration period.

  The data mover accesses this storage device and transfers the searcher results to the sample buffer. The sample buffer can be configured as a double buffer having a first sample buffer portion and a second sample buffer portion. The data mover alternately writes to one of the first or second buffer portions to allow simultaneous reading of the buffer portions not being written. The sizes of the first and second sample buffer portions can be dynamically configured to correspond to an initial integration period that can be a coherent integration period.

  The accelerator accesses the correlation results from the sample buffer, and then alternately accesses the first sample buffer portion and the second sample buffer portion in a manner complementary to the timing of writing to the sample buffer. The accelerator determines the coherent accumulation of searcher results over a dynamically adjustable initial integration period. The length of the initial integration period can be extended beyond the potential data modulation period. For example, this initial integration period can be extended beyond a 20 ms data modulation period by tracking edge transitions and received data. The accelerator can selectively invert the correlation results based on edge transitions and potential data values.

  The accelerator can generate energy or magnitude for each of the coherent accumulation results. The accelerator writes the energy result to the energy buffer. The energy buffer can also be configured as a double buffer with a first energy buffer portion and a second energy buffer portion. The accelerator can write to the first portion of the energy buffer and simultaneously read from the second energy buffer portion.

  The data mover can also be configured to read and write to the energy buffer. The data mover can read the energy results from the energy buffer, write them to the storage device, and read the previous energy results from the storage device to the energy buffer.

  The accelerator can determine non-coherent integration by summing multiple energy results. These results are buffered in an energy buffer so that the data mover can store the non-coherent sum in storage.

  FIG. 1 is a simplified block diagram of an embodiment of a wireless communication system 100 that supports position location.

  The wireless communication system 100 may include one or more terrestrial elements that can communicate with the user terminal 110. User terminal 110 may be, for example, a wireless telephone configured to operate according to one or more communication standards. The one or more communication standards include, for example, GSM, WCDMA, and CDMA2000. The user terminal 110 may be a mobile unit, a mobile unit, or a stationary unit. The user terminal 110 is also called a mobile unit, a mobile terminal, a mobile station, a user equipment, a portable device, a telephone, or the like.

  User terminal 110 generally communicates with one or more base stations 120a or 120b, shown here as sectored cellular towers. Typically, user terminal 110 attempts to communicate with a base station that provides maximum signal strength at a receiver within user terminal 110, eg, 120b. Two base stations 120a, 120b and one user terminal 110 are shown in FIG. 1 for convenience and clarity purposes. The system typically has multiple base stations and can support more than one user terminal.

  The user terminal 110 can partially determine its position based on position search signals received from one or more signal sources. These signal sources may include one or more satellites 130 that may be part of a satellite based location system such as GPS. These signal sources may also include one or more base stations 120a or 120b.

  The user terminal 110 can partially determine its location by determining the pseudorange to each location search signal source. When each position search signal source transmits a position search signal spread using a pseudo noise code, the user terminal determines the pseudo distance to some extent by correlating the locally generated pseudo noise code with the received signal. The phase of the received pseudo noise signal can be determined. The user terminal 110 can determine a pseudorange that correlates with time or distance based in part on the phase of the received pseudonoise signal.

  Each of the base stations 120a and 120b can be coupled to a base station controller (BSC) 140 that routes communication signals to and from the appropriate base stations 120a and 120b. BSC 140 may be coupled to a mobile switching center (MSC) 150 that may be configured to operate as an interface between user terminal 110 and public switched telephone network (PSTN) 170. Thus, MSC 150 may be coupled to PSTN 170. Further, the MSC 150 may be configured to coordinate internal system handoff with other communication systems.

  A location center (PLC) 160 may be coupled to the BSC 140. The PLC 160 may be configured to store position search information such as the location of each of the base stations 120a and 120b within the position search system 100, for example. In one embodiment, the PLC 160 can provide this information to the user terminal 110 to determine its location based in part on pseudoranges to multiple signal sources that the user terminal 110 may be a relative arrival time value. It can be constituted as follows. In another embodiment, the PLC 160 can be configured to determine the location of the user terminal 110 based on pseudorange information provided by the user terminal 110. In the latter embodiment, a network server (not shown) in the PLC 160 can make a location search decision to offload processing from the user terminal 110.

  The PLC 160 can be configured to instruct the base stations 120a and 120b via the BSC 140 to generate a position search signal. In another embodiment, the base stations 120a, 120b can be configured to periodically generate position location signals.

  The user terminal 110 can determine its location using any one of several location search techniques in cooperation with the PLC 160. User terminal 110 or PLC 160 may select this technique based in part on the signal source used to generate the pseudorange value. For example, the user terminal 110 may use arrival time (TOA), arrival time difference (TDOA), advanced forward link triangulation (AFLT), or other location search techniques. User terminal 110 or PLC 160 is based on GPS, augments GPS signals with ground-based beacons such as a hybrid location system, and is based on pseudorange values derived from ground-based beacons. The position of the user terminal 110 can be determined by executing the search technique.

  For example, a receiver in user terminal 110 configured to process a GPS satellite signal to generate an initial position fix upon startup may include a full satellite PN code sequence, a full PN code phase hypothesis, and a full Doppler frequency offset. Need to search across. This means that the search is performed over 24 satellites, a range of Doppler frequencies, 1023 code hypotheses (which are typically performed as 2046 discrete half-chip code shifts and calculations). . Once the initial position is determined, the user terminal 110 limits the number of searched frequencies and code phases to a subset based on the satellite signal used in determining the initial position. The user terminal 110 can reduce the number of discrete satellite PN code sequences to search to a set of actually visible satellites, typically eight, and this number can be further reduced to four.

  However, if location cannot be determined using single GPS health information, the user terminal 110 needs to search for one or more PN code sequences for one or more terrestrial beacons. The code sequence used by terrestrial beacons is usually different from the code sequence used by GPS satellites. In addition, the processing and timeline of ground-based location signals are usually different from those for GPS.

  User terminal 110 may include a reconfigurable received signal processor. The reconfigurable signal processor can include multiple independently configurable resources and can support multiple integration periods. These independently configurable resources can be configured to perform a search for a selected code space portion over a configurable time. This search result can be coherently integrated over a configurable integration period. Furthermore, this integration result can be integrated non-coherently.

The implementation of the reconfigurable received signal processor within the user terminal 110 allows the user terminal 110 to concentrate on resources in an efficient manner for current processing conditions. For example, the user terminal 110 may be configured to search for a reconfigurable received signal processor across a maximum number of position search sources in order to quickly identify a position search signal source proof during initial position determination. be able to. For example, the user terminal 110 can first perform a search across a predetermined maximum number of GPS satellites to identify which satellites have generated the received signal. Having determined which satellite generated the received signal, the user terminal 110 can reconfigure the received signal processor to process the identified satellite signal more intensively. For example, the user terminal 110 can configure a longer coherent integration period to improve reception sensitivity along with frequency sensitivity.

  FIG. 2 is a simplified functional block diagram of an embodiment of a reconfigurable position search signal processing system 200 that performs code space searches. The signal processing system 200 includes a sample server 210 coupled to a searcher 220. Searcher 220 generates results that are stored in memory 240. The accelerator 250 accesses the searcher results in the memory 240 to perform additional signal processing.

  The data mover 230 writes the result from the searcher 220 to a location in the memory 240. Data mover 230 also controls read and write operations between buffer 260 and memory 240 associated with accelerator 250. The buffer 260 can be divided into a sample buffer 262 and an energy buffer 264. Each of sample buffer 262 and energy buffer 264 can be configured as a double buffer, where data is written to the first portion of the buffer while other data is read from the second portion of the buffer.

  The controller 270 operates to configure the searcher 220 and the accelerator 250. For example, the controller 270 can configure subtasks performed by the searcher 220. Controller 270 can also configure the coherent integration period or length and the length of the total non-coherent energy performed by accelerator 250.

  Controller 270 can also configure the amount of memory required to store various correlation values and energy sums. The amount of memory required to store the correlation results is determined based in part on the coherent integration period length and the number of non-coherent energy sums. The controller 270 utilizes the memory resources necessary to support the configuration and allows unused memory to be used for other processing. Controller 240 sends a dynamic memory map to data mover 230 to allow data mover 130 to access the appropriate memory location when reading or writing to memory 240.

  In general, the sample server 210 is implemented as a memory such as a RAM that temporarily stores complex samples of received signals. In another embodiment, the sample server 210 is a complex analog to digital converter (ADC) configured to sample the received baseband signal and generate in-phase (I) and quadrature (Q) samples. A simple signal sampler may be included.

  For example, the sample server 210 can be configured to store up to 4 milliseconds of complex samples taken at twice the chip rate. Of course, the sample server 210 is not limited to samples acquired at twice the chip rate, and the actual sample rate may be a fraction or a multiple of the chip rate. For example, the sample server 210 can be configured to store samples taken at a tip rate, four times the tip rate, or at other intervals. If the signal processing system 200 is configured to process received GPS signals, the sampling rate may be about 2 MHz. The sample server 210 can synchronize with a real time clock (not shown) such that the millisecond boundaries of the samples stored therein match the GPS millisecond boundaries corresponding to the code period.

  The searcher 220 operates on complex samples stored in the sample server 210. The searcher 220 supports 32 independently configurable subtasks, and each subtask can be reassigned every millisecond. Each subtask searches 32 chip windows across 64 separate hypotheses. This subtask can be assigned to search for the same or different codes corresponding to GPS satellites. Increasing the number of subtasks assigned to search for a particular satellite code space reduces the average search time. The total number of different hypotheses and the length of each window can be changed by changing the hardware configuration, and the actual number and configuration of subtasks are not limited to the example described above.

  For example, in a GPS code phase search, a subtask can be configured to search a 32-chip window of samples across 64 different hypotheses. The number of hypotheses to search can be programmed by the controller 270 and can be, for example, a multiple of 2 from 2 to 64.

  Prior to performing the code phase search, searcher 220 corrects the frequency offset in the received signal. In one embodiment, searcher 220 can implement a rotator that rotates search samples to a desired center frequency. The amount of frequency offset that can be corrected by the rotator can be determined based in part on a frequency correction loop that can be implemented as a frequency search performed by the signal processing system 200.

  Searcher 220 may optionally perform interpolation of received and oversampled chip sequences. This interpolation processing is also called resampling of the input signal prior to correlation. In one embodiment, the received signal is sampled at a rate twice the code sequence chip rate (chips × 2). The sampler interpolates two consecutive samples and introduces a variable delay. This variable delay is generally shorter than ½ of one chip period, and may be, for example, ¼ of a chip period or a multiple of a short chip period. For example, the resampler can introduce a delay that is a multiple of 1/8 of a chip period, where the multiple is in the range of 0-3.

  Searcher 220 despreads the 32 chip sequence using each of the hypotheses, where the hypothesis corresponds to a particular phase of the locally generated PN code sequence. Each hypothesis can be aligned on a half-chip boundary allowing a search for 32 code phase offsets. In another embodiment, each hypothesis can be aligned at a chip boundary, thereby allowing a search for 64 different code phase offsets. Searcher 220 is configured to store each of the complex correlation results in a search buffer. The data mover 230 can store the buffered search results at a location in the memory 240.

  In one embodiment, search buffer 224 can be configured as a double buffer. Searcher 220 can be configured to update the first portion of the double buffer while data mover 230 accesses the second portion of the double buffer to move past searcher results to memory 240. This double buffer configuration allows searcher 220 to be computationally limited rather than data transmission limited. By configuring the double buffer, it is not necessary to complete the transfer of the preceding calculation result before executing the next searcher task, and the data transmission of the preceding result and the processing of the latest task can occur simultaneously. .

  Of course, the searcher 220 is not limited to the use of a double buffer configuration, but may use other memory configurations capable of simultaneous processing and data transmission. For example, the searcher 220 can implement a circular buffer that is large enough to allow a full data transfer to occur before the next update of a particular memory location.

  The configuration of the searcher 220 and in particular the configuration of the search code space and the number of hypotheses can be configured for each correlation increment. In the example described above, the correlation increment occurs every millisecond.

  Searcher 220 includes a hardware command register that can be updated for each correlation increment. The controller 270 can write the location and size of the task queue to the hardware command register. As previously described, searcher 220 can be controlled to perform up to 32 separate tasks in a single queue.

  The searcher 220 is configured to access the queue specified by the hardware command register. The searcher 220 can acquire the task queue during task processing, and can determine the start time of the task specified in the hardware command register based on the validity comparison value.

  Accelerator 250 is configured to process the correlation results from searcher 220. Accelerator 250 can be configured to operate on data stored in buffer 260 to reduce the number of different data transfers that need to be initiated. Buffer 260 may include sample buffer 262 and energy grid buffer 264. Arranging each of sample buffer 262 and energy grid buffer 264 as a double buffer eliminates memory contention problems that may occur in connection with read and write locations in memory 240.

  Each double buffer may include first and second portions or banks of memory. At a given time period, one bank of buffers is coupled to the integration engine of accelerator 250 and another bank of buffers is coupled to or made accessible to data mover 280. The association between the bank and the integration engine or data mover 280 is swapped after each processing interval.

  Accelerator 250 includes an integration engine that includes a plurality of parallel accumulators configured to generate a coherent integration sum over a configurable integration period and a plurality of frequencies. Although the accelerator 250 can be controlled to support virtually any coherent integration period length, the accelerator 250 can also be optimized to support a discrete set of integration period lengths. In one embodiment, the accelerator 250 is configured to generate a coherent integration sum, also called coherent accumulation, over an integration period of 10, 20, 39, 80, 160 milliseconds. Since the searcher 220 generates a coherent integration result over a period of 1 millisecond, the coherent accumulation time in milliseconds corresponds to the period length of the coherent integration. Accelerator 250 can be configured to track bit edges and bit values to accommodate an extended period length of integration over one or more bit edges.

  The number of parallel cumulative paths depends on the complexity tolerance level in the accelerator 250. In one embodiment, the accelerator 250 can include six parallel multiplier accelerator paths that allow, for example, integration of a set of samples over six different frequencies. The operation of the parallel cumulative path can be repeated to support many frequencies and many sample sets.

  The accelerator buffer 262 may be sufficient to perform a 20 millisecond integration for all hypotheses of one task. Similarly, the energy buffer 264 may be large enough to support 20 frequencies over each of the 64 time offsets. Integration over 20 milliseconds can be done by processing a subset of the total time offset within an operation. N accelerator operations are used to perform 20 * N millisecond integration. Each operation processes 63 / N time hypotheses. Each sample memory holds 20 * N milliseconds for each of 64 / N time offsets. Each energy memory holds 20 * N frequencies for each of 64 / N time offsets. As a result, the memory bandwidth and accelerator transaction rate required to support different integration period lengths does not change.

  For example, the accelerator 250 may be configured to simultaneously support 20 milliseconds of accumulated time over 64 different time hypotheses during a single operation, or 8 different during the same single operation. It can be configured to support a cumulative time of 160 milliseconds across the time hypothesis. The accelerator 250 can perform eight separate operations to search for the same 64 frequency hypotheses. Thus, the data bandwidth utilized by the accelerator is kept constant regardless of the integration period.

  The size of the frequency range across the accelerator 250 is typically a total of 500 hertz that extends approximately 250 hertz above and below the nominal frequency. The number of frequency hypotheses analyzed simultaneously by the accelerator 250 varies depending on the duration of the coherent integration. In one embodiment, the number of frequency hypotheses that are processed simultaneously is set equal to the period length of the coherent integration. The accelerator 250 places the different frequency bins at approximately uniform intervals across the frequency span.

  The accelerator 250 determines the coherent integration at a particular frequency offset by rotating the input sample with a cumulative and desired frequency offset over the duration of the coherent integration. The accelerator 250 then calculates the coherent sum energy to populate the two-dimensional energy lattice. The two-dimensional energy grid can contain the current coherent integration period length energy for each time hypothesis and each frequency offset.

  The accelerator 250 can be configured to determine a coherent sum for all frequencies of a particular time hypothesis before determining a coherent sum of another time hypothesis. By executing the coherent sum in this way, the number of times the memory is accessed can be minimized. Of course, in another embodiment, the use of frequency offsets may be processor intensive, and the coherent sum of each frequency offset across all time hypotheses is completed before determining the coherent sum for another frequency offset. can do. Another embodiment can determine this sum in any other order.

  Data mover 230 operates as a DMA engine to transfer information between searcher 220 and memory 240 and between memory 240 and accelerator 250. The data mover 230 transfers the memory to each location depending at least in part on the search mode and the associated integration period length. The data mover 230 can determine the memory map based on the task queue from the controller 270.

  Data mover 230 copies the coherent sum generated by searcher 220 for each scheduled subtask. In embodiments where the searcher 220 double buffers the coherent sum, the data mover 230 transfers blocks from a buffer that has not yet been written by the searcher 220. Data mover 230 is configured to operate on data in a block of buffers not associated with the current subtask operation.

  Similarly, the data mover 230 is written by the accelerator 250 with the previously stored searcher output and the previously determined energy sum from the memory 240 to the buffer 262 in the accelerator 250, particularly in connection with the memory transfer. Copy to no buffer block. The data mover 230 also copies the latest energy sum from the accelerator buffer to the memory 230.

  The controller 270 generates a task queue and associated control information written in the hardware command register of the searcher 220. The controller 270 can configure substantially any search and integration period length supported by the space available in the memory 240. However, the controller 270 generally has a predetermined number of search configurations or search modes that can be selected and programmed at each control boundary. For example, the controller 270 may have a high search mode over 1600 Hz, 20 different frequency bins, 64 hypotheses, 20 coherent lengths, a first low search mode over 400 Hz, 80 different frequency bins, 16 hypotheses. In addition, a coherent length of 80, a second low search mode over 200 Hz, 160 different frequency bins, 8 hypotheses, a coherent length of 160, a coarse acquisition search mode spanning 1600 Hz, 8 different frequency bins , 8 hypotheses, one of 20 coherent lengths can be selected.

  FIG. 3 is a simple functional block diagram illustrating an embodiment of data flow in a receiver that implements a position search signal processing system 200 for code space search. The system 200 will be described with reference to GPS code space search processing. However, a similar code space search can be processed for other PN code spreading information such as AFLT.

  Sample server 210 receives complex input samples at about twice the chip speed and writes the samples to a memory such as RAM. The sample server 210 can be configured to arrange the RAM as a circular buffer and to overwrite the oldest entry with the latest sample.

  The searcher 220 examines the contents of the hardware command register to determine the location and size of the task queue. The hardware command register in the searcher 220 can be programmed during the processing of the task queue specified by the past hardware command register contents. The searcher 220 can determine the start time of the next scheduled search task and start a new search task as soon as the current search task is finished.

  Each task queue can control up to a predetermined maximum number of subtasks processed during an initial search period that can be 1 millisecond. Searcher 220 can process the subtasks and write a coherent sum of each hypothesis to a buffer in searcher 220. The searcher buffer can be organized as a double buffer. Two blocks of the searcher double buffer can be alternately associated with one of the searcher 220 or the data mover 230. The block associated with the searcher 220 receives the correlation result generated by the searcher 220, while the block associated with the data mover 230 allows the block data to be transferred from the searcher 220 to the memory 240. The relevance of blocks in the searcher double buffer is swapped at a predetermined time. For example, if the searcher 220 fills a block associated with it, the relevance of the blocks is swapped.

  Data mover 230 performs data transfer 310 between the associated searcher 220 buffer and memory 240. The data mover 230 need not synchronize the data transfer 310 performed in the searcher 220 with the coherent integration process. Instead, the data mover 230 can be configured to perform the data transfer 310 at any time when the buffer block association is valid. The data mover 230 determines the location in the memory 240 for writing the value based at least in part on the active search mode initiated by the controller (not shown). The size of the memory 240 allocated to the system 200 can be dynamic and can change based on, for example, the active code search mode. As an example, the storage space memory 240 required for bit edge search mode over 1600 Hz, 8 different frequency bins, 8 hypotheses, 20 coherent lengths is 200 Hz, 160 different frequency bins, 8 hypotheses, It is smaller than the storage space memory required for the low search mode over 160 coherent lengths.

  When the memory 240 is shared with processing different from the code space search, such as when the memory 240 is a system memory for a wireless communication device, a task different from the code search is performed by dynamic allocation of the memory space. The memory space that can be used to support is maximized. System 200 need only be allocated enough memory 240 space to support the active code search mode.

  The data mover 230 can also control the operation of data transfer 320 into the double buffered sample buffer 262 of searcher results stored in memory. Since accelerator 250 consumes searcher results during coherent integration, data transfer 320 to sample buffer 262 may be unidirectional from memory 240 to sample buffer 262.

  The double buffered sample buffer 262 can change the association of the first and second blocks between the data mover 230 and the accelerator 250. The accelerator 250 controls the read operation 340 from the associated sample buffer 262 block. Data mover 230 and accelerator 250 can swap the relevance of the sample buffer 262 block once accelerator 250 has accessed all the data in the associated sample buffer 262 block.

  The accelerator 250 determines a coherent sum of searcher results over a coherent accumulation period length determined based on a search mode programmed by the controller. The accelerator 250 can generate the energy value of each coherent integration by adding the squares of the complex components of the coherent integration result.

  The accelerator 250 can transfer the energy value to the memory 240 by writing the energy value to the energy buffer 264. Alternatively, the accelerator 250 can be configured to generate a non-coherent accumulation of energy values by adding the current energy value calculated in the same energy grid location and the past energy value.

  The accelerator 250 controls the bi-directional data transfer 350 of energy values between related blocks of the double buffered energy buffer 264. The energy buffer 264 can be configured as a double buffer with blocks alternately associated with one of the data mover 230 or the accelerator 250.

  The data mover 230 controls the bi-directional data transfer 330 of energy values between the memory 240 and the associated block of energy buffer 264. Similarly, the accelerator 250 controls energy buffer read and write operations 350 between blocks of the associated energy buffer 350. The relevance between blocks of the energy buffer 264 can be swapped based on the schedule determined by the active search mode.

  Data mover 230 can access previously stored energy results from memory 240 and copy this value to the associated block of energy buffer 264 during data transfer operation 330. After a swap associated with a block, accelerator 250 can access energy values previously transferred by data mover 230, and can determine non-coherent accumulation using, for example, current energy values. The accelerator 250 controls the write operation 350 back to this energy buffer 264 block. When the block of energy buffer 264 is swapped again, the data mover 130 can transfer the updated energy value 330 from the energy buffer 264 to the memory 240.

  The accelerator 250 process can be performed in a pipeline format to process the data more efficiently. This pipeline type processing may be, for example, a pipeline of three different operations. The pipeline can support input data transfer for one operation, coherent accumulation and energy value processing for the second operation, and past result data transfer from the accelerator 250 to the memory 24 for the third operation.

  Thus, while the accelerator 250 is operating on the searcher results for past data transfers (operation N), the data mover 230 can transfer the searcher results from the memory to the sample buffer (operation N + 1). In addition, the data mover 230 can transfer the accumulated energy sum from the energy buffer to the memory 240 for the third different operation before loading the values previously stored from the external memory 240 into the energy buffer ( Operation N-1).

  FIG. 4 is a flowchart illustrating an embodiment of a code space search method 400. This method 400 can be realized by the position search signal processing system of FIG. 2 and can be realized by the user terminal in FIG. Method 400 illustrates processing across functional blocks. The sequence of operations in method 400 illustrates the processing of a set of samples throughout the system. With the simultaneous generation of multiple operations in the system, it is possible to operate the method continuously without reconfiguration or data transfer latency.

  Method 400 begins at block 402 where the system captures complex samples of a received signal to be searched. For example, the signal sampler can receive a received GPS signal at a rate approximately twice the PN code rate. Complex samples can be stored in RAM or other storage devices.

  The system then proceeds to block 410 where the searcher is configured to support a specific code search processing mode. The searcher can determine the processing mode for future samples while processing the samples according to the current processing mode. For example, the searcher can determine the location and size of the task queue by reading the hardware command register. The searcher can execute tasks in the task queue at task boundaries or when processing of the current task is complete. The task queue can include multiple tasks until a predetermined maximum number of tasks is reached. For example, the task queue can contain up to 32 tasks that are executed for the searcher in each initial integration period, eg, 1 millisecond.

  Each search task can support a search across a predetermined number of code chips over multiple hypotheses. The number of hypotheses to search can be programmed, and this number can be varied up to a predetermined maximum number of hypotheses. For example, each task can be configured to search a window containing 32 code chips, and can be configured to search up to 64 different hypotheses for the search window, where each code space hypothesis May deviate by 1/2 chip period from the closest hypothesis.

  The system then proceeds to block 412. Here, samples associated with the search configuration are transferred from the sample memory to the searcher. The searcher may be configured to search the entire code space of one satellite vehicle within an initial integration period of 1 millisecond using the example provided above. More generally, however, the searcher is configured to search for received samples for portions of multiple codes.

  After transferring the relevant samples, the system proceeds to block 414 and performs the tasks described in the task queue. Each task result within the coherent integration of a sample over an initial integration period of 1 millisecond accesses each of the hypotheses applied by the task, but other embodiments may use a different initial integration period. it can.

  The searcher proceeds to block 416 and writes the coherent integration results from each hypothesis into the associated double buffered block. The double buffer contains two blocks that are alternately associated with either the searcher or the data mover. In order to transfer data from its associated buffer block, the searcher writes to the associated buffer block. By double buffering the searcher output, both the searcher and the data mover prevent memory contention when accessing data from the buffer. While the searcher is operating on the sample and writing to another part of the double buffer, the previously buffered results can be read from the part of the double buffer. Since it is not necessary to complete the transfer of the previous searcher result before starting the next searcher operation, the double buffer enables more flexible data transfer. In addition, if the DMA memory transfer by the data mover can be achieved in a time shorter than the time to populate the searcher results, the transfer of the results to the memory can be scheduled more flexibly.

  Since the resulting transfer only occurs from the block of search buffers associated with the data mover, the system proceeds to block 418 and swaps the relevance between the blocks of the double buffer. Swapping block associations allows the most recent result to be transferred to memory while keeping the block of buffers available for storing the current integration results.

  After swapping the block association of the searcher double buffer, the system proceeds to block 420. At block 420, the data mover transfers the initial coherent integration result from the searcher to memory. In one embodiment, the memory is shared by other processes, and the data mover performs a DMA transfer to each location in the shared memory of the searcher buffer.

  After transferring the searcher results to memory, the system proceeds to block 430. At block 430, the data mover transfers at least some of the searcher results from memory to the relevant block of the sample buffer, allowing the accelerator to process some of the results. With each block of the sample buffer associated with either the data mover or the accelerator, the sample buffer can also be configured as a double buffer. The sample buffer block association can be swapped after a given event. This predetermined event may be buffer filling, timing, or other events.

  The system proceeds to block 432 and transfers at least a portion of the past energy accumulation from the memory to the relevant block of the energy buffer for access by the accelerator. The system may return the updated result from the energy buffer to the memory before transferring the energy accumulation that is to be updated from the memory to the energy buffer. The energy buffer can also be configured as a double buffer. One block of the double buffer is associated with the data mover and another block of the double buffer is associated with the accelerator. The energy buffer association can be swapped after executing a predetermined event separate from the event that initiates the swap of the sample buffer block.

  The accelerator accesses only the block of sample buffers and the associated block of energy buffers. Therefore, the system proceeds to block 434 to swap the sample buffer and energy buffer associations so that the accelerator can access the latest value transferred from memory by the data mover. In addition, the data mover can access the latest energy results from the accelerator. The accelerator consumes searcher results and does not rewrite the results to the search buffer. Therefore, swapping search buffer blocks creates additional space for the data mover to transfer to the sample buffer.

  After swapping buffer associations, the system proceeds to block 450 where it determines the coherent accumulation of accessible search results in the associated sample buffer. The accelerator determines coherent accumulation based on the active code search mode. The accelerator must wait depending on the size of the sample buffer while multiple swaps between sample buffers are performed to support the desired integration period length.

  If the duration of the integration crosses a data boundary, such as the 20 millisecond data boundary used in GPS signals, the accelerator tracks the occurrence of the bit boundary and interpolates the bit value in calculating the accumulation can do.

  The accelerator can also determine coherent accumulation for multiple frequency bins based on the active search mode. The accelerator may include multiple parallel paths that allow simultaneous accumulation for multiple frequencies or multiple searcher results.

  The system then proceeds to block 452, where the energy associated with each coherent accumulation is determined. The accelerator can determine the energy associated with the complex cumulative value, for example by summing the squares of the in-phase value and the square value. In some embodiments, the accelerator may omit the determination of accumulated energy and instead store a complex accumulated value in the energy buffer. In embodiments where the accelerator stores the sum of the coherent accumulations in a buffer rather than an energy value, the operations of blocks 452-454 may be omitted. The accelerator can directly update the energy buffer with the coherent accumulation value.

  The system proceeds to block 454 where it determines any non-coherent energy accumulation that the code search mode can specify. To determine non-coherent accumulation, the accelerator reads past energy values from the desired position of the energy grid in the energy buffer and sums the associated energy values. In some embodiments, the accelerator determines a weighted sum and further adjusts the past accumulated energy sum by a predetermined fraction depending on the size of the sample buffer before summing the latest energy values. can do.

  The system proceeds to block 456 where the accelerator writes the accumulated energy value back into the energy buffer. In general, the system does not directly access the block of energy buffers associated with the accelerator. Thus, the system proceeds to block 458 and waits for the next energy block related swap to occur.

  At block 460, the data mover accesses the latest energy value updated by the accelerator. The data mover can DMA transfer the updated energy accumulation to the memory. The data mover can also load any energy value from the memory into the energy buffer to support the next non-coherent accumulation.

  Following block 460, processing of the particular sample received completes the entire processing path from sampling to energy accumulation. By performing various intermediate value double buffering and memory storage, the entire process can be executed substantially continuously. While the searcher is operating on a task scheduled in the past, the searcher can be reconfigured at each initial cumulative boundary, so the system needs to abort or wait for changes in the search configuration. Absent. Double buffering of the searcher results at both the searcher and the input to the accelerator effectively eliminates memory contention while increasing the flexibility of access to the memory. This memory may be a module having a searcher and an accelerator or a shared memory provided outside the integrating circuit.

  By separating the initial coherent integration from the coherent integration associated with a longer integration period, system scheduling and configuration becomes more flexible. The 1 ms integration result from the searcher can be used to support virtually any integration period length.

  FIG. 5 is a simple functional block diagram illustrating an embodiment of a position search signal processing system 500 that implements code space search. The system 500 shown in FIG. 5 can be realized, for example, in the user terminal shown in FIG.

  System 500 includes means 510 for capturing complex samples of received radio signals. The means 510 for capturing the complex sample is coupled to the search means 520.

  The search means 550 can operate according to each code space search task specified by the hardware register 522, and the hardware register 522 operates as a means constituting a plurality of code space search tasks. Search means 550 generates a plurality of coherent integration results acquired over an initial integration period that may be met in, for example, 1 millisecond. Search means 550 can be configured to generate a plurality of coherent integration results associated with a plurality of code space hypotheses, as defined in the search task.

  The control means 570 controls the value written in the hardware register. The value in the hardware register 522 can be specified, for example, in a task queue in memory determined based on the code space search mode. Data transfer means 530 is coupled to search means 520 and operates to transfer a plurality of coherent integration results to storage means 540. Data transfer means 530 also transfers a plurality of coherent integration results from storage means 540 to buffer means 562, 564 in or coupled to acceleration means 550. Specifically, the data transfer means 530 transfers a large number of coherent integration results related to the integration period length.

  The acceleration means 550 operates as means for determining coherent integration of a plurality of coherent integration results. The integration period length and frequency offset associated with coherent integration are based on a programmable code space search mode.

The code space search system, apparatus, and method have been described herein. The described system, apparatus, and method can be implemented in a user terminal to process GPS signals, AFLT signals, etc., or other code spread signals. For example, the code space search process and apparatus is applied to search for an arbitrary code space of the received spread spectrum signal. Although specific embodiments describe application to GPS signals, the challenge claimed belongs to code space search and is not limited to GPS. The searcher is configured to determine a coherent integration result over an initial integration period or time. The searcher results are used as intermediate values for further coherent integration and non-integral energy accumulation performed in the accelerator.

   Intermediate values are stored in double buffers to allow for efficient and non-competitive data transfer to memory. The use of a double buffer allows the code search mode to be reconfigured with low or no latency.

  In addition, by separating the processing following the coherent integration over the initial integration period, the code space search mode can be flexibly reconfigured without redundant data acquisition and analysis. The function of reconfiguring the code space search in near real time enables more efficient code space search, and also enables reconfiguration from high-speed code acquisition to high-sensitivity code space search.

  As used herein, the term “coupled” or “connected” means non-direct coupling as well as direct coupling or connection. When two or more blocks, modules, devices, or devices are combined, there may be one or more intervening blocks between the two connected blocks.

  Various illustrative logic blocks, modules, and circuits described herein in connection with the disclosed embodiments can be general purpose processors, digital signal processors (DSPs), reduced instruction set computer (RISC) processors, application limited integrated circuits ( ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or these designed to perform the functions described herein Realized or implemented by any combination. A general purpose processor may be a microprocessor, but in the alternative, may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a combination of multiple microprocessors, a combination of one or more microprocessors and a DSP core cooperating therewith, or other similar configuration. be able to.

  The methods, processes, and algorithms described herein in connection with the disclosed embodiments can be implemented directly in hardware, in a software module executed by a processor, or a combination of the two. The various steps or operations in the method or process may be performed in the order presented here or in any other order. In addition, one or more processes or method steps may be omitted, or one or more processes or method steps may be added to these methods and processes. Additional steps, blocks, and actions can be added to the beginning, end, and intermediate elements of the method and process.

  The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. can do. Accordingly, the present disclosure is not limited to the embodiments shown herein but is consistent with the widest scope consistent with the principles and novel features of the disclosure herein.

1 is a simplified block diagram of an embodiment of a wireless communication system that supports position location. FIG. 1 is a simplified functional block diagram of an embodiment of a position search signal processing system that implements code space search. FIG. FIG. 6 is a simplified functional block diagram illustrating an embodiment of data flow in a receiver that implements code space search. 5 is a flowchart of an embodiment of a method for code space search. 1 is a simplified functional block diagram of an embodiment of a position search signal processing system that implements code space search. FIG.

Claims (33)

A device for code space search, the device comprising:
Memory,
Performing a plurality of programmable tasks , each of the plurality of programmable tasks configured to generate a plurality of coherent integration results obtained over an initial integration period , wherein each of the plurality of programmable tasks is and dynamically reconfigurable der Ru searcher at the boundaries of the integration period,
An accelerator configured to determine a coherent accumulation of the plurality of integration results based on one or more coherent integration period lengths and frequency offsets determined by a selectable search mode;
An apparatus comprising: a data mover configured to transfer the plurality of integration results from the searcher to the memory and configured to transfer the integration results from the memory to the accelerator.   The apparatus of claim 1, wherein the searcher comprises a double-buffered searcher result buffer, wherein each block of the double-buffered searcher result buffer is associated with one of the searcher or the data mover.   The apparatus of claim 1, wherein the searcher is configured to perform a maximum of 32 tasks within one initial integration period.   The apparatus of claim 1, wherein each task identifies a number of code phase hypotheses of an associated code, and each of the plurality of coherent integration results is based on one of the number of code phase hypotheses.   The apparatus of claim 1, wherein the initial integration period comprises a code period.   The apparatus of claim 1, wherein the initial integration period comprises about 1 millisecond.   The apparatus of claim 1, wherein the searcher is configured to determine a plurality of programmable tasks based on a task queue that can be updated every initial integration period.   8. The apparatus of claim 7, wherein the searcher is configured to determine a task queue for a future initial integration period during task processing in a task queue corresponding to a current initial integration period.   The apparatus of claim 1, wherein the accelerator is further configured to generate an energy value for each of the at least one coherent accumulation.   The apparatus of claim 9, wherein the accelerator is further configured to generate a non-coherent integral of energy values.   The apparatus of claim 1, wherein the accelerator is configured to generate the at least one coherent accumulation over a frequency span of less than or equal to about 500 Hertz.   The accelerator comprises a double buffer, each block of the double buffer being associated with one of the accelerator or the data mover, and access by the accelerator and data mover is restricted to the block of the double buffer with which it is associated. The device described in 1.   The apparatus of claim 1, wherein multiple frequency offsets are determined based in part on the integration period length. A device for performing a code space search, the device comprising:
A memory having a portion assigned to code space search and dependent on an active programmable search mode;
An integrating circuit coupled to the memory, the integrating circuit comprising:
Configured to generate a plurality of coherent integration results determined over an initial integration period for each of the plurality of programmable search tasks, wherein each of the plurality of programmable search tasks is at a boundary of the initial integration period A searcher that is dynamically reconfigurable,
An accelerator configured to determine a coherent accumulation of coherent integration results over a frequency hypothesis determined by an active programmable search mode and a coherent integration period length; and between the searcher and memory, between the accelerator and memory A device including a data mover configured to perform DMA data transfer in   The apparatus of claim 14, wherein each search task identifies a set of code hypotheses selected from the code. The apparatus of claim 14, wherein the searcher is configured to support up to 32 different search tasks during an initial integration.   15. The apparatus of claim 14, wherein the data mover is configured to transfer data from the memory to an associated block of a double buffered sample buffer of the accelerator.   15. The apparatus of claim 14, wherein the data mover is configured to transfer data from an associated block of a double buffered searcher buffer of the searcher to a memory. A code space search method comprising:
Capture multiple complex samples of the received radio signal,
Configure multiple code space search tasks, each dynamically reconfigurable at the boundary of the initial integration period ,
Running each of the plurality of code space search task in order to generate the initial integration of the plurality of coherent integration results obtained over a period,
How comprises determining based on said plurality of coherent integration results of the coherent accumulation, the integration period length and the frequency offset associated with said coherent accumulation programmable code space search mode.   20. The method of claim 19, further comprising determining the coherent cumulative energy. Determining the coherent cumulative energy;
The method of claim 19, further comprising determining a non-coherent integral of an energy grid position corresponding to the energy. Storing the incoherent integral in a block of energy double buffers associated with the accelerator;
Swap the relevance of the energy double buffer block to the data mover,
The method of claim 21, further comprising transferring the non-coherent integration from the block of energy double buffers to a memory.   The method of claim 19, further comprising storing the plurality of coherent integration results in a block of searcher double buffers associated with the searcher. Swap the relevance of the searcher double buffer block to the data mover;
24. The method of claim 23, further comprising transferring a coherent integration result from a block of the searcher double buffer to a memory. Each execution of the plurality of code space search tasks includes:
Determine multiple code space hypotheses,
The method of claim 19, comprising correlating each of the plurality of code space hypotheses to at least a portion of the plurality of complex samples. The determination of the coherent accumulation is
Transferring the plurality of coherent integration results from memory to a first block of a sample double buffer;
Swap the relevance of the first block of the double buffer to the accelerator;
The method of claim 19, comprising determining the coherent accumulation of the plurality of coherent integration results in the first block. A code space search method comprising:
Capture multiple complex samples of the received radio signal,
Performing each of a plurality of code space search tasks each dynamically reconfigurable at a boundary of an initial integration period to generate a plurality of coherent integration results corresponding to the plurality of code space hypotheses;
Storing the plurality of coherent integration results in a memory;
Read a number of coherent integration results corresponding to the integration period length from memory,
Determining a coherent accumulation of these multiple coherent integration results.   28. The method of claim 27, further comprising determining the coherent cumulative energy.   28. The method of claim 27, further comprising determining a non-coherent energy integral based on the coherent cumulative energy. Wherein each of the execution of a plurality of code space search task, the method of claim 27 comprising determining the correlation of the plurality of code hypothesis for at least some of said plurality of complex samples. Storage of the plurality of coherent integration results in memory is
Storing at least some of the plurality of coherent search results in a block of double buffers;
Swap the relevance of the double buffer block,
28. The method of claim 27, comprising transferring a portion of the plurality of coherent search results from the block of double buffers to a memory. A device for performing a code space search, the device comprising:
Means for capturing multiple complex samples of the received radio signal;
Means for configuring a plurality of code space search tasks that are each dynamically reconfigurable at an initial integration period boundary ;
It means for performing a search in accordance with each of the plurality of code space search task in order to generate the initial integrated plurality of coherent integration results obtained over a period,
A plurality of said coherent integration results of coherent accumulation based on the program code space search mode, and means for determining the integration period length and the frequency offset associated with said coherent accumulation. A device for performing a code space search, the device comprising:
Means for capturing multiple complex samples of the received radio signal;
Searching the plurality of complex samples according to each of a plurality of code space search tasks, each dynamically reconfigurable at a boundary of an initial integration period to generate a plurality of coherent integration results corresponding to a plurality of code space hypotheses; Means,
Means for storing the plurality of coherent integration results;
Means for transferring a number of coherent integration results corresponding to the integration period length;
Means for determining a coherent accumulation of the multiple coherent integration results.

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