KR101138879B1 - Communication System - Google Patents

Abstract

The present invention relates to a communication system, and compares a destination address included in a frame transmitted from a master station with an address of a slave station to receive data only when the address is the same, thereby reducing the overhead of the CPU due to unnecessary data reception. It is characterized by providing a communication system capable of.

To this end, the present invention includes a master station for transmitting a communication frame and a plurality of slave stations for receiving a frame transmitted from the master station, and the plurality of slave stations are transmitted from the communication device and the communication device receiving the frame. In a communication system comprising a central processing unit for processing a frame, each slave station is a comparison unit for comparing the first register to store its own address, the address stored in the first register and the destination address included in the frame And a controller for requesting the CPU to process the received frame when the comparison result is the same, and discarding the received frame when the comparison result is different.

Description

Communication System {Communication System}

1 shows a communication block diagram between typical building installations.

2 shows a detailed block of a slave station in communication between typical building facilities.

3 shows a structure of a communication frame according to an embodiment of the present invention.

4 is a block diagram showing a configuration of a communication control apparatus according to an embodiment of the present invention.

5A and 5B are flowcharts illustrating a control method of a communication control apparatus according to an embodiment of the present invention.

6 illustrates the operation of a communication control apparatus according to an embodiment of the present invention through a communication block diagram between building facilities.

The present invention relates to a communication system, and more particularly, when one master station and a plurality of slave stations are connected in a communication scheme such as RS-485, each slave station has its own destination address of a frame transmitted from the master station. The present invention relates to a communication system that can reduce the processing burden of the CPU by making the reception only the same as compared with the address.

In general, one central control unit and a plurality of facility devices transmit and receive data using a communication method such as RS-485 between multi-type air conditioners or building management devices installed in a building.

1 shows a communication block diagram between typical building installations. As shown in FIG. 1, communication between facilities in a building using RS-485 is connected to one master station 10 and a plurality of slave stations 11-1 to 11-n through a communication line 12. To send and receive data.

The master station 10 may be an outdoor unit in the case of a multi-type air conditioner, or a central control unit in the case of a building management device. The plurality of slave stations 11-1 to 11-n may be an indoor unit in the case of a multi-type air conditioner, and may be a management facility for building management in the case of a building management device.

2 shows a detailed block of a slave station in communication between typical building facilities. As shown in FIG. 2, each slave station includes a driver 13 connected to an external interface, a universal asychronous receiver / transmitter (UART) 14 connected to the driver, and a UART connected to the driver. A central processing unit (CPU) 15 (hereinafter referred to as CPU) 15 is included, and generally, the UART and the CPU are implemented in one chip.

The driver 13 is responsible for the physical matching of the signal with the external interface, and the UART 14 converts the data received in series from the external device in parallel and transmits the data to the CPU 15, which is received from the CPU 15. By performing the function of converting the parallel data serially to the external device, it is responsible for asynchronous serial communication between the external device and the CPU (15).

Referring to Figure 1 and 2 will be described the communication process between the conventional building facilities as follows.

When the master station 10 transmits data to a specific slave station, all slave stations 11-1 to 11-n receive data transmitted from the master station 10 to generate an interrupt in the UART 14, The CPU 15 reads the received data in response to the interrupt, and discards the data if the read data is unnecessary.

That is, all slave stations 11-1 to 11-n receive and process all data sent from the master station, and when the destination address is not their own address, communication is performed by discarding the received data.

For example, if 32 slave stations are connected via RS-485, only about 3 percent of the total data received by each slave station is useful for each slave station, and most received data is discarded because it is unnecessary.

In general, low-cost communication devices used for communication between facilities in buildings use 8-bit CPUs and UARTs without first-in-first memory (FIFO). Therefore, interrupts occur frequently and CPUs occur when the communication speed is high. Because most of the work time is allocated for interrupt processing, processing of other tasks can be difficult.

That is, in the case of a CPU that does not have a high processing speed, the conventional communication method as described above has to deal with unnecessary data not transmitted to itself, thereby increasing the overhead of the CPU.

The present invention is to solve the above problems, an object of the present invention is to compare the destination address included in the frame transmitted from the master station and the address of the slave station to receive data only when the address is the same to eliminate unnecessary data It is to provide a communication system that can reduce the CPU overhead due to reception.

 According to an aspect of the present invention, there is provided a communication apparatus including a master station transmitting a communication frame and a plurality of slave stations receiving a frame transmitted from the master station, wherein the plurality of slave stations receive the frame. And a central processing unit for processing a frame transmitted from the communication device, wherein each slave station includes a first register storing its own address, an address stored in the first register, and a destination included in the frame. And a comparator for comparing addresses and a controller for requesting processing of the received frame when the comparison result is the same, and discarding the received frame when the comparison result is different. .

The slave station may receive and store a second register storing the frame transmitted from the master station and a data length included in the frame from the second register, and when data included in the frame is stored. Each counter further comprises a counter that decreases at a predetermined interval.

The slave station may store data until the counter indicates that there is no more data to store.

The slave station may further include a third register that stores a control state of the controller and indicates a control progress state of the controller.

The control state may include controllability, data discard, data length reception, transmission source address reception, destination address reception, and frame start code value reception.

A communication system including a slave station receiving a frame from a master station and controlling the received frame and transmitting the received frame to a central processing unit, wherein the destination address included in the received frame is compared with the address of the slave station. And a data processing step of requesting the CPU to process the received frame if the address of the address comparison step is the same, and discarding the received frame if the address is different. It is characterized by.

In addition, the data processing step stores the data length included in the frame in a counter, and decreases the value of the counter every time the data included in the frame is received, indicating that the value of the counter is no longer data. Characterized in that it is performed until.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

3 shows a structure of a communication frame according to an embodiment of the present invention. As shown in FIG. 3, a frame according to an embodiment of the present invention includes an STX field 20, a DA field 21, an SA field 22, a data length field 23, a data field 24, and an EOF field ( 25, and the FCS field 26.

The STX (Start of Text) field 20 indicates the start of a frame, and an ASCII code corresponding to a body start character (STX) is stored. The DA (Destination Address) field 21 indicates a destination address of a frame, and when a frame is transmitted from a master station, an address of one slave station among a plurality of slave stations is stored. The SA (Source Address) field 22 indicates an address of a source and, when transmitting a frame from the master station, the address of the master station is stored.

The data length field 23 indicates the length of pay load data included in the data field of the frame. The data field 24 is a field in which data which is an effective load is stored. The end of frame (EOF) field 25 is a field indicating the end of a frame, and the frame check sum (FCS) field 26 is a field for detecting an error of a frame.

4 is a block diagram showing a configuration of a communication control apparatus according to an embodiment of the present invention. As shown in FIG. 4, the communication control device 30 receives data serially from an external device, converts the received serial data into parallel data, and performs parity check. Receiving buffer 32 which temporarily stores data while receiving data from 31, and receiving data register 33 which receives data from receiving buffer 32 and transmits data to CPU 15. It includes.

When data is once transmitted from the reception data register 33 to the CPU 15, the transferred data disappears from the reception data register 33 and enters a state in which new data can be received by the reception buffer 32.

In addition, the data counter 34 receives the data length field value of the frame from the input shift register 31 and decreases the value as the data is received. The control unit 35 performs control or logic of each register. The status register 36 is used to determine an internal control process when receiving and processing general data without performing data filtering, and the processing state of the received data, which is used when receiving data by performing filtering. The filtering status register 37 is stored.

And a multiplexer 38 for multiplexing the reception data register 33, the status register 36, and the filtering status registers 37 to transfer the data of the selected register to the CPU 15, and the received data from the CPU 15. And a demultiplexer 39 for demultiplexing the signal to transfer data to a selected one of the plurality of registers.

In addition, the control register 40 which receives and stores the interrupt, filtering, communication speed, or external gate control command received from the CPU 15, and its address for comparison with the destination address field value of the received frame. An address register 41 for storing the STX value, an STX register 42 for storing the STX value for comparison with the STX field value of the received frame, and an own address and an input shift register received from the address register 41; And a second comparator 44 for comparing the STX value received from the STX register 42 and the STX value received from the input shift register.

In addition, a transmission data register 45 for receiving and storing data transmitted from the CPU 15, a transmission buffer 46 temporarily stored before transmitting data, and parallel data received from the transmission buffer are serially converted. And an output shift register 47 that adds a parity bit and transmits it to an external device.

In addition, values such as STX reception, destination address reception, source address reception, data length reception, EOF reception, data discarding, and filtering valid are set in the filtering status register 37 according to the data filtering process. The controller 35 performs the data filtering operation according to the value set in the filtering status register 37.

5A and 5B are flowcharts illustrating a control method of a communication control apparatus according to an embodiment of the present invention. The data filtering operation of the communication control device of the present invention is performed in the slave station, and in order to perform data filtering, the STX value is recorded in the STX register, its address value is recorded in the address register, and the filtering is effective in the filtering status register. Should be set to a value indicating

When the data filtering operation starts, it is determined whether the data filtering is valid by looking at the value recorded in the filtering status register (step S10). If the data filtering is not valid, the data is received and processed in a conventional manner (step S11). If the data filtering is valid, the STX is received (step S12). Then, it is determined whether the STX value is the same by comparing the STX value received in the input shift register with the register value stored in the STX register (step S13).

If the result of the determination in step S13 is the same, it is set in the filtering status register that STX has been received (step S14), and if not, the process returns to step S10. Next, the destination address data of the frame is received (step S15), and the received destination address is compared with the own address stored in the address register to determine whether the addresses are the same (step S16).

If the result of the determination in step S16 is the same, it means that the destination of the data transmitted from the master station is the slave station where filtering is currently performed. Therefore, the destination address data is set in the filtering status register (step S17), and the receiving buffer The received destination address data is stored (step S18). If the determination result in step S16 is not the same, the received data is discarded in the filtering status register (step S19), and the received destination address data is discarded (step S20).

Next, the address of the transmission destination is received (step S21), and it is determined whether the reception buffer is valid (step S22). If it is determined in step S22 that the reception buffer is valid, it is set in the filtering status register that the destination address has been received (step S23), and the received destination address data is stored in the reception buffer (step S24). If the reception buffer is not valid, it sets in the filtering status register that the received data is discarded (step S26), and discards the received source address data (step S27).

Next, data length data is received (step S28), and the received data length data is stored in a data counter (step S29). Then, it is determined whether the reception buffer is valid (step S30), and if it is valid, it is set in the filtering status register that the data length data has been received (step S31), and the data length data is stored in the reception buffer (step S32). If the reception buffer is not valid, it is set in the filtering status register that the received data is discarded (step S33), and the received data length data is discarded (step S34).

Next, data is received (step S35), and the data length value stored in the data counter is decreased by one (step S36). Then, it is determined whether the reception buffer is valid (step S37), and if valid, data is received (step S38). If the reception buffer is invalid, the received data is discarded (step S39).

The value of the data counter is examined to determine whether the counter value is 0 (step S40). As a result of the determination, if the counter value is not 0, it means that there is still data to be received, and the flow returns to step S35.

6 shows the operation of a communication control apparatus according to an embodiment of the present invention through a communication block diagram between facilities in a building. As shown in FIG. 6, the building equipment is composed of one master station 50 and three slave stations 51 to 53, the address of the master station 50 is 0, and the slave stations 51 to 53. ) Are 1, 2, and 3 respectively.

If the master station 50 transmits data to the slave station 3 (53), the STX field, DA field and SA field of the frame 54 transmitted from the master station is 02 (hexadecimal value corresponding to STX in ASCII code, respectively). ), 3, 0.

The slave station 1 51 receives the frame 54, compares the DA field value 3 of the received frame with its own address value 1, and discards the data included in the frame 54 without receiving the data. In addition, the slave station 2 52 also compares the DA field value 3 of the received frame 54 with its own address value 2 and discards all data of the frame 54 without receiving it because the values are different.

The slave station 3 53 compares the DA field value 3 of the received frame 54 with its own address value 3 and thus receives all data of the frame 54. The interrupt request is sent to the CPU to transmit the received data, and the processed data is received from the CPU to the master station. When the slave station 3 53 transmits data to the master station, the STX field, the DA field, and the SA field of the transmission frame 55 become 02, 0, and 3, respectively.

The present invention compares a destination address included in a frame received from a slave station with its own address and receives and processes data when the address is the same, thereby reducing unnecessary CPU data processing and improving performance at the same communication speed. Can use low CPU

Claims (7)

A master station transmitting a communication frame and a plurality of slave stations receiving a frame transmitted from the master station, wherein the plurality of slave stations process the frame transmitted from the communication device and the communication device receiving the frame. In a communication system consisting of a central processing unit, Each slave station has a first register for storing its address; A comparison unit comparing the address stored in the first register with a destination address included in the frame; A second register for storing the frame transmitted from the master station; A counter which receives and stores the data length included in the frame from the second register, and decreases the data length included in the frame at a predetermined interval every time the data included in the frame is stored; A reception buffer for temporarily storing the received frame; If the comparison result of the comparison unit is the same, request processing of the received frame to the central processing unit; if the comparison result is different, discard the received frame, and continue until the counter indicates that there is no data to store A control unit configured to determine whether to store the data according to the validity of the reception buffer; And a third register which stores a control state of the control unit and indicates a control progress state of the control unit. delete delete delete 2. The communication system according to claim 1, wherein the control state includes controllability, data discard, data length reception, source address reception, destination address reception, and frame start code value reception. A communication system comprising a slave station receiving a frame from a master station and controlling and transmitting the received frame to a central processing unit, An address comparison step of receiving the frame and comparing a destination address included in the received frame with an address of the slave station; A data processing step of requesting the CPU to process the received frame if the address of the comparison result of the address comparison step is the same, and discarding the received frame if the address of the comparison result is different; Determining whether to store the data according to a validity of a reception buffer temporarily storing the received frame; Storing the control state and indicating the control progress, The data processing step stores the data length included in the frame in a counter, and decreases the value of the counter every time the data included in the frame is received until the counter value indicates that there is no more data. A communication system characterized in that delete

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