KR101137853B1 - A Electro-Luminescence Display Device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting display device capable of preventing deterioration of a driving transistor, and by using two driving transistors and two light emitting elements and alternately driving the two driving transistors to prevent deterioration of the driving transistor. The present invention relates to a light emitting display device.

Light emitting display, deterioration, driving transistor, light emitting device, threshold voltage

Description

A Electro-Luminescence Display Device

1 illustrates a basic pixel structure of a conventional active matrix type light emitting display device.

2 is a view showing a light emitting display device according to an embodiment of the present invention;

3 is a diagram illustrating a circuit configuration of the pixel of FIG. 2.

4A and 4B illustrate timings of various signals supplied to the pixels of FIG. 3.

5 is a view for comparing the degree of degradation of the driving transistor provided in the light emitting display device of the present invention and the driving transistor provided in the conventional light emitting display device.

6 is a diagram illustrating another circuit configuration of the pixel of FIG. 2.

7A and 7B illustrate timings of various signals supplied to the pixels of FIG. 6.

8 is a view illustrating a shape of a light emitting device provided in the pixel of FIG. 2;

* Explanation of symbols on the main parts of the drawings

200: display unit 201: gate driver

202: Data Driver PXL: Pixel

SL: Scan Line DL: Data Line

RS: reset lines L1 to L4: first to fourth power lines

The present invention relates to a light emitting display device, and more particularly, to a light emitting display device that can prevent deterioration of a driving transistor.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Such flat panel displays include a liquid crystal display, a field emission display, a plasma display panel, an electroluminescence display, and the like.

Recently, studies are being actively conducted to increase the display quality of such a flat panel display device and to attempt to make a large screen. Among them, the electroluminescent display device is a self-light emitting device that emits light by itself. The electroluminescent display displays a video image by exciting a fluorescent material using carriers such as electrons and holes. The electroluminescent display is divided into inorganic electroluminescent display and light emitting display according to the material used. The light emitting display device is driven at a voltage of about 5 to 20V lower than that of an inorganic electroluminescent display device requiring a high voltage of 100 to 200V, thereby enabling direct current low voltage driving. In addition, the light emitting display device has excellent features such as a wide viewing angle, high-speed response, and high contrast ratio, so that it is used as a pixel of a graphic display, a pixel of a television image display, or a surface light source. It can be used and is suitable as next generation flat panel display because it is thin, light and good color.

On the other hand, a passive matrix type (Passive matrix type) that does not have a separate thin film transistor is mainly used as a driving method of the light emitting display device.

However, since the passive matrix method has many limited factors such as resolution, power consumption, and lifespan, active matrix type electroluminescent display devices for manufacturing next-generation displays requiring high resolution and large screens have been researched and developed.

1 illustrates a basic pixel structure of a conventional active matrix type light emitting display device.

A basic pixel structure of a conventional active matrix type light emitting display device includes a scan line SL arranged in one direction, a data line DL formed to cross the scan line SL, and A light emitting element OLED formed in each pixel Pixel defined by the scan line SL and the data line DL, and a power line for transmitting a DC voltage to an anode of the light emitting element OLED 110, a switching transistor NTS connected with a gate terminal to the scan line SL, and a drain terminal connected to the data line DL, and a gate terminal connected to a source terminal of the switching transistor NTS. A driving transistor NTD having a drain terminal connected to the cathode of the light emitting device OLED and a source terminal connected to the ground terminal, and a capacitor Cst connected between the gate terminal and the source terminal of the driving transistor NTD. It is.

Here, the switching transistor NTS is turned on in response to the scan signal from the scan line SL to form a current path between its source terminal and the drain terminal, and on the scan line SL. When the voltage is below its threshold voltage (Vth), it maintains the turn-off state. In the turn-on time period of the switching transistor NTS, the data voltage from the data line DL is applied to the gate terminal of the driving transistor NTD through the drain terminal of the switching transistor NTS. On the contrary, in the off time period of the switching transistor NTS, a current path between the source terminal and the drain terminal of the switching transistor NTS is opened so that the data voltage is not applied to the driving transistor NTD.

The driving transistor NTD adjusts the amount of current flowing between its source terminal and the drain terminal according to the data voltage supplied to its gate terminal, thereby emitting the light emitting device OLED at a brightness corresponding to the data voltage. .

The capacitor Cst maintains a constant data voltage applied to the gate terminal of the driving transistor NTD for one frame period and maintains a current applied to the light emitting device OLED for one frame period.

On the other hand, since a data voltage of a certain polarity (positive polarity) is always applied to the gate terminal of the driving transistor NTD, and the source terminal of the driving transistor NTD is grounded, the gate terminal of the driving transistor NTD- The voltage between the source terminals always has a positive polarity. In addition, since the driving transistor is always turned on during the operation of the light emitting display device, a current always flows between the drain and source terminals of the driving transistor.

This causes a problem that the threshold voltage of the driving transistor NTD continuously rises to one polarity. Increasing the threshold voltage of the driving transistor NTD causes a decrease in current supplied to the light emitting device OLED, which in turn lowers the luminance of the light emitting device OLED and degrades image quality. Becomes

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and uses a light emitting display that can prevent deterioration of the driving transistor by using two driving transistors and two light emitting elements and alternately driving the two driving transistors. The purpose is to provide a device.

According to an aspect of the present invention, there is provided a light emitting display device including: first and second light emitting devices that are provided for each pixel and emit light according to an applied current; A first switching element for switching the data voltage from the data line according to the scan signal from the scan line; A first driving switching element connected to a first power line for controlling the amount of the current supplied to the first light emitting element according to the data voltage switched from the first switching element, the source terminal being connected to a first power line for transmitting a first voltage source; ; A second power supply line connected to one side of the first light emitting device and transmitting a second voltage source periodically having a higher potential voltage greater than the first voltage source and a low potential voltage equal to or smaller than the first voltage source; A first reset switching device for turning off the first driving switching device by supplying a third voltage source to the gate terminal of the first driving switching device in response to a reset signal from a reset line; A second switching element for switching the data voltage from the data line according to the scan signal from the scan line; A second driving switching element controlling an amount of the current supplied to the second light emitting element according to the data voltage switched from the second switching element, wherein a source terminal is connected to the first power line; A third power line connected to one side of the second light emitting device and transmitting a fourth voltage source inverted to the second voltage source; And a second reset switching device which turns off the second driving switching device by supplying the third voltage source to the gate terminal of the second driving switching device according to the reset signal from the reset line. do.

In addition, the light emitting display device according to the present invention for achieving the above object is provided for each pixel, the first and second light emitting device for emitting light according to the applied current; A first switching element for switching the data voltage from the data line according to the scan signal from the scan line; A first driving switching element connected to a first power line for controlling the amount of the current supplied to the first light emitting element according to the data voltage switched from the first switching element, the source terminal being connected to a first power line for transmitting a first voltage source; ; A second power supply line connected to one side of the first light emitting device and transmitting a second voltage source periodically having a higher potential voltage greater than the first voltage source and a low potential voltage equal to or smaller than the first voltage source; A second switching element for switching the data voltage from the data line according to the scan signal from the scan line; A second driving switching element controlling the amount of current supplied to the second light emitting element according to the data voltage switched from the second switching element, and a source terminal of which is connected to the first power line; A third power line connected to one side of the second light emitting device and transmitting a third voltage source inverted to the second voltage source; A first reset switching device which turns off the first driving switching device by supplying a fourth voltage source to the gate terminal of the first driving switching device according to the high potential voltage of the third voltage source; And a second reset switching device which turns off the second driving switching device by supplying the fourth voltage source to the gate terminal of the second driving switching device according to the high potential voltage of the second voltage source. It is done.

Hereinafter, a light emitting display device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 illustrates a light emitting display device according to an exemplary embodiment of the present invention.

As shown in FIG. 2, a light emitting display device according to an exemplary embodiment of the present invention includes a display unit 200 for displaying an image, scan lines SLs and reset lines RLs of the display unit 200. A gate driver 201 for driving and a data driver 202 for driving the data lines DL of the display unit 200.

Here, the scan lines SL and the data lines DL of the display unit 200 are arranged to vertically cross each other, and each region defined by the scan lines SL and the data line DL includes a pixel. PXL) is formed. The pixel PXL includes a scan signal SS from the scan line SL, a data signal Vdata from the data line DL, a reset signal RS from the reset line RL, and The first to fourth voltages VDD1, VDD2, VSS1, and VSS2 are supplied from the first to fourth power lines L1 to L4 to display an image. The reset line RL is arranged to be parallel to the scan line SL, and the first to fourth power lines L1 to L4 are arranged to be parallel to the data line DL. The first to fourth power lines L1 to L4 are connected to a power supply unit (not shown), and the first to fourth voltages VDD1, VDD2, VSS1, and VSS2 output from the power supply unit are each pixel ( PXL).

Here, the first voltage VDD1 and the second voltage VDD2 are AC voltage sources having a high potential voltage and a low potential voltage at regular intervals. The first voltage VDD1 is inverted to the second voltage VDD2. Has a phase. That is, when the first voltage VDD1 is maintained at the high potential voltage for a period of time, the second voltage VDD2 is maintained at the low potential voltage. The second voltage VDD2 is maintained at a high potential voltage when the first voltage VDD1 is maintained at a low potential voltage for a period of time. For example, the high potential voltage may be a positive voltage, and the low potential voltage may be a negative voltage.

The third voltage VSS1 and the fourth voltage VSS2 are ground voltages, and the third voltage VSS1 and the fourth voltage VSS2 may have the same magnitude or different magnitudes. In this case, the third voltage VSS1 has a value between the high potential voltage and the low potential voltage of the first voltage VDD1 (or the second voltage VDD2). Specifically, the third voltage VSS1 is smaller than the high potential voltage. The third voltage VSS1 is equal to or greater than the low potential voltage.

In the light emitting display device according to the exemplary embodiment of the present invention configured as described above, the pixel PXL will be described in more detail as follows.

3 is a diagram illustrating a circuit configuration of the pixel of FIG. 2.

As illustrated in FIG. 3, each pixel PXL includes first and second switching transistors NTS1 and NTS2, first and second driving transistors NTD1 and NTD2, and first and second reset transistors NTR1, NTR2, and first and second light emitting elements OLED2.

That is, each pixel PXL includes six transistors NTS1, NTS2, NTD1, NTD2, NTR1, NTR2 and two light emitting elements OLED1, OLED2.

The first switching transistor NTS1 is turned on in response to the scan signal SS from the scan line SL to switch the data signal Vdata from the data line DL and to switch the switched data signal Vdata is supplied to the gate terminal of the first driving transistor NTD1. To this end, a gate terminal of the first switching transistor NTS1 is connected to the scan line SL, a drain terminal is connected to the data line DL, and a source terminal of the first driving transistor NTD1 is connected. It is connected to the gate terminal.

The first driving transistor NTD1 controls the amount of current Ids1 supplied to the first light emitting device OLED1 according to the data signal Vdata switched from the first switching transistor NTS1. That is, the first driving transistor NTD1 is turned on according to the data signal Vdata supplied to its gate terminal to form a current path between its drain and source terminals. The first current is controlled by controlling the magnitude of the current Ids1 flowing along the current path according to the magnitude of the supplied data signal Vdata, and supplying the controlled current Ids1 to the first light emitting device OLED1. 1 The light emitting element OLED1 emits light. For this purpose, the gate terminal of the first driving transistor NTD1 is connected to the source terminal of the first switching transistor NTS1, the drain terminal is connected to the cathode of the first light emitting device OLED1, and the source terminal is It is connected to the third power supply line L3 which transmits the third voltage VSS1.

The first reset transistor NTR1 supplies the fourth voltage VSS2 to the gate terminal of the first driving transistor NTD1 in response to the reset signal RS from the reset line RL to drive the first drive. The transistor NTD1 is turned off. For this purpose, a gate terminal of the first reset transistor NTR1 is connected to the reset line RL, a drain terminal is connected to a gate terminal of the first driving transistor NTD1, and a source terminal of the first voltage is connected to the fourth voltage. It is connected to the fourth power supply line L4 that transmits VSS2.

The first light emitting device OLED1 emits light according to the current Ids1 supplied through the first driving transistor NTD1. To this end, the cathode of the first light emitting device OLED1 is connected to the drain terminal of the first driving transistor NTD1, and the anode is connected to the first power line L1 which transmits the first voltage VDD1. .

The second switching transistor NTS2 is turned on in response to the scan signal SS from the scan line SL, thereby switching the data signal Vdata from the data line DL and switching the switched data. The signal Vdata is supplied to the gate terminal of the second driving transistor NTD2. To this end, the gate terminal of the second switching transistor NTS2 is connected to the scan line SL, the drain terminal is connected to the data line DL, and the source terminal of the second driving transistor NTD2 is connected. It is connected to the gate terminal.

The second driving transistor NTD2 controls the amount of current Ids2 supplied to the second light emitting element OLED2 according to the data signal Vdata switched from the second switching transistor NTS2. That is, the second driving transistor NTD2 is turned on according to the data signal Vdata supplied to its gate terminal to form a current path between its drain and source terminals. In addition, the magnitude of the current Ids2 flowing along the current path is controlled according to the magnitude of the supplied data signal Vdata, and the controlled current Ids2 is supplied to the second light emitting device OLED2. 2 The light emitting element OLED2 emits light. For this purpose, the gate terminal of the second driving transistor NTD2 is connected to the source terminal of the second switching transistor NTS2, the drain terminal is connected to the cathode of the second light emitting device OLED2, and the source terminal is It is connected to the third power supply line L3 which transmits the third voltage VSS1.

The second reset transistor NTR2 supplies the fourth voltage VSS2 to the gate terminal of the second driving transistor NTD2 in response to the reset signal RS from the reset line RL to drive the second drive. The transistor NTD2 is turned off. For this purpose, a gate terminal of the second reset transistor NTR2 is connected to the reset line RL, a drain terminal is connected to a gate terminal of the second driving transistor NTD2, and a source terminal of the second voltage is connected to the fourth voltage. It is connected to the fourth power supply line L4 that transmits VSS2.

The second light emitting device OLED2 emits light according to the current Ids2 supplied through the second driving transistor NTD2. To this end, the cathode of the second light emitting element OLED2 is connected to the drain terminal of the second driving transistor NTD2, and the anode is connected to the second power line L2 which transmits the second voltage VDD2. .

The operation of the light emitting display device according to the embodiment of the present invention configured as described above will be described in detail as follows.

4A and 4B illustrate timings of various signals supplied to the pixels of FIG. 3.

First, a case where the third voltage VSS1 and the fourth voltage VSS2 are the same will be described.

As shown in FIGS. 4A and 4B, the scan signal SS and the reset signal RS are output once every frame, and the scan signal SS is first output after every predetermined time and the predetermined time passes. The reset signal RS is output. The data signal Vdata is output in synchronization with the scan signal SS. In addition, the first and second voltages VDD1 and VDD2 are outputted to alternately display the high potential voltage and the low potential voltage for each frame, wherein the first voltage VDD1 is inverted with the second voltage VDD2. Has

Here, the scan signal SS is output in the first period T1 of the first frame, and the output scan signal SS is supplied to the gate terminals of the first and second switching transistors NTS1 and NTS2, respectively. do. Accordingly, the first and second switching transistors NTS1 and NTS2 are turned on in the first period T1. In this case, the data signal Vdata is supplied to the gate terminal of the first driving transistor NTD1 through the turned-on first switching transistor NTS1. Similarly, the data signal Vdata is supplied to the gate terminal of the second driving transistor NTD2 through the turned-on second switching transistor NTS2.

Accordingly, the voltage Vgs1 between the gate terminal and the source terminal of the first driving transistor NTD1 becomes larger than the threshold voltage Vth1 of the first driving transistor NTD1, so that the first driving transistor NTD1 is turned on. -On. In this case, the voltage Vgs1 is stored in the first capacitor C1. Here, the voltage Vgs1 may be a parasitic capacitor of the first driving transistor NTD1, that is, a parasitic formed between the gate terminal and the source terminal of the first driving transistor NTD1, even if the first capacitor C1 is not used. Stored in the capacitor. That is, in the present invention, the first capacitor C1 may not be used.

Similarly, the voltage Vgs2 between the gate terminal and the source terminal of the second driving transistor NTD2 is greater than the threshold voltage Vth2 of the second driving transistor NTD2, so that the second driving transistor NTD2 is turned on. -On. In this case, the voltage Vgs2 is stored in the second capacitor C2. Here, the voltage Vgs2 is a parasitic capacitor of the second driving transistor NTD2, that is, a parasitic formed between the gate terminal and the source terminal of the second driving transistor NTD2, even when the second capacitor C2 is not used. Stored in the capacitor. That is, in the present invention, the second capacitor C2 may not be used.

Meanwhile, since the first voltage VDD1 is maintained at the high potential voltage and the second voltage VDD2 is maintained at the low potential voltage during the first frame including the first period T1, the first driving transistor ( Current Ids1 flows between the drain-source terminal of NTD1, and no current Ids2 flows between the drain-source terminal of the second driving transistor NTD2. If this is explained in more detail as follows.

As described above, since the first voltage VDD1 is maintained at a high potential voltage in the first period T1, the first voltage VDD1 is larger than the third voltage VSS1 in this period. Has Therefore, the first light emitting device OLED1 connected between the first voltage VDD1 and the third voltage VSS1 is biased in the forward direction. Therefore, the current Ids1 may flow through the first light emitting device OLED1. This current Ids1 is a current Ids1 flowing between the drain and source terminals of the first driving transistor NTD1.

In contrast, since the second voltage VDD2 is maintained at the low potential voltage in the first period T1, the second voltage VDD2 has a voltage value smaller than the third voltage VSS1 in the period. . Therefore, the second light emitting device OLED2 connected between the second voltage VDD2 and the third voltage VSS1 is biased in the reverse direction. Therefore, the current Ids2 cannot flow through the second light emitting device OLED2. Accordingly, no current Ids2 flows between the drain and source terminals of the second driving transistor NTD2.

As a result, the first light emitting device OLED1 emits light and the second light emitting device OLED2 does not emit light in the first period T1. Thereafter, the first light emitting device OLED1 maintains the light emitting state until the third period T3, and the second light emitting device OLED2 still does not emit light. In addition, the current Ids1 flows in the first driving transistor NTD1 and the current Ids2 does not flow in the second driving transistor NTD2 until the third period T3.

Then, the reset signal RS is output after the half frame period (first to third periods T1 to T3) after the scan signal SS is output, that is, in the fourth period T4. . The reset signal RS is supplied to the gate terminals of the first and second reset transistors NTR1 and NTR2. Accordingly, both the first and second reset transistors NTR1 and NTR2 are turned on.

As the first reset transistor NTR1 is turned on, the fourth voltage VSS2 is supplied to the gate terminal of the first driving transistor NTD1 through the turned-on first reset transistor NTR1. That is, the gate terminal of the first driving transistor NTD1 is maintained at the fourth voltage VSS2 and the source terminal is maintained at the third voltage VSS1. Meanwhile, as described above, since the third voltage VSS1 and the fourth voltage VSS2 have the same magnitude, the gate-source terminal voltage Vgs1 of the first driving transistor NTD1 is set to 0V. maintain. That is, the voltage Vgs1 of the gate-source terminal of the first driving transistor NTD1 becomes smaller than its threshold voltage Vth1 from the fourth period T4 to the sixth period T6. In other words, the gate-source terminal voltage Vgs1 of the first reset transistor NTR1 is set to the threshold voltage during the next 1/2 frame period of the first frame (fourth to sixth periods T4 to T6). Is kept smaller than Vth1). In this case, the first driving transistor NTD1 is turned off and thus the current path between the drain and source terminals of the first driving transistor NTD1 is turned off so that the current Ids1 does not flow. Therefore, the first light emitting element OLED1 does not emit light during this period.

Similarly, the gate-source terminal voltage Vgs2 of the second reset transistor NTR2 also has its threshold during the next 1/2 frame period of the first frame (fourth to sixth periods T4 to T6). It becomes smaller than the voltage Vth2. Also, during this period, the current path between the drain and source terminals of the second reset transistor NTR2 is turned off. During this period, the second light emitting element OLED2 is still biased in the reverse direction and thus does not emit light.

As a result, the gate-source terminal voltage Vgs1 of the first driving transistor NTD1 becomes the threshold voltage Vth1 during the first 1/2 period of the first frame (first to third periods T1 to T3). It is kept higher and lower than the threshold voltage Vth1 for the next 1/2 period (for the fourth to sixth periods T4 to T6). In addition, while the first driving transistor NTD1 is biased in the forward direction during this one frame, the current path between the drain and source terminals of the first driving transistor NTD1 is opened as soon as the reset signal RS is output. The current Ids1 flowing between the drain and source terminals of the first driving transistor NTD1 is generated only for a period before the reset signal RS is output (for a half period of the first frame). By the current Ids1, the first light emitting element OLED1 emits light for the first half of the first frame. That is, the current Ids1 flows into the first driving transistor NTD1 only for the first half of the first frame and does not flow for the next half of the first frame. As described above, the light emitting display device of the present invention does not drive the first driving transistor NTD1 continuously but drives only the first half of the first frame, and also gates the next half of the first frame. By increasing or decreasing the voltage between the source terminals relative to the threshold voltage Vth1, it is possible to prevent the threshold voltage Vth1 from increasing in either direction.

Meanwhile, the gate-source terminal voltage Vgs2 of the second driving transistor NTD2 is higher than the threshold voltage Vth2 during the 1/2 period of the first frame (first to third periods T3). And lower than the threshold voltage Vth2 for the next 1/2 period (for the fourth to sixth periods T4 to T6). In addition, since the second driving transistor NTD2 is biased in the reverse direction during this one frame, no current Ids2 is generated between the drain and source terminals of the second driving transistor NTD2. That is, the current Ids2 does not flow to the second driving transistor NTD2 for one frame.

Thereafter, when the first frame is completed as described above, the second frame (seventh through twelfth periods T7 through T12) begins. The operation of the circuit during this second frame is the same as the operation of the circuit of the first frame. However, as shown in FIG. 4A, the first voltage VDD1 is maintained at a low potential voltage and the second voltage VDD2 is maintained as a high potential voltage source during this second frame. Therefore, in this period, the first voltage VDD1 has a smaller voltage value than the third voltage VSS1. Therefore, the first light emitting device OLED1 connected between the first voltage VDD1 and the third voltage VSS1 is biased in the reverse direction during the second frame (for the seventh to twelfth periods T7 to T12). . Therefore, the current Ids1 cannot flow through the first light emitting device OLED1 during the second frame. Accordingly, the current Ids1 does not flow between the drain and source terminals of the first driving transistor NTD1.

Meanwhile, during the second frame, the second voltage VDD2 has a larger value than the third voltage VSS1. Therefore, the second light emitting device OLED2 connected between the second voltage VDD2 and the third voltage VSS1 is biased in the forward direction. Therefore, current Ids2 is generated between the drain and source terminals of the second driving transistor NTD2, and the current Ids2 emits the second light emitting element OLED2. Since the second driving transistor NTD2 opens its current drain-source terminal at the time when the reset signal RS is output, the second driving transistor NTD2 has the first driving period of the second frame in the second driving transistor NTD2. Current Ids2 flows up to. That is, the second driving transistor NTD2 flows the current Ids2 through its drain-source terminal during the seventh through ninth periods T7 through T9. This current Ids2 is supplied to the second light emitting device OLED2 to emit the second light emitting device OLED2. The second driving transistor NTD2 is applied to the reset signal RS from the second reset transistor NTR2 for the next 1/2 period of the second frame (for the tenth to twelfth periods T10 to T12). By turning it off. Therefore, the second light emitting element OLED2 does not emit light during the tenth to twelfth periods T10 to T12.

As a result, the first driving transistor NTD1 operates in the same manner as the second driving transistor NTD2 during the first frame. The second driving transistor NTD2 operates in the same manner as the first driving transistor NTD1 during the first frame during the second frame.

In addition, during the second frame, the first switching transistor NTS1 operates the same as the first switching transistor NTS1 during the first frame, and the second reset transistor NTR2 during the second frame during the first frame. The same operation as the second reset transistor NTR2 is performed.

As a result, the gate-source terminal voltage Vgs2 of the second driving transistor NTD2 becomes the threshold voltage Vth2 during the first 1/2 period of the second frame (seventh through ninth periods T7 through T9). It is kept higher and lower than the threshold voltage Vth2 for the next 1/2 period (during the tenth to twelfth periods T10 to T12). In addition, while the second driving transistor NTD2 is forward biased during the second frame, the current path between the drain and source terminals of the second driving transistor NTD2 is opened at the moment when the reset signal RS is output. The current Ids2 flowing between the drain and source terminals of the second driving transistor NTD2 is generated only during the period before the reset signal RS is output (for half of the second frame). By this current Ids2, the second light emitting element OLED2 emits light for the first half of the second frame. That is, the current Ids2 flows in the second driving transistor NTD2 only for the first half period of the second frame and does not flow for the next half period. As described above, the light emitting display device of the present invention does not continuously drive the second driving transistor NTD2, but only drives the first half of the second frame, and also gates the next half of the second frame. It is possible to prevent the threshold voltage Vth2 from increasing in either direction by allowing the voltage between the source terminals to increase or decrease relative to the threshold voltage Vth2.

Meanwhile, the gate-source terminal voltage Vgs1 of the first driving transistor NTD1 is greater than the threshold voltage Vth1 during the 1/2 period of the second frame (for the seventh to ninth periods T7 to T9). It is kept high and lower than the threshold voltage Vth1 for the next 1/2 period (during the tenth to twelfth periods T10 to T12). In addition, since the first driving transistor NTD1 is biased in the reverse direction during this second frame, no current Ids1 is generated between the drain and source terminals of the first driving transistor NTD1. That is, the current Ids1 does not flow to the first driving transistor NTD1 for one frame.

As described above, the light emitting display device of the present invention drives the first light emitting device OLED1 and the first driving transistor NTD1 for supplying current to the first light emitting device OLED1 in the odd frame, and the even frame. The second light emitting device OLED2 and the second driving transistor NTD2 for supplying current to the second light emitting device OLED2 may be driven to prevent deterioration of the driving transistors NTD1 and NTD2. Specifically, since the current Ids1 flows to the first driving transistor NTD1 for half the frame of the odd-numbered frame, and then the current Ids1 is not supplied for the entire period of the even-numbered frame, the first driving transistor NTD1. ) Has a driving period of half a frame and a rest period of 1.5 frames. In addition, since the current Ids2 flows to the second driving transistor NTD2 during the half frame of the even-numbered frame, and the current Ids2 is not supplied during the entire period of the odd-numbered frame, the second driving transistor NTD2. Fig. 1 shows a driving period of half a frame and a rest period of 1.5 frames. During this idle period, the first and second driving transistors NTD1 and NTD2 restore their own threshold voltages Vth1 and Vth2 by changing the voltages Vgs1 and Vgs2 between their gate and source terminals. In addition, the first and second driving transistors NTD1 and NTD2 are turned off every time the reset signal RS is output, and at this time, their gate-source terminal voltages Vgs1 and Vgs2 have their threshold voltages. Lower than (Vth1, Vth2). By doing so, the first and second driving transistors NTD1 and NTD2 are prevented from deterioration.

Meanwhile, referring to one pixel PXL, the pixel PXL displays an image by emitting the first light emitting diode OLED1 in an odd frame, and the pixel PXL emits a second light in an even frame. The image is displayed by emitting the element OLED2.

Hereinafter, an operation in the case where the third voltage VSS1 and the fourth voltage VSS2 are different, that is, when the third voltage VSS1 is greater than the fourth voltage VSS2 will be described in detail.

The operation of the circuit when the third voltage VSS1 is greater than the fourth voltage VSS2 is the same as the operation of the circuit when the third voltage VSS1 is equal to the fourth voltage VSS2. In this case, however, since the third voltage VSS1 is greater than the fourth voltage VSS2, as illustrated in FIG. 4B, the deterioration of the first and second driving transistors NTD1 and NTD2 is more effectively prevented. can do. If this is explained in more detail as follows.

That is, a fourth voltage VSS2 is applied to the gate terminal of the first driving transistor NTD1 while the reset signal RS is output and the first driving transistor NTD1 is turned off. The third voltage VSS1 is applied thereto. At this time, as described above, since the third voltage VSS1 has a higher voltage value than the fourth voltage VSS2, as shown in FIG. 4B, the gate of the first driving transistor NTD1 is reduced. The voltage Vgs1 between the source terminals shows negative polarity.

In other words, when the third voltage VSS1 and the fourth voltage VSS2 have the same magnitude, the voltage Vgs1 between the gate and source terminals of the first driving transistor NTD1 is maintained at 0V, but the third voltage When VSS1 has a larger value than the fourth voltage VSS2, the gate-source terminal voltage Vgs1 of the first driving transistor NTD1 is maintained at a negative polarity lower than 0V. Therefore, when the third voltage VSS1 is set larger than the fourth voltage VSS2, the deterioration of the first driving transistor NTD1 can be prevented more effectively. In this manner, deterioration of the second driving transistor NTD2 can be prevented more effectively.

5 is a view for comparing the degree of deterioration of the driving transistor provided in the light emitting display device of the present invention and the driving transistor provided in the conventional light emitting display device, as shown in FIG. As this elapses, the accumulated voltage due to the data signal Vdata continues to increase, so that the conventional driving transistor is easily degraded by this accumulated voltage. However, the driving transistor of the present invention has a long period of rest and also the gate-source terminal voltages Vgs1 and Vgs2 repeat increase and decrease with respect to the threshold voltages Vth1 and Vth2. As described above, the cumulative voltage repeats the increase and decrease with the frame cycle. Therefore, the present invention can prevent deterioration of the driving transistor.

Meanwhile, in order to achieve the object of the present invention, each pixel PXL may have a structure as follows.

FIG. 6 is a diagram illustrating another circuit configuration of the pixel of FIG. 2.

As illustrated in FIG. 6, each pixel PXL includes first and second switching transistors NTS1 and NTS2, first and second driving transistors NTD1 and NTD2, and first and second reset transistors NTR1, NTR2, and first and second light emitting elements OLED2.

That is, each pixel PXL includes six transistors NTS1, NTS2, NTD1, NTD2, NTR1, NTR2 and two light emitting elements OLED1, OLED2.

Here, the first and second switching transistors NTS1 and NTS2 and the first and second driving transistors NTD1 and NTD2 are the first and second switching transistors NTS1 and NTS2 shown in FIG. Since it is the same as the first and second driving transistors NTD1 and NTD2, description thereof will be omitted. Meanwhile, the first and second reset transistors NTR1 and NTR2 of FIG. 6 will be described below.

The first reset transistor NTR1 turns off the first driving transistor NTD1 by supplying a fourth voltage VSS2 to the gate terminal of the first driving transistor NTD1 in response to the second voltage VDD2. . To this end, the gate terminal of the first reset transistor NTR1 is connected to the second power line L2 which supplies the second voltage VDD2, and the drain terminal of the first reset transistor NTR1 is connected to the gate terminal of the first driving transistor NTD1. The source terminal is connected to a fourth power supply line L4 that transmits the fourth voltage VSS2.

The second reset transistor NTR2 turns off the second driving transistor NTD2 by supplying a fourth voltage VSS2 to the gate terminal of the second driving transistor NTD2 in response to the first voltage VDD1. . To this end, the gate terminal of the second reset transistor NTR2 is connected to the first power line L1 which supplies the first voltage VDD1, and the drain terminal of the second reset transistor NTR2 is connected to the gate terminal of the second driving transistor NTD2. The source terminal is connected to a fourth power supply line L4 that transmits the fourth voltage VSS2. The light emitting display device having such a circuit structure does not need the reset signal RS required to drive the first and second reset transistors NTR1 and NTR2 and the reset line RL for transmitting the same.

The operation of the light emitting display device having the circuit structure configured as described above will be described in detail as follows.

7A and 7B illustrate timings of various signals supplied to the pixel of FIG. 6.

The operation of the light emitting display device having the circuit structure configured as described above is the same as the light emitting display device having the circuit structure of FIG. only. The first reset transistor NTR1 is not turned on by receiving a separate reset signal RS, but is turned on by being supplied with a high potential voltage of the second voltage VDD2. Similarly, the second reset transistor NTR2 is not turned on by receiving a separate reset signal RS, but is turned on by being supplied with a high potential voltage of the first voltage VDD1.

That is, since the first voltage VDD1 is maintained at the high potential voltage and the second voltage VDD2 is kept at the low potential voltage in the first frame, the first voltage VDD2 receives the low potential voltage of the second voltage VDD2. One reset transistor NTR1 remains turned off during the first frame. Therefore, the first reset transistor NTR1 cannot supply the fourth voltage VSS2 to the gate terminal of the first driving transistor NTD1. Therefore, the first driving transistor NTD1 receives the switched data signal Vdata from the first switching transistor NTS1 and maintains a turn-on state.

In contrast, the second reset transistor NTR2 supplied with the high potential voltage of the first voltage VDD1 during the first frame maintains the turn-on state for the first frame. Accordingly, the second reset transistor NTR2 supplies the fourth voltage VSS2 to the second driving transistor NTD2 to turn off the second driving transistor NTD2 during the first frame. That is, the fourth voltage VSS2 and the data signal Vdata are simultaneously supplied to the gate terminal of the second driving transistor NTD2 during the first frame, but are turned off due to the fourth voltage VSS2. Maintain state.

As a result, the gate-source voltage Vgs1 of the first driving transistor NTD1 becomes greater than the threshold voltage Vth1 during the first frame, and the gate-source voltage Vgs2 of the second driving transistor NTD2 becomes the threshold voltage. It becomes smaller than (Vth2).

Subsequently, since the first voltage VDD1 is maintained at the low potential voltage and the second voltage VDD2 is maintained at the high potential voltage, the second frame receives the high potential voltage of the second voltage VDD2. One reset transistor NTR1 remains turned on for the second frame. Therefore, during the second frame, the first reset transistor NTR1 supplies the fourth voltage VSS2 to the first driving transistor NTD1 to turn off the first driving transistor NTD1.

In contrast, the first reset transistor NTR1 supplied with the low potential voltage of the second voltage VDD2 during the second frame maintains a turn-off state during the first frame. Thus, the second driving transistor NTD2 is kept turned on.

As a result, the gate-source voltage Vgs1 of the first driving transistor NTD1 decreases below the threshold voltage Vth1 during the second frame, and the gate-source voltage of the second driving transistor NTD2 is the threshold voltage Vth. Increases)

Meanwhile, as described above, during the first frame, the first light emitting device OLED1 is biased in the forward direction, the second light emitting device OLED2 is biased in the reverse direction, and the first driving transistor NTD1 is turned on. Since the ON state is maintained, the first light emitting device OLED1 emits light during the first frame.

Here, when the first and second driving transistors NTD1 and NTD2 are turned off, the change of the voltages Vgs1 and Vgs2 between their gate and source terminals will be described as follows.

That is, when the third voltage VSS1 and the fourth voltage VSS2 have the same magnitude, as shown in FIG. 7A, voltages between the gate and source terminals of the first and second driving transistors NTD1 and NTD2 are shown. (Vgs) is kept at 0V. When the third voltage VSS1 has a greater value than the fourth voltage VSS2, the gate-source terminal voltage Vgs of the first and second driving transistors NTD1 and NTD2 is negative. Is maintained. In this case, the first and second driving transistors NTD1 and NTD2 are turned off in synchronization with the first and second voltages VDD2 that change into high potential voltages and low potential voltages for each frame. The gate-source voltages Vgs1 and Vgs2 of the two driving transistors NTD1 and NTD2 also become larger or smaller than the threshold voltages Vth1 and Vth2 for each frame. Accordingly, currents Ids1 and Ids2 flow through the first and second driving transistors NTD1 and NTD2 at one frame. Specifically, the current Ids1 flows only in the first driving transistor NTD1 in the odd frame, and the current Ids2 flows in the second driving transistor NTD2 in the even frame.

As a result, the first and second driving transistors NTD1 and NTD2 alternate between driving periods of one frame and rest periods of one frame.

Meanwhile, the first and second voltages VDD1 and VDD2 may be changed into high potential voltages and low potential voltages based on the nth frame (n is an integer greater than 1).

In the light emitting display device having such a configuration, as described above, since two light emitting devices are provided in one pixel PXL, it is preferable to manufacture the light emitting device in the following shape.

8 is a view illustrating a shape of a light emitting device provided in the pixel of FIG. 2.

That is, as shown in FIG. 8A, the first and second light emitting devices OLED1 and OLED2 are formed in a rectangular shape, and the first light emitting device OLED1 having such a shape is one pixel PXL. ) And a second light emitting device OLED2 is disposed below the pixel PXL.

In addition, as shown in FIG. 8B, the first and second light emitting devices OLED1 and OLED2 are formed in a rectangular shape, and the second light emitting device OLED2 having such a shape is one pixel PXL. ) Is disposed on the left side, and the second light emitting element OLED2 is disposed on the right side of the pixel PXL.

In addition, as shown in FIG. 8C, the first and second light emitting devices OLED1 and OLED2 have a 'U' shape, and the first light emitting device OLED1 having such a shape has one pixel. The light emitting diode OLED2 is disposed above the PXL, and the second light emitting device OLED2 is disposed below the pixel PXL. In detail, the first and second light emitting devices OLED1 and OLED2 include a plurality of vertical parts facing each other at predetermined intervals, and a connection part connecting one side of the vertical parts. When the first light emitting device OLED1 and the second light emitting device OLED2 are provided in one pixel PXL, the vertical portion of the first light emitting device OLED1 is perpendicular to the second light emitting device OLED2. Located between the divisions.

In addition, as shown in FIG. 8D, the first and second light emitting devices OLED1 and OLED2 have an 'E' shape, and the first light emitting device OLED1 having such a shape has one pixel. The second light emitting element OLED2 is disposed on the left side of the pixel PXL and disposed on the right side of the pixel PXL. In detail, the first and second light emitting devices OLED1 and OLED2 are formed of a plurality of horizontal parts facing each other at predetermined intervals and a connection part connecting one side of the horizontal parts. When the first light emitting device OLED1 and the second light emitting device OLED2 are provided in one pixel PXL, the horizontal portion of the first light emitting device OLED1 is horizontal to the second light emitting device OLED2. Located between the divisions.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The light emitting display device according to the present invention as described above has the following advantages.

Each pixel included in the light emitting display device of the present invention has two light emitting elements. In addition, each pixel includes two driving transistors for alternately driving the two light emitting elements at regular intervals. Since the two driving transistors are alternately driven, one driving transistor has a rest period while one driving transistor is driven. In this idle period, the driving transistor restores its threshold voltage. Therefore, the driving transistor of the light emitting display device of the present invention is a frame

Almost no deterioration occurs.

Claims (16)

First and second light emitting devices disposed in each pixel and emitting light according to an applied current; A first switching element for switching the data voltage from the data line according to the scan signal from the scan line; A first driving switching element connected to a first power line for controlling the amount of the current supplied to the first light emitting element according to the data voltage switched from the first switching element, and having a source terminal transmitting a first voltage ; A second power line connected to one side of the first light emitting device and transmitting a second voltage having a high potential voltage greater than the first voltage and a low potential voltage periodically equal to or less than the first voltage; A first reset switching device which turns off the first driving switching device by supplying a third voltage to the gate terminal of the first driving switching device according to a reset signal from a reset line; A second switching element for switching the data voltage from the data line according to the scan signal from the scan line; A second driving switching element controlling an amount of the current supplied to the second light emitting element according to the data voltage switched from the second switching element, wherein a source terminal is connected to the first power line; A third power line connected to one side of the second light emitting device and transmitting a fourth voltage inverted to the second voltage; And, A second reset switching device for turning off the second driving switching device by supplying the third voltage to a gate terminal of the second driving switching device in response to a reset signal from the reset line; The first and second light emitting devices each have an E-shape consisting of a plurality of horizontal parts spaced apart from each other and a connection part connecting one side of the horizontal parts; The first light emitting element is disposed on the left side of the pixel, and the second light emitting element is disposed on the right side of the pixel; And the horizontal portion of the first light emitting element is positioned between the horizontal portion of the second light emitting element. The method of claim 1, And the first voltage and the third voltage have the same magnitude. The method of claim 1, And the first voltage is greater than the third voltage. The method of claim 1, And the scan signal and the reset signal are output once in one frame, and the scan signal is output in each frame in a period earlier than the reset signal. The method of claim 4, wherein And the scan signal is output at the beginning of every frame, and the reset signal is output after a half frame period from the time when the scan signal is output. The method of claim 1, And the second and fourth voltages are alternating voltages alternately representing positive and negative voltages at predetermined intervals, and the third voltage is a ground voltage. The method of claim 6, Wherein the polarity of the second voltage and the fourth voltage changes every frame period. The method of claim 1, A first capacitor connected between the gate terminal and the source terminal of the first driving switching device; And, And a second capacitor connected between the gate terminal and the source terminal of the second driving switching element. delete First and second light emitting devices disposed in each pixel and emitting light according to an applied current; A first switching element for switching the data voltage from the data line according to the scan signal from the scan line; A first driving switching element connected to a first power line for controlling the amount of the current supplied to the first light emitting element according to the data voltage switched from the first switching element, and having a source terminal transmitting a first voltage ; A second power line connected to one side of the first light emitting device and transmitting a second voltage having a high potential voltage greater than the first voltage and a low potential voltage periodically equal to or less than the first voltage; A second switching element for switching the data voltage from the data line according to the scan signal from the scan line; A second driving switching element controlling an amount of the current supplied to the second light emitting element according to the data voltage switched from the second switching element, wherein a source terminal is connected to the first power line; A third power line connected to one side of the second light emitting device and transmitting a third voltage inverted to the second voltage; A first reset switching device which turns off the first driving switching device by supplying a fourth voltage to the gate terminal of the first driving switching device according to the high potential voltage of the third voltage; And, And a second reset switching device which turns off the second driving switching device by supplying the fourth voltage to the gate terminal of the second driving switching device according to the high potential voltage of the second voltage. Display. 11. The method of claim 10, The first and fourth voltages have the same magnitude as each other. 11. The method of claim 10, And the first voltage is greater than the fourth voltage. 11. The method of claim 10, And the second and third voltages are alternating voltages alternately representing positive and negative voltages at predetermined intervals, and the fourth voltage is a ground voltage. The method of claim 13, Wherein the polarity of the second voltage and the third voltage changes at a frame period. 11. The method of claim 10, A first capacitor connected between the gate terminal and the source terminal of the first driving switching device; And, And a second capacitor connected between the gate terminal and the source terminal of the second driving switching element. 11. The method of claim 10, And the first light emitting element and the second light emitting element have any one of a rectangular shape, a U shape, and an E shape.

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